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This pushes the platform data for the U300 COH901318
DMA controller down into the driver and cleans up in the <mach/*> namespace for the U300 platform. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.10 (GNU/Linux) iQIcBAABAgAGBQJQ/pQaAAoJEEEQszewGV1z80kP/joeZo37gp+TfkjL5X+BZDb5 O05Q+Ic70t7u80WjACX6vl7YzeRoK8Z9aiNYpDbHT40RuRKTiGH8DLOmYsjxqXg0 LpqTm+RoLlgrrrOw4nwdN7nE/2eUF5SuidhCUfueZlkTQJLdPWDO0n/fBHR05CGM WovRiNtqJSS9X5JrNjQT19oZDpqsY/mvygAV0usiiWC4qxUQFo0ZaT4jis/UeKCF RD/UsILTRe86Q2UGr+XPp45UihqZ4qH187cZMPWr6FZyeIu24vGo7ew+R4KEjVEz xE6NGkqnYl4LiW+K2Y0TYyN4TnhaaIi4/iSVZxiLKsTvE+LWxrv+4cIU4AUQsoY+ XllWkX1aS+zWaeFOwc6EPuhZFxdkmlGRsz8oqOh0kqswtIiM9wCRgWGCuFcns//A N1+OAC5kK9QlrLWoJnnND/SYsl97GhwySqMLL1FgIjTw3CtseqNfv3LjeyNRKIVT jNX6b6Gc/EOOzZFrAMMvinpaFzgnsWp5xohb7EclKevfArsttrlm80fBnbSnq5lA FzFH/9fi8ca2Lu9hoakNHnTFtx9d5qBU8gPDCwsRGb1gHfmlCQsqrVxSvTVyKOjN ZQfeGNfPdddeKvvo/1l1tTuWzMOMY+AIhfWJGrkUvhlykjDsD4M0m4gKnfMnZeUY zWQv3rJU9L76oGhEtmKZ =IGqm -----END PGP SIGNATURE----- Merge tag 'coh901318-for-arm-soc' of http://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson into next/drivers This pushes the platform data for the U300 COH901318 DMA controller down into the driver and cleans up in the <mach/*> namespace for the U300 platform. * tag 'coh901318-for-arm-soc' of http://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson: dma: coh901318: cut down on platform data abstraction dma: coh901318: merge header files dma: coh901318: push definitions into driver dma: coh901318: push header down into the DMA subsystem dma: coh901318: skip hard-coded addresses dma: coh901318: remove hardcoded target addresses dma: coh901318: push platform data into driver dma: coh901318: create a proper platform data file Signed-off-by: Olof Johansson <olof@lixom.net> Conflicts: arch/arm/mach-u300/core.c
This commit is contained in:
Olof Johansson
commit
4324332213
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Load Diff
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@ -1,60 +0,0 @@
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/*
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*
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* arch/arm/mach-u300/include/mach/dma_channels.h
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*
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*
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* Copyright (C) 2007-2012 ST-Ericsson
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* License terms: GNU General Public License (GPL) version 2
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* Map file for the U300 dma driver.
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* Author: Per Friden <per.friden@stericsson.com>
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*/
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#ifndef DMA_CHANNELS_H
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#define DMA_CHANNELS_H
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#define U300_DMA_MSL_TX_0 0
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#define U300_DMA_MSL_TX_1 1
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#define U300_DMA_MSL_TX_2 2
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#define U300_DMA_MSL_TX_3 3
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#define U300_DMA_MSL_TX_4 4
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#define U300_DMA_MSL_TX_5 5
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#define U300_DMA_MSL_TX_6 6
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#define U300_DMA_MSL_RX_0 7
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#define U300_DMA_MSL_RX_1 8
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#define U300_DMA_MSL_RX_2 9
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#define U300_DMA_MSL_RX_3 10
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#define U300_DMA_MSL_RX_4 11
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#define U300_DMA_MSL_RX_5 12
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#define U300_DMA_MSL_RX_6 13
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#define U300_DMA_MMCSD_RX_TX 14
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#define U300_DMA_MSPRO_TX 15
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#define U300_DMA_MSPRO_RX 16
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#define U300_DMA_UART0_TX 17
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#define U300_DMA_UART0_RX 18
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#define U300_DMA_APEX_TX 19
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#define U300_DMA_APEX_RX 20
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#define U300_DMA_PCM_I2S0_TX 21
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#define U300_DMA_PCM_I2S0_RX 22
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#define U300_DMA_PCM_I2S1_TX 23
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#define U300_DMA_PCM_I2S1_RX 24
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#define U300_DMA_XGAM_CDI 25
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#define U300_DMA_XGAM_PDI 26
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#define U300_DMA_SPI_TX 27
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#define U300_DMA_SPI_RX 28
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#define U300_DMA_GENERAL_PURPOSE_0 29
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#define U300_DMA_GENERAL_PURPOSE_1 30
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#define U300_DMA_GENERAL_PURPOSE_2 31
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#define U300_DMA_GENERAL_PURPOSE_3 32
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#define U300_DMA_GENERAL_PURPOSE_4 33
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#define U300_DMA_GENERAL_PURPOSE_5 34
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#define U300_DMA_GENERAL_PURPOSE_6 35
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#define U300_DMA_GENERAL_PURPOSE_7 36
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#define U300_DMA_GENERAL_PURPOSE_8 37
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#define U300_DMA_UART1_TX 38
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#define U300_DMA_UART1_RX 39
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#define U300_DMA_DEVICE_CHANNELS 32
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#define U300_DMA_CHANNELS 40
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#endif /* DMA_CHANNELS_H */
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@ -1,267 +0,0 @@
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/*
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*
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* include/linux/coh901318.h
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*
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*
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* Copyright (C) 2007-2009 ST-Ericsson
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* License terms: GNU General Public License (GPL) version 2
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* DMA driver for COH 901 318
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* Author: Per Friden <per.friden@stericsson.com>
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*/
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#ifndef COH901318_H
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#define COH901318_H
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#include <linux/device.h>
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#include <linux/dmaengine.h>
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#define MAX_DMA_PACKET_SIZE_SHIFT 11
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#define MAX_DMA_PACKET_SIZE (1 << MAX_DMA_PACKET_SIZE_SHIFT)
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/**
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* struct coh901318_lli - linked list item for DMAC
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* @control: control settings for DMAC
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* @src_addr: transfer source address
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* @dst_addr: transfer destination address
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* @link_addr: physical address to next lli
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* @virt_link_addr: virtual address of next lli (only used by pool_free)
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* @phy_this: physical address of current lli (only used by pool_free)
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*/
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struct coh901318_lli {
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u32 control;
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dma_addr_t src_addr;
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dma_addr_t dst_addr;
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dma_addr_t link_addr;
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void *virt_link_addr;
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dma_addr_t phy_this;
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};
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/**
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* struct coh901318_params - parameters for DMAC configuration
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* @config: DMA config register
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* @ctrl_lli_last: DMA control register for the last lli in the list
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* @ctrl_lli: DMA control register for an lli
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* @ctrl_lli_chained: DMA control register for a chained lli
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*/
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struct coh901318_params {
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u32 config;
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u32 ctrl_lli_last;
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u32 ctrl_lli;
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u32 ctrl_lli_chained;
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};
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/**
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* struct coh_dma_channel - dma channel base
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* @name: ascii name of dma channel
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* @number: channel id number
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* @desc_nbr_max: number of preallocated descriptors
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* @priority_high: prio of channel, 0 low otherwise high.
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* @param: configuration parameters
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* @dev_addr: physical address of periphal connected to channel
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*/
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struct coh_dma_channel {
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const char name[32];
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const int number;
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const int desc_nbr_max;
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const int priority_high;
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const struct coh901318_params param;
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const dma_addr_t dev_addr;
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};
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/**
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* dma_access_memory_state_t - register dma for memory access
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*
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* @dev: The dma device
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* @active: 1 means dma intends to access memory
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* 0 means dma wont access memory
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*/
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typedef void (*dma_access_memory_state_t)(struct device *dev,
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bool active);
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/**
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* struct powersave - DMA power save structure
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* @lock: lock protecting data in this struct
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* @started_channels: bit mask indicating active dma channels
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*/
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struct powersave {
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spinlock_t lock;
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u64 started_channels;
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};
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/**
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* struct coh901318_platform - platform arch structure
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* @chans_slave: specifying dma slave channels
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* @chans_memcpy: specifying dma memcpy channels
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* @access_memory_state: requesting DMA memory access (on / off)
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* @chan_conf: dma channel configurations
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* @max_channels: max number of dma chanenls
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*/
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struct coh901318_platform {
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const int *chans_slave;
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const int *chans_memcpy;
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const dma_access_memory_state_t access_memory_state;
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const struct coh_dma_channel *chan_conf;
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const int max_channels;
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};
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#ifdef CONFIG_COH901318
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/**
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* coh901318_filter_id() - DMA channel filter function
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* @chan: dma channel handle
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* @chan_id: id of dma channel to be filter out
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*
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* In dma_request_channel() it specifies what channel id to be requested
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*/
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bool coh901318_filter_id(struct dma_chan *chan, void *chan_id);
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#else
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static inline bool coh901318_filter_id(struct dma_chan *chan, void *chan_id)
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{
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return false;
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}
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#endif
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/*
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* DMA Controller - this access the static mappings of the coh901318 dma.
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*
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*/
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#define COH901318_MOD32_MASK (0x1F)
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#define COH901318_WORD_MASK (0xFFFFFFFF)
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/* INT_STATUS - Interrupt Status Registers 32bit (R/-) */
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#define COH901318_INT_STATUS1 (0x0000)
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#define COH901318_INT_STATUS2 (0x0004)
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/* TC_INT_STATUS - Terminal Count Interrupt Status Registers 32bit (R/-) */
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#define COH901318_TC_INT_STATUS1 (0x0008)
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#define COH901318_TC_INT_STATUS2 (0x000C)
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/* TC_INT_CLEAR - Terminal Count Interrupt Clear Registers 32bit (-/W) */
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#define COH901318_TC_INT_CLEAR1 (0x0010)
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#define COH901318_TC_INT_CLEAR2 (0x0014)
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/* RAW_TC_INT_STATUS - Raw Term Count Interrupt Status Registers 32bit (R/-) */
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#define COH901318_RAW_TC_INT_STATUS1 (0x0018)
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#define COH901318_RAW_TC_INT_STATUS2 (0x001C)
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/* BE_INT_STATUS - Bus Error Interrupt Status Registers 32bit (R/-) */
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#define COH901318_BE_INT_STATUS1 (0x0020)
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#define COH901318_BE_INT_STATUS2 (0x0024)
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/* BE_INT_CLEAR - Bus Error Interrupt Clear Registers 32bit (-/W) */
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#define COH901318_BE_INT_CLEAR1 (0x0028)
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#define COH901318_BE_INT_CLEAR2 (0x002C)
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/* RAW_BE_INT_STATUS - Raw Term Count Interrupt Status Registers 32bit (R/-) */
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#define COH901318_RAW_BE_INT_STATUS1 (0x0030)
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#define COH901318_RAW_BE_INT_STATUS2 (0x0034)
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/*
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* CX_CFG - Channel Configuration Registers 32bit (R/W)
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*/
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#define COH901318_CX_CFG (0x0100)
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#define COH901318_CX_CFG_SPACING (0x04)
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/* Channel enable activates tha dma job */
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#define COH901318_CX_CFG_CH_ENABLE (0x00000001)
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#define COH901318_CX_CFG_CH_DISABLE (0x00000000)
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/* Request Mode */
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#define COH901318_CX_CFG_RM_MASK (0x00000006)
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#define COH901318_CX_CFG_RM_MEMORY_TO_MEMORY (0x0 << 1)
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#define COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY (0x1 << 1)
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#define COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY (0x1 << 1)
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#define COH901318_CX_CFG_RM_PRIMARY_TO_SECONDARY (0x3 << 1)
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#define COH901318_CX_CFG_RM_SECONDARY_TO_PRIMARY (0x3 << 1)
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/* Linked channel request field. RM must == 11 */
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#define COH901318_CX_CFG_LCRF_SHIFT 3
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#define COH901318_CX_CFG_LCRF_MASK (0x000001F8)
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#define COH901318_CX_CFG_LCR_DISABLE (0x00000000)
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/* Terminal Counter Interrupt Request Mask */
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#define COH901318_CX_CFG_TC_IRQ_ENABLE (0x00000200)
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#define COH901318_CX_CFG_TC_IRQ_DISABLE (0x00000000)
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/* Bus Error interrupt Mask */
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#define COH901318_CX_CFG_BE_IRQ_ENABLE (0x00000400)
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#define COH901318_CX_CFG_BE_IRQ_DISABLE (0x00000000)
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/*
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* CX_STAT - Channel Status Registers 32bit (R/-)
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*/
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#define COH901318_CX_STAT (0x0200)
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#define COH901318_CX_STAT_SPACING (0x04)
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#define COH901318_CX_STAT_RBE_IRQ_IND (0x00000008)
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#define COH901318_CX_STAT_RTC_IRQ_IND (0x00000004)
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#define COH901318_CX_STAT_ACTIVE (0x00000002)
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#define COH901318_CX_STAT_ENABLED (0x00000001)
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/*
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* CX_CTRL - Channel Control Registers 32bit (R/W)
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*/
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#define COH901318_CX_CTRL (0x0400)
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#define COH901318_CX_CTRL_SPACING (0x10)
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/* Transfer Count Enable */
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#define COH901318_CX_CTRL_TC_ENABLE (0x00001000)
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#define COH901318_CX_CTRL_TC_DISABLE (0x00000000)
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/* Transfer Count Value 0 - 4095 */
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#define COH901318_CX_CTRL_TC_VALUE_MASK (0x00000FFF)
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/* Burst count */
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#define COH901318_CX_CTRL_BURST_COUNT_MASK (0x0000E000)
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#define COH901318_CX_CTRL_BURST_COUNT_64_BYTES (0x7 << 13)
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#define COH901318_CX_CTRL_BURST_COUNT_48_BYTES (0x6 << 13)
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#define COH901318_CX_CTRL_BURST_COUNT_32_BYTES (0x5 << 13)
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#define COH901318_CX_CTRL_BURST_COUNT_16_BYTES (0x4 << 13)
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#define COH901318_CX_CTRL_BURST_COUNT_8_BYTES (0x3 << 13)
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#define COH901318_CX_CTRL_BURST_COUNT_4_BYTES (0x2 << 13)
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#define COH901318_CX_CTRL_BURST_COUNT_2_BYTES (0x1 << 13)
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#define COH901318_CX_CTRL_BURST_COUNT_1_BYTE (0x0 << 13)
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/* Source bus size */
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#define COH901318_CX_CTRL_SRC_BUS_SIZE_MASK (0x00030000)
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#define COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS (0x2 << 16)
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#define COH901318_CX_CTRL_SRC_BUS_SIZE_16_BITS (0x1 << 16)
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#define COH901318_CX_CTRL_SRC_BUS_SIZE_8_BITS (0x0 << 16)
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/* Source address increment */
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#define COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE (0x00040000)
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#define COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE (0x00000000)
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/* Destination Bus Size */
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#define COH901318_CX_CTRL_DST_BUS_SIZE_MASK (0x00180000)
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#define COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS (0x2 << 19)
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#define COH901318_CX_CTRL_DST_BUS_SIZE_16_BITS (0x1 << 19)
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#define COH901318_CX_CTRL_DST_BUS_SIZE_8_BITS (0x0 << 19)
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/* Destination address increment */
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#define COH901318_CX_CTRL_DST_ADDR_INC_ENABLE (0x00200000)
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#define COH901318_CX_CTRL_DST_ADDR_INC_DISABLE (0x00000000)
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/* Master Mode (Master2 is only connected to MSL) */
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#define COH901318_CX_CTRL_MASTER_MODE_MASK (0x00C00000)
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#define COH901318_CX_CTRL_MASTER_MODE_M2R_M1W (0x3 << 22)
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#define COH901318_CX_CTRL_MASTER_MODE_M1R_M2W (0x2 << 22)
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#define COH901318_CX_CTRL_MASTER_MODE_M2RW (0x1 << 22)
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#define COH901318_CX_CTRL_MASTER_MODE_M1RW (0x0 << 22)
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/* Terminal Count flag to PER enable */
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#define COH901318_CX_CTRL_TCP_ENABLE (0x01000000)
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#define COH901318_CX_CTRL_TCP_DISABLE (0x00000000)
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/* Terminal Count flags to CPU enable */
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#define COH901318_CX_CTRL_TC_IRQ_ENABLE (0x02000000)
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#define COH901318_CX_CTRL_TC_IRQ_DISABLE (0x00000000)
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/* Hand shake to peripheral */
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#define COH901318_CX_CTRL_HSP_ENABLE (0x04000000)
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#define COH901318_CX_CTRL_HSP_DISABLE (0x00000000)
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#define COH901318_CX_CTRL_HSS_ENABLE (0x08000000)
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#define COH901318_CX_CTRL_HSS_DISABLE (0x00000000)
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/* DMA mode */
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#define COH901318_CX_CTRL_DDMA_MASK (0x30000000)
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#define COH901318_CX_CTRL_DDMA_LEGACY (0x0 << 28)
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#define COH901318_CX_CTRL_DDMA_DEMAND_DMA1 (0x1 << 28)
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#define COH901318_CX_CTRL_DDMA_DEMAND_DMA2 (0x2 << 28)
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/* Primary Request Data Destination */
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#define COH901318_CX_CTRL_PRDD_MASK (0x40000000)
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#define COH901318_CX_CTRL_PRDD_DEST (0x1 << 30)
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#define COH901318_CX_CTRL_PRDD_SOURCE (0x0 << 30)
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/*
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* CX_SRC_ADDR - Channel Source Address Registers 32bit (R/W)
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*/
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#define COH901318_CX_SRC_ADDR (0x0404)
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#define COH901318_CX_SRC_ADDR_SPACING (0x10)
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/*
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* CX_DST_ADDR - Channel Destination Address Registers 32bit R/W
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*/
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#define COH901318_CX_DST_ADDR (0x0408)
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#define COH901318_CX_DST_ADDR_SPACING (0x10)
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/*
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* CX_LNK_ADDR - Channel Link Address Registers 32bit (R/W)
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*/
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#define COH901318_CX_LNK_ADDR (0x040C)
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#define COH901318_CX_LNK_ADDR_SPACING (0x10)
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#define COH901318_CX_LNK_LINK_IMMEDIATE (0x00000001)
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#endif /* COH901318_H */
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#include <linux/amba/bus.h>
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#include <linux/spi/spi.h>
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#include <linux/amba/pl022.h>
|
||||
#include <linux/platform_data/dma-coh901318.h>
|
||||
#include <linux/err.h>
|
||||
#include <mach/coh901318.h>
|
||||
#include "dma_channels.h"
|
||||
|
||||
/*
|
||||
* The following is for the actual devices on the SSP/SPI bus
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,16 +1,15 @@
|
|||
/*
|
||||
* driver/dma/coh901318_lli.h
|
||||
*
|
||||
* Copyright (C) 2007-2009 ST-Ericsson
|
||||
* Copyright (C) 2007-2013 ST-Ericsson
|
||||
* License terms: GNU General Public License (GPL) version 2
|
||||
* Support functions for handling lli for coh901318
|
||||
* DMA driver for COH 901 318
|
||||
* Author: Per Friden <per.friden@stericsson.com>
|
||||
*/
|
||||
|
||||
#ifndef COH901318_LLI_H
|
||||
#define COH901318_LLI_H
|
||||
#ifndef COH901318_H
|
||||
#define COH901318_H
|
||||
|
||||
#include <mach/coh901318.h>
|
||||
#define MAX_DMA_PACKET_SIZE_SHIFT 11
|
||||
#define MAX_DMA_PACKET_SIZE (1 << MAX_DMA_PACKET_SIZE_SHIFT)
|
||||
|
||||
struct device;
|
||||
|
||||
|
|
@ -24,7 +23,25 @@ struct coh901318_pool {
|
|||
#endif
|
||||
};
|
||||
|
||||
struct device;
|
||||
/**
|
||||
* struct coh901318_lli - linked list item for DMAC
|
||||
* @control: control settings for DMAC
|
||||
* @src_addr: transfer source address
|
||||
* @dst_addr: transfer destination address
|
||||
* @link_addr: physical address to next lli
|
||||
* @virt_link_addr: virtual address of next lli (only used by pool_free)
|
||||
* @phy_this: physical address of current lli (only used by pool_free)
|
||||
*/
|
||||
struct coh901318_lli {
|
||||
u32 control;
|
||||
dma_addr_t src_addr;
|
||||
dma_addr_t dst_addr;
|
||||
dma_addr_t link_addr;
|
||||
|
||||
void *virt_link_addr;
|
||||
dma_addr_t phy_this;
|
||||
};
|
||||
|
||||
/**
|
||||
* coh901318_pool_create() - Creates an dma pool for lli:s
|
||||
* @pool: pool handle
|
||||
|
|
@ -121,4 +138,4 @@ coh901318_lli_fill_sg(struct coh901318_pool *pool,
|
|||
u32 ctrl, u32 ctrl_last,
|
||||
enum dma_transfer_direction dir, u32 ctrl_irq_mask);
|
||||
|
||||
#endif /* COH901318_LLI_H */
|
||||
#endif /* COH901318_H */
|
||||
|
|
@ -11,9 +11,9 @@
|
|||
#include <linux/memory.h>
|
||||
#include <linux/gfp.h>
|
||||
#include <linux/dmapool.h>
|
||||
#include <mach/coh901318.h>
|
||||
#include <linux/dmaengine.h>
|
||||
|
||||
#include "coh901318_lli.h"
|
||||
#include "coh901318.h"
|
||||
|
||||
#if (defined(CONFIG_DEBUG_FS) && defined(CONFIG_U300_DEBUG))
|
||||
#define DEBUGFS_POOL_COUNTER_RESET(pool) (pool->debugfs_pool_counter = 0)
|
||||
|
|
|
|||
72
include/linux/platform_data/dma-coh901318.h
Normal file
72
include/linux/platform_data/dma-coh901318.h
Normal file
|
|
@ -0,0 +1,72 @@
|
|||
/*
|
||||
* Platform data for the COH901318 DMA controller
|
||||
* Copyright (C) 2007-2013 ST-Ericsson
|
||||
* License terms: GNU General Public License (GPL) version 2
|
||||
*/
|
||||
|
||||
#ifndef PLAT_COH901318_H
|
||||
#define PLAT_COH901318_H
|
||||
|
||||
#ifdef CONFIG_COH901318
|
||||
|
||||
/* We only support the U300 DMA channels */
|
||||
#define U300_DMA_MSL_TX_0 0
|
||||
#define U300_DMA_MSL_TX_1 1
|
||||
#define U300_DMA_MSL_TX_2 2
|
||||
#define U300_DMA_MSL_TX_3 3
|
||||
#define U300_DMA_MSL_TX_4 4
|
||||
#define U300_DMA_MSL_TX_5 5
|
||||
#define U300_DMA_MSL_TX_6 6
|
||||
#define U300_DMA_MSL_RX_0 7
|
||||
#define U300_DMA_MSL_RX_1 8
|
||||
#define U300_DMA_MSL_RX_2 9
|
||||
#define U300_DMA_MSL_RX_3 10
|
||||
#define U300_DMA_MSL_RX_4 11
|
||||
#define U300_DMA_MSL_RX_5 12
|
||||
#define U300_DMA_MSL_RX_6 13
|
||||
#define U300_DMA_MMCSD_RX_TX 14
|
||||
#define U300_DMA_MSPRO_TX 15
|
||||
#define U300_DMA_MSPRO_RX 16
|
||||
#define U300_DMA_UART0_TX 17
|
||||
#define U300_DMA_UART0_RX 18
|
||||
#define U300_DMA_APEX_TX 19
|
||||
#define U300_DMA_APEX_RX 20
|
||||
#define U300_DMA_PCM_I2S0_TX 21
|
||||
#define U300_DMA_PCM_I2S0_RX 22
|
||||
#define U300_DMA_PCM_I2S1_TX 23
|
||||
#define U300_DMA_PCM_I2S1_RX 24
|
||||
#define U300_DMA_XGAM_CDI 25
|
||||
#define U300_DMA_XGAM_PDI 26
|
||||
#define U300_DMA_SPI_TX 27
|
||||
#define U300_DMA_SPI_RX 28
|
||||
#define U300_DMA_GENERAL_PURPOSE_0 29
|
||||
#define U300_DMA_GENERAL_PURPOSE_1 30
|
||||
#define U300_DMA_GENERAL_PURPOSE_2 31
|
||||
#define U300_DMA_GENERAL_PURPOSE_3 32
|
||||
#define U300_DMA_GENERAL_PURPOSE_4 33
|
||||
#define U300_DMA_GENERAL_PURPOSE_5 34
|
||||
#define U300_DMA_GENERAL_PURPOSE_6 35
|
||||
#define U300_DMA_GENERAL_PURPOSE_7 36
|
||||
#define U300_DMA_GENERAL_PURPOSE_8 37
|
||||
#define U300_DMA_UART1_TX 38
|
||||
#define U300_DMA_UART1_RX 39
|
||||
|
||||
#define U300_DMA_DEVICE_CHANNELS 32
|
||||
#define U300_DMA_CHANNELS 40
|
||||
|
||||
/**
|
||||
* coh901318_filter_id() - DMA channel filter function
|
||||
* @chan: dma channel handle
|
||||
* @chan_id: id of dma channel to be filter out
|
||||
*
|
||||
* In dma_request_channel() it specifies what channel id to be requested
|
||||
*/
|
||||
bool coh901318_filter_id(struct dma_chan *chan, void *chan_id);
|
||||
#else
|
||||
static inline bool coh901318_filter_id(struct dma_chan *chan, void *chan_id)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* PLAT_COH901318_H */
|
||||
Loading…
Reference in New Issue
Block a user