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spi: spi-mem: Add Realtek SPI-NAND controller
Add a driver for the SPI-NAND controller on the RTL9300 family of devices. The controller supports * Serial/Dual/Quad data with * PIO and DMA data read/write operation * Configurable flash access timing There is a separate ECC controller on the RTL9300 which isn't currently supported (instead we rely on the on-die ECC supported by most SPI-NAND chips). Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Link: https://patch.msgid.link/20241015225434.3970360-4-chris.packham@alliedtelesis.co.nz Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Chris Packham
Mark Brown
parent
eef26f1c61
commit
42d20a6a61
@ -19538,6 +19538,12 @@ S: Maintained
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F: Documentation/devicetree/bindings/net/dsa/realtek.yaml
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F: drivers/net/dsa/realtek/*
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REALTEK SPI-NAND
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M: Chris Packham <chris.packham@alliedtelesis.co.nz>
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S: Maintained
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F: Documentation/devicetree/bindings/spi/realtek,rtl9301-snand.yaml
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F: drivers/spi/spi-realtek-rtl-snand.c
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REALTEK WIRELESS DRIVER (rtlwifi family)
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M: Ping-Ke Shih <pkshih@realtek.com>
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L: linux-wireless@vger.kernel.org
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@ -843,6 +843,17 @@ config SPI_PXA2XX
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config SPI_PXA2XX_PCI
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def_tristate SPI_PXA2XX && PCI && COMMON_CLK
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config SPI_REALTEK_SNAND
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tristate "Realtek SPI-NAND Flash Controller"
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depends on MACH_REALTEK_RTL || COMPILE_TEST
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select REGMAP
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help
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This enables support for the SPI-NAND Flash controller on
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Realtek SoCs.
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This driver does not support generic SPI. The implementation
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only supports the spi-mem interface.
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config SPI_ROCKCHIP
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tristate "Rockchip SPI controller driver"
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depends on ARCH_ROCKCHIP || COMPILE_TEST
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@ -119,6 +119,7 @@ obj-$(CONFIG_SPI_ROCKCHIP) += spi-rockchip.o
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obj-$(CONFIG_SPI_ROCKCHIP_SFC) += spi-rockchip-sfc.o
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obj-$(CONFIG_SPI_RB4XX) += spi-rb4xx.o
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obj-$(CONFIG_MACH_REALTEK_RTL) += spi-realtek-rtl.o
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obj-$(CONFIG_SPI_REALTEK_SNAND) += spi-realtek-rtl-snand.o
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obj-$(CONFIG_SPI_RPCIF) += spi-rpc-if.o
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obj-$(CONFIG_SPI_RSPI) += spi-rspi.o
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obj-$(CONFIG_SPI_RZV2M_CSI) += spi-rzv2m-csi.o
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405
drivers/spi/spi-realtek-rtl-snand.c
Normal file
405
drivers/spi/spi-realtek-rtl-snand.c
Normal file
@ -0,0 +1,405 @@
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// SPDX-License-Identifier: GPL-2.0-only
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#include <linux/completion.h>
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#include <linux/dma-mapping.h>
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#include <linux/interrupt.h>
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#include <linux/mod_devicetable.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/spi-mem.h>
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#define SNAFCFR 0x00
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#define SNAFCFR_DMA_IE BIT(20)
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#define SNAFCCR 0x04
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#define SNAFWCMR 0x08
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#define SNAFRCMR 0x0c
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#define SNAFRDR 0x10
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#define SNAFWDR 0x14
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#define SNAFDTR 0x18
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#define SNAFDRSAR 0x1c
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#define SNAFDIR 0x20
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#define SNAFDIR_DMA_IP BIT(0)
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#define SNAFDLR 0x24
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#define SNAFSR 0x40
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#define SNAFSR_NFCOS BIT(3)
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#define SNAFSR_NFDRS BIT(2)
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#define SNAFSR_NFDWS BIT(1)
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#define CMR_LEN(len) ((len) - 1)
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#define CMR_WID(width) (((width) >> 1) << 28)
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struct rtl_snand {
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struct device *dev;
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struct regmap *regmap;
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struct completion comp;
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};
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static irqreturn_t rtl_snand_irq(int irq, void *data)
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{
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struct rtl_snand *snand = data;
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u32 val = 0;
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regmap_read(snand->regmap, SNAFSR, &val);
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if (val & (SNAFSR_NFCOS | SNAFSR_NFDRS | SNAFSR_NFDWS))
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return IRQ_NONE;
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regmap_write(snand->regmap, SNAFDIR, SNAFDIR_DMA_IP);
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complete(&snand->comp);
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return IRQ_HANDLED;
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}
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static bool rtl_snand_supports_op(struct spi_mem *mem,
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const struct spi_mem_op *op)
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{
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if (!spi_mem_default_supports_op(mem, op))
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return false;
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if (op->cmd.nbytes != 1 || op->cmd.buswidth != 1)
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return false;
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return true;
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}
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static void rtl_snand_set_cs(struct rtl_snand *snand, int cs, bool active)
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{
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u32 val;
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if (active)
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val = ~(1 << (4 * cs));
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else
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val = ~0;
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regmap_write(snand->regmap, SNAFCCR, val);
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}
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static int rtl_snand_wait_ready(struct rtl_snand *snand)
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{
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u32 val;
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return regmap_read_poll_timeout(snand->regmap, SNAFSR, val, !(val & SNAFSR_NFCOS),
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0, 2 * USEC_PER_MSEC);
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}
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static int rtl_snand_xfer_head(struct rtl_snand *snand, int cs, const struct spi_mem_op *op)
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{
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int ret;
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u32 val, len = 0;
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rtl_snand_set_cs(snand, cs, true);
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val = op->cmd.opcode << 24;
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len = 1;
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if (op->addr.nbytes && op->addr.buswidth == 1) {
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val |= op->addr.val << ((3 - op->addr.nbytes) * 8);
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len += op->addr.nbytes;
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}
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ret = rtl_snand_wait_ready(snand);
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if (ret)
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return ret;
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ret = regmap_write(snand->regmap, SNAFWCMR, CMR_LEN(len));
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if (ret)
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return ret;
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ret = regmap_write(snand->regmap, SNAFWDR, val);
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if (ret)
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return ret;
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ret = rtl_snand_wait_ready(snand);
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if (ret)
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return ret;
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if (op->addr.buswidth > 1) {
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val = op->addr.val << ((3 - op->addr.nbytes) * 8);
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len = op->addr.nbytes;
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ret = regmap_write(snand->regmap, SNAFWCMR,
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CMR_WID(op->addr.buswidth) | CMR_LEN(len));
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if (ret)
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return ret;
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ret = regmap_write(snand->regmap, SNAFWDR, val);
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if (ret)
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return ret;
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ret = rtl_snand_wait_ready(snand);
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if (ret)
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return ret;
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}
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if (op->dummy.nbytes) {
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val = 0;
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ret = regmap_write(snand->regmap, SNAFWCMR,
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CMR_WID(op->dummy.buswidth) | CMR_LEN(op->dummy.nbytes));
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if (ret)
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return ret;
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ret = regmap_write(snand->regmap, SNAFWDR, val);
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if (ret)
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return ret;
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ret = rtl_snand_wait_ready(snand);
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if (ret)
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return ret;
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}
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return 0;
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}
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static void rtl_snand_xfer_tail(struct rtl_snand *snand, int cs)
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{
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rtl_snand_set_cs(snand, cs, false);
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}
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static int rtl_snand_xfer(struct rtl_snand *snand, int cs, const struct spi_mem_op *op)
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{
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unsigned int pos, nbytes;
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int ret;
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u32 val, len = 0;
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ret = rtl_snand_xfer_head(snand, cs, op);
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if (ret)
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goto out_deselect;
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if (op->data.dir == SPI_MEM_DATA_IN) {
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pos = 0;
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len = op->data.nbytes;
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while (pos < len) {
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nbytes = len - pos;
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if (nbytes > 4)
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nbytes = 4;
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ret = rtl_snand_wait_ready(snand);
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if (ret)
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goto out_deselect;
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ret = regmap_write(snand->regmap, SNAFRCMR,
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CMR_WID(op->data.buswidth) | CMR_LEN(nbytes));
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if (ret)
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goto out_deselect;
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ret = rtl_snand_wait_ready(snand);
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if (ret)
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goto out_deselect;
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ret = regmap_read(snand->regmap, SNAFRDR, &val);
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if (ret)
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goto out_deselect;
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memcpy(op->data.buf.in + pos, &val, nbytes);
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pos += nbytes;
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}
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} else if (op->data.dir == SPI_MEM_DATA_OUT) {
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pos = 0;
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len = op->data.nbytes;
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while (pos < len) {
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nbytes = len - pos;
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if (nbytes > 4)
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nbytes = 4;
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memcpy(&val, op->data.buf.out + pos, nbytes);
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pos += nbytes;
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ret = regmap_write(snand->regmap, SNAFWCMR, CMR_LEN(nbytes));
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if (ret)
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goto out_deselect;
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ret = regmap_write(snand->regmap, SNAFWDR, val);
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if (ret)
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goto out_deselect;
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ret = rtl_snand_wait_ready(snand);
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if (ret)
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goto out_deselect;
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}
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}
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out_deselect:
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rtl_snand_xfer_tail(snand, cs);
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if (ret)
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dev_err(snand->dev, "transfer failed %d\n", ret);
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return ret;
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}
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static int rtl_snand_dma_xfer(struct rtl_snand *snand, int cs, const struct spi_mem_op *op)
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{
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int ret;
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dma_addr_t buf_dma;
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enum dma_data_direction dir;
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u32 trig;
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ret = rtl_snand_xfer_head(snand, cs, op);
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if (ret)
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goto out_deselect;
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if (op->data.dir == SPI_MEM_DATA_IN) {
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dir = DMA_FROM_DEVICE;
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trig = 0;
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} else if (op->data.dir == SPI_MEM_DATA_OUT) {
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dir = DMA_TO_DEVICE;
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trig = 1;
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} else {
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ret = -EOPNOTSUPP;
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goto out_deselect;
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}
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buf_dma = dma_map_single(snand->dev, op->data.buf.in, op->data.nbytes, dir);
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ret = dma_mapping_error(snand->dev, buf_dma);
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if (ret)
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goto out_deselect;
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ret = regmap_write(snand->regmap, SNAFDIR, SNAFDIR_DMA_IP);
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if (ret)
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goto out_unmap;
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ret = regmap_update_bits(snand->regmap, SNAFCFR, SNAFCFR_DMA_IE, SNAFCFR_DMA_IE);
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if (ret)
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goto out_unmap;
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reinit_completion(&snand->comp);
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ret = regmap_write(snand->regmap, SNAFDRSAR, buf_dma);
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if (ret)
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goto out_disable_int;
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ret = regmap_write(snand->regmap, SNAFDLR,
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CMR_WID(op->data.buswidth) | (op->data.nbytes & 0xffff));
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if (ret)
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goto out_disable_int;
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ret = regmap_write(snand->regmap, SNAFDTR, trig);
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if (ret)
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goto out_disable_int;
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if (!wait_for_completion_timeout(&snand->comp, usecs_to_jiffies(20000)))
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ret = -ETIMEDOUT;
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if (ret)
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goto out_disable_int;
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out_disable_int:
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regmap_update_bits(snand->regmap, SNAFCFR, SNAFCFR_DMA_IE, 0);
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out_unmap:
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dma_unmap_single(snand->dev, buf_dma, op->data.nbytes, dir);
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out_deselect:
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rtl_snand_xfer_tail(snand, cs);
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if (ret)
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dev_err(snand->dev, "transfer failed %d\n", ret);
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return ret;
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}
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static bool rtl_snand_dma_op(const struct spi_mem_op *op)
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{
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switch (op->data.dir) {
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case SPI_MEM_DATA_IN:
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case SPI_MEM_DATA_OUT:
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return op->data.nbytes > 32;
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default:
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return false;
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}
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}
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static int rtl_snand_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
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{
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struct rtl_snand *snand = spi_controller_get_devdata(mem->spi->controller);
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int cs = spi_get_chipselect(mem->spi, 0);
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dev_dbg(snand->dev, "cs %d op cmd %02x %d:%d, dummy %d:%d, addr %08llx@%d:%d, data %d:%d\n",
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cs, op->cmd.opcode,
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op->cmd.buswidth, op->cmd.nbytes, op->dummy.buswidth,
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op->dummy.nbytes, op->addr.val, op->addr.buswidth,
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op->addr.nbytes, op->data.buswidth, op->data.nbytes);
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if (rtl_snand_dma_op(op))
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return rtl_snand_dma_xfer(snand, cs, op);
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else
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return rtl_snand_xfer(snand, cs, op);
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}
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static const struct spi_controller_mem_ops rtl_snand_mem_ops = {
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.supports_op = rtl_snand_supports_op,
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.exec_op = rtl_snand_exec_op,
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};
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static const struct of_device_id rtl_snand_match[] = {
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{ .compatible = "realtek,rtl9301-snand" },
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{ .compatible = "realtek,rtl9302b-snand" },
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{ .compatible = "realtek,rtl9302c-snand" },
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{ .compatible = "realtek,rtl9303-snand" },
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{},
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};
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MODULE_DEVICE_TABLE(of, rtl_snand_match);
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static int rtl_snand_probe(struct platform_device *pdev)
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{
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struct rtl_snand *snand;
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struct device *dev = &pdev->dev;
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struct spi_controller *ctrl;
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void __iomem *base;
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const struct regmap_config rc = {
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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.cache_type = REGCACHE_NONE,
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};
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int irq, ret;
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ctrl = devm_spi_alloc_host(dev, sizeof(*snand));
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if (!ctrl)
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return -ENOMEM;
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snand = spi_controller_get_devdata(ctrl);
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snand->dev = dev;
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base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(base))
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return PTR_ERR(base);
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snand->regmap = devm_regmap_init_mmio(dev, base, &rc);
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if (IS_ERR(snand->regmap))
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return PTR_ERR(snand->regmap);
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init_completion(&snand->comp);
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irq = platform_get_irq(pdev, 0);
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if (irq < 0)
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return irq;
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ret = dma_set_mask(snand->dev, DMA_BIT_MASK(32));
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if (ret)
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return dev_err_probe(dev, ret, "failed to set DMA mask\n");
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ret = devm_request_irq(dev, irq, rtl_snand_irq, 0, "rtl-snand", snand);
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if (ret)
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return dev_err_probe(dev, ret, "failed to request irq\n");
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ctrl->num_chipselect = 2;
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ctrl->mem_ops = &rtl_snand_mem_ops;
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ctrl->bits_per_word_mask = SPI_BPW_MASK(8);
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ctrl->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_TX_DUAL | SPI_TX_QUAD;
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device_set_node(&ctrl->dev, dev_fwnode(dev));
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return devm_spi_register_controller(dev, ctrl);
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}
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static struct platform_driver rtl_snand_driver = {
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.driver = {
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.name = "realtek-rtl-snand",
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.of_match_table = rtl_snand_match,
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},
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.probe = rtl_snand_probe,
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};
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module_platform_driver(rtl_snand_driver);
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MODULE_DESCRIPTION("Realtek SPI-NAND Flash Controller Driver");
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MODULE_LICENSE("GPL");
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