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MIPS: ptrace: Fix FP context restoration FCSR regression
Fix a floating-point context restoration regression introduced with commit9b26616c8d
("MIPS: Respect the ISA level in FCSR handling") that causes a Floating Point exception and consequently a kernel oops with hard float configurations when one or more FCSR Enable and their corresponding Cause bits are set both at a time via a ptrace(2) call. To do so reinstate Cause bit masking originally introduced with commitb1442d39fa
("MIPS: Prevent user from setting FCSR cause bits") to address this exact problem and then inadvertently removed from the PTRACE_SETFPREGS request with the commit referred above. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: stable@vger.kernel.org # v4.0+ Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13238/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -176,6 +176,7 @@ int ptrace_setfpregs(struct task_struct *child, __u32 __user *data)
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}
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__get_user(value, data + 64);
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value &= ~FPU_CSR_ALL_X;
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fcr31 = child->thread.fpu.fcr31;
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mask = boot_cpu_data.fpu_msk31;
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child->thread.fpu.fcr31 = (value & ~mask) | (fcr31 & mask);
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