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nfp: bpf: add support for atomic add of unknown values
Allow atomic add to be used even when the value is not guaranteed to fit into a 16 bit immediate. This requires the value to be pulled as data, and therefore use of a transfer register and a context swap. Track the information about possible lengths of the value, if it's guaranteed to be larger than 16bits don't generate the code for the optimized case at all. Signed-off-by: Jakub Kicinski <jakub.kicinski@netronome.com> Reviewed-by: Quentin Monnet <quentin.monnet@netronome.com> Reviewed-by: Jiong Wang <jiong.wang@netronome.com> Signed-off-by: Alexei Starovoitov <ast@kernel.org>
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@ -2125,12 +2125,49 @@ static int mem_stx8(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta)
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static int
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mem_xadd(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta, bool is64)
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{
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swreg addra, addrb, off, prev_alu = imm_a(nfp_prog);
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u8 dst_gpr = meta->insn.dst_reg * 2;
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u8 src_gpr = meta->insn.src_reg * 2;
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unsigned int full_add, out;
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swreg addra, addrb, off;
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off = ur_load_imm_any(nfp_prog, meta->insn.off, imm_b(nfp_prog));
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/* We can fit 16 bits into command immediate, if we know the immediate
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* is guaranteed to either always or never fit into 16 bit we only
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* generate code to handle that particular case, otherwise generate
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* code for both.
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*/
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out = nfp_prog_current_offset(nfp_prog);
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full_add = nfp_prog_current_offset(nfp_prog);
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if (meta->insn.off) {
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out += 2;
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full_add += 2;
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}
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if (meta->xadd_maybe_16bit) {
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out += 3;
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full_add += 3;
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}
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if (meta->xadd_over_16bit)
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out += 2 + is64;
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if (meta->xadd_maybe_16bit && meta->xadd_over_16bit) {
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out += 5;
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full_add += 5;
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}
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/* Generate the branch for choosing add_imm vs add */
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if (meta->xadd_maybe_16bit && meta->xadd_over_16bit) {
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swreg max_imm = imm_a(nfp_prog);
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wrp_immed(nfp_prog, max_imm, 0xffff);
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emit_alu(nfp_prog, reg_none(),
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max_imm, ALU_OP_SUB, reg_b(src_gpr));
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emit_alu(nfp_prog, reg_none(),
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reg_imm(0), ALU_OP_SUB_C, reg_b(src_gpr + 1));
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emit_br(nfp_prog, BR_BLO, full_add, meta->insn.off ? 2 : 0);
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/* defer for add */
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}
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/* If insn has an offset add to the address */
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if (!meta->insn.off) {
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addra = reg_a(dst_gpr);
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@ -2144,13 +2181,38 @@ mem_xadd(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta, bool is64)
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addrb = imma_b(nfp_prog);
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}
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wrp_immed(nfp_prog, prev_alu,
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FIELD_PREP(CMD_OVE_DATA, 2) |
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CMD_OVE_LEN |
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FIELD_PREP(CMD_OV_LEN, 0x8 | is64 << 2));
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wrp_reg_or_subpart(nfp_prog, prev_alu, reg_b(src_gpr), 2, 2);
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emit_cmd_indir(nfp_prog, CMD_TGT_ADD_IMM, CMD_MODE_40b_BA, 0,
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addra, addrb, 0, CMD_CTX_NO_SWAP);
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/* Generate the add_imm if 16 bits are possible */
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if (meta->xadd_maybe_16bit) {
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swreg prev_alu = imm_a(nfp_prog);
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wrp_immed(nfp_prog, prev_alu,
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FIELD_PREP(CMD_OVE_DATA, 2) |
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CMD_OVE_LEN |
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FIELD_PREP(CMD_OV_LEN, 0x8 | is64 << 2));
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wrp_reg_or_subpart(nfp_prog, prev_alu, reg_b(src_gpr), 2, 2);
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emit_cmd_indir(nfp_prog, CMD_TGT_ADD_IMM, CMD_MODE_40b_BA, 0,
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addra, addrb, 0, CMD_CTX_NO_SWAP);
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if (meta->xadd_over_16bit)
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emit_br(nfp_prog, BR_UNC, out, 0);
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}
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if (!nfp_prog_confirm_current_offset(nfp_prog, full_add))
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return -EINVAL;
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/* Generate the add if 16 bits are not guaranteed */
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if (meta->xadd_over_16bit) {
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emit_cmd(nfp_prog, CMD_TGT_ADD, CMD_MODE_40b_BA, 0,
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addra, addrb, is64 << 2,
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is64 ? CMD_CTX_SWAP_DEFER2 : CMD_CTX_SWAP_DEFER1);
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wrp_mov(nfp_prog, reg_xfer(0), reg_a(src_gpr));
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if (is64)
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wrp_mov(nfp_prog, reg_xfer(1), reg_a(src_gpr + 1));
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}
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if (!nfp_prog_confirm_current_offset(nfp_prog, out))
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return -EINVAL;
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return 0;
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}
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@ -229,6 +229,8 @@ struct nfp_bpf_reg_state {
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* @pkt_cache.range_start: start offset for associated packet data cache
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* @pkt_cache.range_end: end offset for associated packet data cache
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* @pkt_cache.do_init: this read needs to initialize packet data cache
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* @xadd_over_16bit: 16bit immediate is not guaranteed
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* @xadd_maybe_16bit: 16bit immediate is possible
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* @jmp_dst: destination info for jump instructions
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* @func_id: function id for call instructions
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* @arg1: arg1 for call instructions
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@ -243,6 +245,7 @@ struct nfp_bpf_reg_state {
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struct nfp_insn_meta {
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struct bpf_insn insn;
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union {
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/* pointer ops (ld/st/xadd) */
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struct {
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struct bpf_reg_state ptr;
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struct bpf_insn *paired_st;
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@ -253,8 +256,12 @@ struct nfp_insn_meta {
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s16 range_end;
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bool do_init;
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} pkt_cache;
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bool xadd_over_16bit;
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bool xadd_maybe_16bit;
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};
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/* jump */
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struct nfp_insn_meta *jmp_dst;
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/* function calls */
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struct {
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u32 func_id;
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struct bpf_reg_state arg1;
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@ -414,16 +414,16 @@ nfp_bpf_check_xadd(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta,
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dreg->type);
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return -EOPNOTSUPP;
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}
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if (sreg->type != SCALAR_VALUE ||
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sreg->var_off.value > 0xffff || sreg->var_off.mask > 0xffff) {
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char tn_buf[48];
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tnum_strn(tn_buf, sizeof(tn_buf), sreg->var_off);
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pr_vlog(env, "atomic add not of a small constant scalar: %s\n",
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tn_buf);
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if (sreg->type != SCALAR_VALUE) {
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pr_vlog(env, "atomic add not of a scalar: %d\n", sreg->type);
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return -EOPNOTSUPP;
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}
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meta->xadd_over_16bit |=
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sreg->var_off.value > 0xffff || sreg->var_off.mask > 0xffff;
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meta->xadd_maybe_16bit |=
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(sreg->var_off.value & ~sreg->var_off.mask) <= 0xffff;
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return nfp_bpf_check_ptr(nfp_prog, meta, env, meta->insn.dst_reg);
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}
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@ -48,6 +48,7 @@ const struct cmd_tgt_act cmd_tgt_act[__CMD_TGT_MAP_SIZE] = {
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[CMD_TGT_READ32_SWAP] = { 0x02, 0x5c },
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[CMD_TGT_READ_LE] = { 0x01, 0x40 },
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[CMD_TGT_READ_SWAP_LE] = { 0x03, 0x40 },
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[CMD_TGT_ADD] = { 0x00, 0x47 },
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[CMD_TGT_ADD_IMM] = { 0x02, 0x47 },
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};
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@ -238,6 +238,7 @@ enum cmd_tgt_map {
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CMD_TGT_READ32_SWAP,
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CMD_TGT_READ_LE,
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CMD_TGT_READ_SWAP_LE,
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CMD_TGT_ADD,
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CMD_TGT_ADD_IMM,
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__CMD_TGT_MAP_SIZE,
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};
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@ -252,6 +253,8 @@ enum cmd_mode {
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enum cmd_ctx_swap {
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CMD_CTX_SWAP = 0,
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CMD_CTX_SWAP_DEFER1 = 1,
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CMD_CTX_SWAP_DEFER2 = 2,
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CMD_CTX_NO_SWAP = 3,
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};
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