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crypto: cavium/nitrox - Added support for SR-IOV configuration.
Added support to configure SR-IOV using sysfs interface. Supported VF modes are 16, 32, 64 and 128. Grouped the hardware configuration functions to "nitrox_hal.h" file. Changed driver version to "1.1". Signed-off-by: Srikanth Jampala <Jampala.Srikanth@cavium.com> Reviewed-by: Gadam Sreerama <sgadam@cavium.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
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a788848116
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@ -7,3 +7,5 @@ n5pf-objs := nitrox_main.o \
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nitrox_hal.o \
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nitrox_reqmgr.o \
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nitrox_algs.o
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n5pf-$(CONFIG_PCI_IOV) += nitrox_sriov.o
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@ -25,19 +25,5 @@ int nitrox_process_se_request(struct nitrox_device *ndev,
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struct skcipher_request *skreq);
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void backlog_qflush_work(struct work_struct *work);
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void nitrox_config_emu_unit(struct nitrox_device *ndev);
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void nitrox_config_pkt_input_rings(struct nitrox_device *ndev);
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void nitrox_config_pkt_solicit_ports(struct nitrox_device *ndev);
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void nitrox_config_vfmode(struct nitrox_device *ndev, int mode);
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void nitrox_config_nps_unit(struct nitrox_device *ndev);
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void nitrox_config_pom_unit(struct nitrox_device *ndev);
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void nitrox_config_rand_unit(struct nitrox_device *ndev);
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void nitrox_config_efl_unit(struct nitrox_device *ndev);
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void nitrox_config_bmi_unit(struct nitrox_device *ndev);
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void nitrox_config_bmo_unit(struct nitrox_device *ndev);
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void nitrox_config_lbc_unit(struct nitrox_device *ndev);
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void invalidate_lbc(struct nitrox_device *ndev);
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void enable_pkt_input_ring(struct nitrox_device *ndev, int ring);
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void enable_pkt_solicit_port(struct nitrox_device *ndev, int port);
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#endif /* __NITROX_COMMON_H */
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@ -88,9 +88,25 @@ struct nitrox_bh {
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struct bh_data *slc;
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};
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/* NITROX-V driver state */
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#define NITROX_UCODE_LOADED 0
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#define NITROX_READY 1
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/*
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* NITROX Device states
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*/
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enum ndev_state {
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__NDEV_NOT_READY,
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__NDEV_READY,
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__NDEV_IN_RESET,
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};
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/* NITROX support modes for VF(s) */
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enum vf_mode {
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__NDEV_MODE_PF,
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__NDEV_MODE_VF16,
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__NDEV_MODE_VF32,
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__NDEV_MODE_VF64,
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__NDEV_MODE_VF128,
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};
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#define __NDEV_SRIOV_BIT 0
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/* command queue size */
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#define DEFAULT_CMD_QLEN 2048
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@ -98,7 +114,6 @@ struct nitrox_bh {
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#define CMD_TIMEOUT 2000
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#define DEV(ndev) ((struct device *)(&(ndev)->pdev->dev))
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#define PF_MODE 0
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#define NITROX_CSR_ADDR(ndev, offset) \
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((ndev)->bar_addr + (offset))
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@ -108,13 +123,15 @@ struct nitrox_bh {
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* @list: pointer to linked list of devices
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* @bar_addr: iomap address
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* @pdev: PCI device information
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* @status: NITROX status
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* @state: NITROX device state
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* @flags: flags to indicate device the features
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* @timeout: Request timeout in jiffies
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* @refcnt: Device usage count
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* @idx: device index (0..N)
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* @node: NUMA node id attached
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* @qlen: Command queue length
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* @nr_queues: Number of command queues
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* @mode: Device mode PF/VF
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* @ctx_pool: DMA pool for crypto context
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* @pkt_cmdqs: SE Command queues
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* @msix: MSI-X information
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@ -128,7 +145,8 @@ struct nitrox_device {
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u8 __iomem *bar_addr;
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struct pci_dev *pdev;
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unsigned long status;
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atomic_t state;
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unsigned long flags;
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unsigned long timeout;
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refcount_t refcnt;
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@ -136,6 +154,8 @@ struct nitrox_device {
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int node;
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u16 qlen;
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u16 nr_queues;
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int num_vfs;
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enum vf_mode mode;
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struct dma_pool *ctx_pool;
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struct nitrox_cmdq *pkt_cmdqs;
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@ -173,9 +193,9 @@ static inline void nitrox_write_csr(struct nitrox_device *ndev, u64 offset,
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writeq(value, (ndev->bar_addr + offset));
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}
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static inline int nitrox_ready(struct nitrox_device *ndev)
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static inline bool nitrox_ready(struct nitrox_device *ndev)
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{
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return test_bit(NITROX_READY, &ndev->status);
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return atomic_read(&ndev->state) == __NDEV_READY;
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}
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#endif /* __NITROX_DEV_H */
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@ -256,7 +256,7 @@ void nitrox_config_nps_unit(struct nitrox_device *ndev)
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/* disable ILK interface */
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core_gbl_vfcfg.value = 0;
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core_gbl_vfcfg.s.ilk_disable = 1;
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core_gbl_vfcfg.s.cfg = PF_MODE;
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core_gbl_vfcfg.s.cfg = __NDEV_MODE_PF;
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nitrox_write_csr(ndev, NPS_CORE_GBL_VFCFG, core_gbl_vfcfg.value);
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/* config input and solicit ports */
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nitrox_config_pkt_input_rings(ndev);
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@ -400,3 +400,13 @@ void nitrox_config_lbc_unit(struct nitrox_device *ndev)
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offset = LBC_ELM_VF65_128_INT_ENA_W1S;
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nitrox_write_csr(ndev, offset, (~0ULL));
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}
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void config_nps_core_vfcfg_mode(struct nitrox_device *ndev, enum vf_mode mode)
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{
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union nps_core_gbl_vfcfg vfcfg;
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vfcfg.value = nitrox_read_csr(ndev, NPS_CORE_GBL_VFCFG);
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vfcfg.s.cfg = mode & 0x7;
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nitrox_write_csr(ndev, NPS_CORE_GBL_VFCFG, vfcfg.value);
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}
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22
drivers/crypto/cavium/nitrox/nitrox_hal.h
Normal file
22
drivers/crypto/cavium/nitrox/nitrox_hal.h
Normal file
@ -0,0 +1,22 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __NITROX_HAL_H
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#define __NITROX_HAL_H
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#include "nitrox_dev.h"
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void nitrox_config_emu_unit(struct nitrox_device *ndev);
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void nitrox_config_pkt_input_rings(struct nitrox_device *ndev);
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void nitrox_config_pkt_solicit_ports(struct nitrox_device *ndev);
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void nitrox_config_nps_unit(struct nitrox_device *ndev);
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void nitrox_config_pom_unit(struct nitrox_device *ndev);
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void nitrox_config_rand_unit(struct nitrox_device *ndev);
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void nitrox_config_efl_unit(struct nitrox_device *ndev);
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void nitrox_config_bmi_unit(struct nitrox_device *ndev);
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void nitrox_config_bmo_unit(struct nitrox_device *ndev);
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void nitrox_config_lbc_unit(struct nitrox_device *ndev);
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void invalidate_lbc(struct nitrox_device *ndev);
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void enable_pkt_input_ring(struct nitrox_device *ndev, int ring);
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void enable_pkt_solicit_port(struct nitrox_device *ndev, int port);
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void config_nps_core_vfcfg_mode(struct nitrox_device *ndev, enum vf_mode mode);
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#endif /* __NITROX_HAL_H */
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@ -6,6 +6,7 @@
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#include "nitrox_dev.h"
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#include "nitrox_csr.h"
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#include "nitrox_common.h"
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#include "nitrox_hal.h"
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#define NR_RING_VECTORS 3
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#define NPS_CORE_INT_ACTIVE_ENTRY 192
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@ -11,13 +11,14 @@
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#include "nitrox_dev.h"
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#include "nitrox_common.h"
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#include "nitrox_csr.h"
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#include "nitrox_hal.h"
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#define CNN55XX_DEV_ID 0x12
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#define MAX_PF_QUEUES 64
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#define UCODE_HLEN 48
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#define SE_GROUP 0
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#define DRIVER_VERSION "1.0"
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#define DRIVER_VERSION "1.1"
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#define FW_DIR "cavium/"
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/* SE microcode */
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#define SE_FW FW_DIR "cnn55xx_se.fw"
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@ -42,6 +43,15 @@ static unsigned int qlen = DEFAULT_CMD_QLEN;
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module_param(qlen, uint, 0644);
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MODULE_PARM_DESC(qlen, "Command queue length - default 2048");
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#ifdef CONFIG_PCI_IOV
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int nitrox_sriov_configure(struct pci_dev *pdev, int num_vfs);
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#else
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int nitrox_sriov_configure(struct pci_dev *pdev, int num_vfs)
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{
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return 0;
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}
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#endif
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/**
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* struct ucode - Firmware Header
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* @id: microcode ID
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@ -136,9 +146,6 @@ static int nitrox_load_fw(struct nitrox_device *ndev, const char *fw_name)
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write_to_ucd_unit(ndev, ucode);
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release_firmware(fw);
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set_bit(NITROX_UCODE_LOADED, &ndev->status);
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/* barrier to sync with other cpus */
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smp_mb__after_atomic();
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return 0;
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}
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@ -555,7 +562,7 @@ static int nitrox_probe(struct pci_dev *pdev,
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if (err)
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goto pf_hw_fail;
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set_bit(NITROX_READY, &ndev->status);
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atomic_set(&ndev->state, __NDEV_READY);
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/* barrier to sync with other cpus */
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smp_mb__after_atomic();
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@ -567,7 +574,7 @@ static int nitrox_probe(struct pci_dev *pdev,
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crypto_fail:
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nitrox_debugfs_exit(ndev);
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clear_bit(NITROX_READY, &ndev->status);
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atomic_set(&ndev->state, __NDEV_NOT_READY);
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/* barrier to sync with other cpus */
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smp_mb__after_atomic();
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pf_hw_fail:
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@ -602,11 +609,16 @@ static void nitrox_remove(struct pci_dev *pdev)
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dev_info(DEV(ndev), "Removing Device %x:%x\n",
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ndev->hw.vendor_id, ndev->hw.device_id);
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clear_bit(NITROX_READY, &ndev->status);
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atomic_set(&ndev->state, __NDEV_NOT_READY);
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/* barrier to sync with other cpus */
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smp_mb__after_atomic();
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nitrox_remove_from_devlist(ndev);
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#ifdef CONFIG_PCI_IOV
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/* disable SR-IOV */
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nitrox_sriov_configure(pdev, 0);
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#endif
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nitrox_crypto_unregister();
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nitrox_debugfs_exit(ndev);
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nitrox_pf_sw_cleanup(ndev);
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@ -632,6 +644,9 @@ static struct pci_driver nitrox_driver = {
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.probe = nitrox_probe,
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.remove = nitrox_remove,
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.shutdown = nitrox_shutdown,
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#ifdef CONFIG_PCI_IOV
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.sriov_configure = nitrox_sriov_configure,
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#endif
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};
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module_pci_driver(nitrox_driver);
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150
drivers/crypto/cavium/nitrox/nitrox_sriov.c
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150
drivers/crypto/cavium/nitrox/nitrox_sriov.c
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@ -0,0 +1,150 @@
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// SPDX-License-Identifier: GPL-2.0
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#include <linux/pci.h>
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#include <linux/delay.h>
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#include "nitrox_dev.h"
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#include "nitrox_hal.h"
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#include "nitrox_common.h"
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static inline bool num_vfs_valid(int num_vfs)
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{
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bool valid = false;
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switch (num_vfs) {
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case 16:
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case 32:
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case 64:
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case 128:
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valid = true;
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break;
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}
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return valid;
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}
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static inline enum vf_mode num_vfs_to_mode(int num_vfs)
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{
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enum vf_mode mode = 0;
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switch (num_vfs) {
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case 0:
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mode = __NDEV_MODE_PF;
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break;
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case 16:
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mode = __NDEV_MODE_VF16;
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break;
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case 32:
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mode = __NDEV_MODE_VF32;
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break;
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case 64:
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mode = __NDEV_MODE_VF64;
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break;
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case 128:
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mode = __NDEV_MODE_VF128;
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break;
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}
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return mode;
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}
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static void pf_sriov_cleanup(struct nitrox_device *ndev)
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{
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/* PF has no queues in SR-IOV mode */
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atomic_set(&ndev->state, __NDEV_NOT_READY);
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/* unregister crypto algorithms */
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nitrox_crypto_unregister();
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/* cleanup PF resources */
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nitrox_pf_cleanup_isr(ndev);
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nitrox_common_sw_cleanup(ndev);
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}
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static int pf_sriov_init(struct nitrox_device *ndev)
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{
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int err;
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/* allocate resources for PF */
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err = nitrox_common_sw_init(ndev);
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if (err)
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return err;
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err = nitrox_pf_init_isr(ndev);
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if (err) {
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nitrox_common_sw_cleanup(ndev);
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return err;
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}
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/* configure the packet queues */
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nitrox_config_pkt_input_rings(ndev);
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nitrox_config_pkt_solicit_ports(ndev);
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/* set device to ready state */
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atomic_set(&ndev->state, __NDEV_READY);
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/* register crypto algorithms */
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return nitrox_crypto_register();
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}
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static int nitrox_sriov_enable(struct pci_dev *pdev, int num_vfs)
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{
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struct nitrox_device *ndev = pci_get_drvdata(pdev);
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int err;
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if (!num_vfs_valid(num_vfs)) {
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dev_err(DEV(ndev), "Invalid num_vfs %d\n", num_vfs);
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return -EINVAL;
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}
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if (pci_num_vf(pdev) == num_vfs)
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return num_vfs;
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err = pci_enable_sriov(pdev, num_vfs);
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if (err) {
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dev_err(DEV(ndev), "failed to enable PCI sriov %d\n", err);
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return err;
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}
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dev_info(DEV(ndev), "Enabled VF(s) %d\n", num_vfs);
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ndev->num_vfs = num_vfs;
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ndev->mode = num_vfs_to_mode(num_vfs);
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/* set bit in flags */
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set_bit(__NDEV_SRIOV_BIT, &ndev->flags);
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/* cleanup PF resources */
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pf_sriov_cleanup(ndev);
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config_nps_core_vfcfg_mode(ndev, ndev->mode);
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return num_vfs;
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}
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static int nitrox_sriov_disable(struct pci_dev *pdev)
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{
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struct nitrox_device *ndev = pci_get_drvdata(pdev);
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if (!test_bit(__NDEV_SRIOV_BIT, &ndev->flags))
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return 0;
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if (pci_vfs_assigned(pdev)) {
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dev_warn(DEV(ndev), "VFs are attached to VM. Can't disable SR-IOV\n");
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return -EPERM;
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}
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pci_disable_sriov(pdev);
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/* clear bit in flags */
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clear_bit(__NDEV_SRIOV_BIT, &ndev->flags);
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ndev->num_vfs = 0;
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ndev->mode = __NDEV_MODE_PF;
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config_nps_core_vfcfg_mode(ndev, ndev->mode);
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return pf_sriov_init(ndev);
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}
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int nitrox_sriov_configure(struct pci_dev *pdev, int num_vfs)
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{
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if (!num_vfs)
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return nitrox_sriov_disable(pdev);
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return nitrox_sriov_enable(pdev, num_vfs);
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}
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