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rtw88: add BT co-existence support
Both RTL8822BE/RTL8822CE are WiFi + BT combo chips. Since WiFi and BT use 2.4GHz to transmit, it is important to make sure they run concurrently without interfering each other. To achieve this, WiFi driver requires a mechanism to collaborate with BT, whether they share the antenna(s) or not. The final decision made by the co-existence mechanism is to choose a proper strategy, or called "tdma/table", and inform either firmware or hardware of the strategy. To choose a strategy, co-existence mechanism needs to have enough information from WiFi and BT. BT information is provided through firmware C2H. The contents describe the current status of BT, such as if BT is connected or is idle, or the profile that is being used. WiFi information can be provided by WiFi itself. The WiFi driver will call various of "notify" functions each time the state of WiFi changed, such as WiFi is going to switch channel or is connected. Also WiFi driver can know if it shares antenna with BT by reading efuse content. Antenna configuration of the module will finally get a different strategy. Upon receiving any information from WiFi or BT, the WiFi driver will run the co-existence mechanism immediately. It will set the RF antenna configuration according to the strategy through the TDMA H2C to firmware and a hardware table. Based on the tdma/table, WiFi + BT should work with each other, and having a better user experience. Signed-off-by: Yan-Hsuan Chuang <yhchuang@realtek.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
This commit is contained in:
Yan-Hsuan Chuang
Kalle Valo
parent
713a30de45
commit
4136214f7c
@ -9,6 +9,7 @@ rtw88-y += main.o \
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rx.o \
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mac.o \
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phy.o \
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coex.o \
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efuse.o \
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fw.o \
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ps.o \
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2507
drivers/net/wireless/realtek/rtw88/coex.c
Normal file
2507
drivers/net/wireless/realtek/rtw88/coex.c
Normal file
File diff suppressed because it is too large
Load Diff
369
drivers/net/wireless/realtek/rtw88/coex.h
Normal file
369
drivers/net/wireless/realtek/rtw88/coex.h
Normal file
@ -0,0 +1,369 @@
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/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
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/* Copyright(c) 2018-2019 Realtek Corporation
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*/
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#ifndef __RTW_COEX_H__
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#define __RTW_COEX_H__
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/* BT profile map bit definition */
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#define BPM_HFP BIT(0)
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#define BPM_HID BIT(1)
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#define BPM_A2DP BIT(2)
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#define BPM_PAN BIT(3)
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#define COEX_RESP_ACK_BY_WL_FW 0x1
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#define COEX_REQUEST_TIMEOUT msecs_to_jiffies(10)
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#define COEX_MIN_DELAY 10 /* delay unit in ms */
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#define COEX_RFK_TIMEOUT 600 /* RFK timeout in ms */
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#define COEX_RF_OFF 0x0
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#define COEX_RF_ON 0x1
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#define COEX_H2C69_WL_LEAKAP 0xc
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#define PARA1_H2C69_DIS_5MS 0x1
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#define PARA1_H2C69_EN_5MS 0x0
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#define COEX_H2C69_TDMA_SLOT 0xb
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#define PARA1_H2C69_TDMA_4SLOT 0xc1
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#define PARA1_H2C69_TDMA_2SLOT 0x1
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#define TDMA_4SLOT BIT(8)
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#define COEX_RSSI_STEP 4
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#define COEX_RSSI_HIGH(rssi) \
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({ typeof(rssi) __rssi__ = rssi; \
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(__rssi__ == COEX_RSSI_STATE_HIGH || \
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__rssi__ == COEX_RSSI_STATE_STAY_HIGH ? true : false); })
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#define COEX_RSSI_MEDIUM(rssi) \
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({ typeof(rssi) __rssi__ = rssi; \
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(__rssi__ == COEX_RSSI_STATE_MEDIUM || \
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__rssi__ == COEX_RSSI_STATE_STAY_MEDIUM ? true : false); })
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#define COEX_RSSI_LOW(rssi) \
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({ typeof(rssi) __rssi__ = rssi; \
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(__rssi__ == COEX_RSSI_STATE_LOW || \
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__rssi__ == COEX_RSSI_STATE_STAY_LOW ? true : false); })
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#define GET_COEX_RESP_BT_SCAN_TYPE(payload) \
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le64_get_bits(*((__le64 *)(payload)), GENMASK(31, 24))
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enum coex_mp_info_op {
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BT_MP_INFO_OP_PATCH_VER = 0x00,
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BT_MP_INFO_OP_READ_REG = 0x11,
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BT_MP_INFO_OP_SUPP_FEAT = 0x2a,
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BT_MP_INFO_OP_SUPP_VER = 0x2b,
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BT_MP_INFO_OP_SCAN_TYPE = 0x2d,
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BT_MP_INFO_OP_LNA_CONSTRAINT = 0x32,
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};
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enum coex_set_ant_phase {
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COEX_SET_ANT_INIT,
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COEX_SET_ANT_WONLY,
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COEX_SET_ANT_WOFF,
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COEX_SET_ANT_2G,
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COEX_SET_ANT_5G,
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COEX_SET_ANT_POWERON,
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COEX_SET_ANT_2G_WLBT,
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COEX_SET_ANT_2G_FREERUN,
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COEX_SET_ANT_MAX
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};
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enum coex_runreason {
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COEX_RSN_2GSCANSTART = 0,
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COEX_RSN_5GSCANSTART = 1,
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COEX_RSN_SCANFINISH = 2,
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COEX_RSN_2GSWITCHBAND = 3,
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COEX_RSN_5GSWITCHBAND = 4,
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COEX_RSN_2GCONSTART = 5,
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COEX_RSN_5GCONSTART = 6,
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COEX_RSN_2GCONFINISH = 7,
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COEX_RSN_5GCONFINISH = 8,
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COEX_RSN_2GMEDIA = 9,
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COEX_RSN_5GMEDIA = 10,
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COEX_RSN_MEDIADISCON = 11,
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COEX_RSN_BTINFO = 12,
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COEX_RSN_LPS = 13,
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COEX_RSN_WLSTATUS = 14,
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COEX_RSN_MAX
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};
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enum coex_lte_coex_table_type {
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COEX_CTT_WL_VS_LTE,
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COEX_CTT_BT_VS_LTE,
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};
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enum coex_gnt_setup_state {
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COEX_GNT_SET_HW_PTA = 0x0,
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COEX_GNT_SET_SW_LOW = 0x1,
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COEX_GNT_SET_SW_HIGH = 0x3,
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};
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enum coex_ext_ant_switch_pos_type {
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COEX_SWITCH_TO_BT,
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COEX_SWITCH_TO_WLG,
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COEX_SWITCH_TO_WLA,
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COEX_SWITCH_TO_NOCARE,
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COEX_SWITCH_TO_WLG_BT,
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COEX_SWITCH_TO_MAX
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};
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enum coex_ext_ant_switch_ctrl_type {
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COEX_SWITCH_CTRL_BY_BBSW,
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COEX_SWITCH_CTRL_BY_PTA,
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COEX_SWITCH_CTRL_BY_ANTDIV,
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COEX_SWITCH_CTRL_BY_MAC,
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COEX_SWITCH_CTRL_BY_BT,
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COEX_SWITCH_CTRL_BY_FW,
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COEX_SWITCH_CTRL_MAX
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};
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enum coex_algorithm {
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COEX_ALGO_NOPROFILE = 0,
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COEX_ALGO_HFP = 1,
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COEX_ALGO_HID = 2,
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COEX_ALGO_A2DP = 3,
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COEX_ALGO_PAN = 4,
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COEX_ALGO_A2DP_HID = 5,
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COEX_ALGO_A2DP_PAN = 6,
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COEX_ALGO_PAN_HID = 7,
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COEX_ALGO_A2DP_PAN_HID = 8,
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COEX_ALGO_MAX
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};
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enum coex_wl_link_mode {
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COEX_WLINK_2G1PORT = 0x0,
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COEX_WLINK_5G = 0x3,
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COEX_WLINK_MAX
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};
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enum coex_wl2bt_scoreboard {
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COEX_SCBD_ACTIVE = BIT(0),
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COEX_SCBD_ONOFF = BIT(1),
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COEX_SCBD_SCAN = BIT(2),
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COEX_SCBD_UNDERTEST = BIT(3),
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COEX_SCBD_RXGAIN = BIT(4),
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COEX_SCBD_BT_RFK = BIT(5),
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COEX_SCBD_WLBUSY = BIT(6),
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COEX_SCBD_EXTFEM = BIT(8),
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COEX_SCBD_TDMA = BIT(9),
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COEX_SCBD_FIX2M = BIT(10),
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COEX_SCBD_ALL = GENMASK(15, 0),
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};
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enum coex_power_save_type {
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COEX_PS_WIFI_NATIVE = 0,
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COEX_PS_LPS_ON = 1,
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COEX_PS_LPS_OFF = 2,
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};
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enum coex_rssi_state {
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COEX_RSSI_STATE_HIGH,
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COEX_RSSI_STATE_MEDIUM,
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COEX_RSSI_STATE_LOW,
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COEX_RSSI_STATE_STAY_HIGH,
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COEX_RSSI_STATE_STAY_MEDIUM,
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COEX_RSSI_STATE_STAY_LOW,
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};
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enum coex_notify_type_ips {
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COEX_IPS_LEAVE = 0x0,
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COEX_IPS_ENTER = 0x1,
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};
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enum coex_notify_type_lps {
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COEX_LPS_DISABLE = 0x0,
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COEX_LPS_ENABLE = 0x1,
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};
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enum coex_notify_type_scan {
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COEX_SCAN_FINISH,
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COEX_SCAN_START,
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COEX_SCAN_START_2G,
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COEX_SCAN_START_5G,
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};
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enum coex_notify_type_switchband {
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COEX_NOT_SWITCH,
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COEX_SWITCH_TO_24G,
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COEX_SWITCH_TO_5G,
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COEX_SWITCH_TO_24G_NOFORSCAN,
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};
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enum coex_notify_type_associate {
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COEX_ASSOCIATE_FINISH,
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COEX_ASSOCIATE_START,
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COEX_ASSOCIATE_5G_FINISH,
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COEX_ASSOCIATE_5G_START,
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};
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enum coex_notify_type_media_status {
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COEX_MEDIA_DISCONNECT,
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COEX_MEDIA_CONNECT,
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COEX_MEDIA_CONNECT_5G,
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};
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enum coex_bt_status {
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COEX_BTSTATUS_NCON_IDLE = 0,
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COEX_BTSTATUS_CON_IDLE = 1,
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COEX_BTSTATUS_INQ_PAGE = 2,
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COEX_BTSTATUS_ACL_BUSY = 3,
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COEX_BTSTATUS_SCO_BUSY = 4,
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COEX_BTSTATUS_ACL_SCO_BUSY = 5,
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COEX_BTSTATUS_MAX
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};
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enum coex_wl_tput_dir {
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COEX_WL_TPUT_TX = 0x0,
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COEX_WL_TPUT_RX = 0x1,
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COEX_WL_TPUT_MAX
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};
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enum coex_wl_priority_mask {
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COEX_WLPRI_RX_RSP = 2,
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COEX_WLPRI_TX_RSP = 3,
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COEX_WLPRI_TX_BEACON = 4,
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COEX_WLPRI_TX_OFDM = 11,
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COEX_WLPRI_TX_CCK = 12,
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COEX_WLPRI_TX_BEACONQ = 27,
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COEX_WLPRI_RX_CCK = 28,
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COEX_WLPRI_RX_OFDM = 29,
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COEX_WLPRI_MAX
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};
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enum coex_commom_chip_setup {
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COEX_CSETUP_INIT_HW = 0x0,
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COEX_CSETUP_ANT_SWITCH = 0x1,
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COEX_CSETUP_GNT_FIX = 0x2,
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COEX_CSETUP_GNT_DEBUG = 0x3,
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COEX_CSETUP_RFE_TYPE = 0x4,
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COEX_CSETUP_COEXINFO_HW = 0x5,
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COEX_CSETUP_WL_TX_POWER = 0x6,
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COEX_CSETUP_WL_RX_GAIN = 0x7,
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COEX_CSETUP_WLAN_ACT_IPS = 0x8,
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COEX_CSETUP_MAX
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};
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enum coex_indirect_reg_type {
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COEX_INDIRECT_1700 = 0x0,
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COEX_INDIRECT_7C0 = 0x1,
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COEX_INDIRECT_MAX
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};
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enum coex_pstdma_type {
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COEX_PSTDMA_FORCE_LPSOFF = 0x0,
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COEX_PSTDMA_FORCE_LPSON = 0x1,
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COEX_PSTDMA_MAX
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};
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enum coex_btrssi_type {
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COEX_BTRSSI_RATIO = 0x0,
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COEX_BTRSSI_DBM = 0x1,
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COEX_BTRSSI_MAX
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};
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struct coex_table_para {
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u32 bt;
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u32 wl;
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};
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struct coex_tdma_para {
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u8 para[5];
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};
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struct coex_5g_afh_map {
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u32 wl_5g_ch;
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u8 bt_skip_ch;
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u8 bt_skip_span;
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};
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struct coex_rf_para {
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u8 wl_pwr_dec_lvl;
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u8 bt_pwr_dec_lvl;
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bool wl_low_gain_en;
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u8 bt_lna_lvl;
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};
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static inline void rtw_coex_set_init(struct rtw_dev *rtwdev)
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{
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struct rtw_chip_info *chip = rtwdev->chip;
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chip->ops->coex_set_init(rtwdev);
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}
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static inline
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void rtw_coex_set_ant_switch(struct rtw_dev *rtwdev, u8 ctrl_type, u8 pos_type)
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{
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struct rtw_chip_info *chip = rtwdev->chip;
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if (!chip->ops->coex_set_ant_switch)
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return;
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chip->ops->coex_set_ant_switch(rtwdev, ctrl_type, pos_type);
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}
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static inline void rtw_coex_set_gnt_fix(struct rtw_dev *rtwdev)
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{
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struct rtw_chip_info *chip = rtwdev->chip;
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chip->ops->coex_set_gnt_fix(rtwdev);
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}
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static inline void rtw_coex_set_gnt_debug(struct rtw_dev *rtwdev)
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{
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struct rtw_chip_info *chip = rtwdev->chip;
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chip->ops->coex_set_gnt_debug(rtwdev);
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}
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static inline void rtw_coex_set_rfe_type(struct rtw_dev *rtwdev)
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{
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struct rtw_chip_info *chip = rtwdev->chip;
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chip->ops->coex_set_rfe_type(rtwdev);
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}
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static inline void rtw_coex_set_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr)
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{
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struct rtw_chip_info *chip = rtwdev->chip;
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chip->ops->coex_set_wl_tx_power(rtwdev, wl_pwr);
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}
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static inline
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void rtw_coex_set_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain)
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{
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struct rtw_chip_info *chip = rtwdev->chip;
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chip->ops->coex_set_wl_rx_gain(rtwdev, low_gain);
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}
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void rtw_coex_info_response(struct rtw_dev *rtwdev, struct sk_buff *skb);
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void rtw_coex_write_indirect_reg(struct rtw_dev *rtwdev, u16 addr,
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u32 mask, u32 val);
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void rtw_coex_write_scbd(struct rtw_dev *rtwdev, u16 bitpos, bool set);
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void rtw_coex_bt_relink_work(struct work_struct *work);
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void rtw_coex_bt_reenable_work(struct work_struct *work);
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void rtw_coex_defreeze_work(struct work_struct *work);
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void rtw_coex_power_on_setting(struct rtw_dev *rtwdev);
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void rtw_coex_init_hw_config(struct rtw_dev *rtwdev, bool wifi_only);
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void rtw_coex_ips_notify(struct rtw_dev *rtwdev, u8 type);
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void rtw_coex_lps_notify(struct rtw_dev *rtwdev, u8 type);
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void rtw_coex_scan_notify(struct rtw_dev *rtwdev, u8 type);
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void rtw_coex_connect_notify(struct rtw_dev *rtwdev, u8 action);
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void rtw_coex_media_status_notify(struct rtw_dev *rtwdev, u8 status);
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void rtw_coex_bt_info_notify(struct rtw_dev *rtwdev, u8 *buf, u8 len);
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void rtw_coex_wl_fwdbginfo_notify(struct rtw_dev *rtwdev, u8 *buf, u8 length);
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void rtw_coex_switchband_notify(struct rtw_dev *rtwdev, u8 type);
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void rtw_coex_wl_status_change_notify(struct rtw_dev *rtwdev);
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#endif
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@ -3,6 +3,7 @@
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*/
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#include "main.h"
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#include "coex.h"
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#include "fw.h"
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#include "tx.h"
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#include "reg.h"
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@ -39,6 +40,12 @@ void rtw_fw_c2h_cmd_handle(struct rtw_dev *rtwdev, struct sk_buff *skb)
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mutex_lock(&rtwdev->mutex);
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switch (c2h->id) {
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case C2H_BT_INFO:
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rtw_coex_bt_info_notify(rtwdev, c2h->payload, len);
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break;
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case C2H_WLAN_INFO:
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rtw_coex_wl_fwdbginfo_notify(rtwdev, c2h->payload, len);
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break;
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case C2H_HALMAC:
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rtw_fw_c2h_cmd_handle_ext(rtwdev, skb);
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break;
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@ -63,6 +70,9 @@ void rtw_fw_c2h_cmd_rx_irqsafe(struct rtw_dev *rtwdev, u32 pkt_offset,
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c2h->id, c2h->seq, len);
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switch (c2h->id) {
|
||||
case C2H_BT_MP_INFO:
|
||||
rtw_coex_info_response(rtwdev, skb);
|
||||
break;
|
||||
default:
|
||||
/* pass offset for further operation */
|
||||
*((u32 *)skb->cb) = pkt_offset;
|
||||
@ -206,6 +216,102 @@ void rtw_fw_do_iqk(struct rtw_dev *rtwdev, struct rtw_iqk_para *para)
|
||||
rtw_fw_send_h2c_packet(rtwdev, h2c_pkt);
|
||||
}
|
||||
|
||||
void rtw_fw_query_bt_info(struct rtw_dev *rtwdev)
|
||||
{
|
||||
u8 h2c_pkt[H2C_PKT_SIZE] = {0};
|
||||
|
||||
SET_H2C_CMD_ID_CLASS(h2c_pkt, H2C_CMD_QUERY_BT_INFO);
|
||||
|
||||
SET_QUERY_BT_INFO(h2c_pkt, true);
|
||||
|
||||
rtw_fw_send_h2c_command(rtwdev, h2c_pkt);
|
||||
}
|
||||
|
||||
void rtw_fw_wl_ch_info(struct rtw_dev *rtwdev, u8 link, u8 ch, u8 bw)
|
||||
{
|
||||
u8 h2c_pkt[H2C_PKT_SIZE] = {0};
|
||||
|
||||
SET_H2C_CMD_ID_CLASS(h2c_pkt, H2C_CMD_WL_CH_INFO);
|
||||
|
||||
SET_WL_CH_INFO_LINK(h2c_pkt, link);
|
||||
SET_WL_CH_INFO_CHNL(h2c_pkt, ch);
|
||||
SET_WL_CH_INFO_BW(h2c_pkt, bw);
|
||||
|
||||
rtw_fw_send_h2c_command(rtwdev, h2c_pkt);
|
||||
}
|
||||
|
||||
void rtw_fw_query_bt_mp_info(struct rtw_dev *rtwdev,
|
||||
struct rtw_coex_info_req *req)
|
||||
{
|
||||
u8 h2c_pkt[H2C_PKT_SIZE] = {0};
|
||||
|
||||
SET_H2C_CMD_ID_CLASS(h2c_pkt, H2C_CMD_QUERY_BT_MP_INFO);
|
||||
|
||||
SET_BT_MP_INFO_SEQ(h2c_pkt, req->seq);
|
||||
SET_BT_MP_INFO_OP_CODE(h2c_pkt, req->op_code);
|
||||
SET_BT_MP_INFO_PARA1(h2c_pkt, req->para1);
|
||||
SET_BT_MP_INFO_PARA2(h2c_pkt, req->para2);
|
||||
SET_BT_MP_INFO_PARA3(h2c_pkt, req->para3);
|
||||
|
||||
rtw_fw_send_h2c_command(rtwdev, h2c_pkt);
|
||||
}
|
||||
|
||||
void rtw_fw_force_bt_tx_power(struct rtw_dev *rtwdev, u8 bt_pwr_dec_lvl)
|
||||
{
|
||||
u8 h2c_pkt[H2C_PKT_SIZE] = {0};
|
||||
u8 index = 0 - bt_pwr_dec_lvl;
|
||||
|
||||
SET_H2C_CMD_ID_CLASS(h2c_pkt, H2C_CMD_FORCE_BT_TX_POWER);
|
||||
|
||||
SET_BT_TX_POWER_INDEX(h2c_pkt, index);
|
||||
|
||||
rtw_fw_send_h2c_command(rtwdev, h2c_pkt);
|
||||
}
|
||||
|
||||
void rtw_fw_bt_ignore_wlan_action(struct rtw_dev *rtwdev, bool enable)
|
||||
{
|
||||
u8 h2c_pkt[H2C_PKT_SIZE] = {0};
|
||||
|
||||
SET_H2C_CMD_ID_CLASS(h2c_pkt, H2C_CMD_IGNORE_WLAN_ACTION);
|
||||
|
||||
SET_IGNORE_WLAN_ACTION_EN(h2c_pkt, enable);
|
||||
|
||||
rtw_fw_send_h2c_command(rtwdev, h2c_pkt);
|
||||
}
|
||||
|
||||
void rtw_fw_coex_tdma_type(struct rtw_dev *rtwdev,
|
||||
u8 para1, u8 para2, u8 para3, u8 para4, u8 para5)
|
||||
{
|
||||
u8 h2c_pkt[H2C_PKT_SIZE] = {0};
|
||||
|
||||
SET_H2C_CMD_ID_CLASS(h2c_pkt, H2C_CMD_COEX_TDMA_TYPE);
|
||||
|
||||
SET_COEX_TDMA_TYPE_PARA1(h2c_pkt, para1);
|
||||
SET_COEX_TDMA_TYPE_PARA2(h2c_pkt, para2);
|
||||
SET_COEX_TDMA_TYPE_PARA3(h2c_pkt, para3);
|
||||
SET_COEX_TDMA_TYPE_PARA4(h2c_pkt, para4);
|
||||
SET_COEX_TDMA_TYPE_PARA5(h2c_pkt, para5);
|
||||
|
||||
rtw_fw_send_h2c_command(rtwdev, h2c_pkt);
|
||||
}
|
||||
|
||||
void rtw_fw_bt_wifi_control(struct rtw_dev *rtwdev, u8 op_code, u8 *data)
|
||||
{
|
||||
u8 h2c_pkt[H2C_PKT_SIZE] = {0};
|
||||
|
||||
SET_H2C_CMD_ID_CLASS(h2c_pkt, H2C_CMD_BT_WIFI_CONTROL);
|
||||
|
||||
SET_BT_WIFI_CONTROL_OP_CODE(h2c_pkt, op_code);
|
||||
|
||||
SET_BT_WIFI_CONTROL_DATA1(h2c_pkt, *data);
|
||||
SET_BT_WIFI_CONTROL_DATA2(h2c_pkt, *(data + 1));
|
||||
SET_BT_WIFI_CONTROL_DATA3(h2c_pkt, *(data + 2));
|
||||
SET_BT_WIFI_CONTROL_DATA4(h2c_pkt, *(data + 3));
|
||||
SET_BT_WIFI_CONTROL_DATA5(h2c_pkt, *(data + 4));
|
||||
|
||||
rtw_fw_send_h2c_command(rtwdev, h2c_pkt);
|
||||
}
|
||||
|
||||
void rtw_fw_send_rssi_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si)
|
||||
{
|
||||
u8 h2c_pkt[H2C_PKT_SIZE] = {0};
|
||||
|
||||
@ -35,7 +35,9 @@
|
||||
|
||||
enum rtw_c2h_cmd_id {
|
||||
C2H_BT_INFO = 0x09,
|
||||
C2H_BT_MP_INFO = 0x0b,
|
||||
C2H_HW_FEATURE_REPORT = 0x19,
|
||||
C2H_WLAN_INFO = 0x27,
|
||||
C2H_HW_FEATURE_DUMP = 0xfd,
|
||||
C2H_HALMAC = 0xff,
|
||||
};
|
||||
@ -71,6 +73,14 @@ enum rtw_fw_rf_type {
|
||||
FW_RF_MAX_TYPE = 0xF,
|
||||
};
|
||||
|
||||
struct rtw_coex_info_req {
|
||||
u8 seq;
|
||||
u8 op_code;
|
||||
u8 para1;
|
||||
u8 para2;
|
||||
u8 para3;
|
||||
};
|
||||
|
||||
struct rtw_iqk_para {
|
||||
u8 clear;
|
||||
u8 segment_iqk;
|
||||
@ -139,6 +149,14 @@ static inline void rtw_h2c_pkt_set_header(u8 *h2c_pkt, u8 sub_id)
|
||||
#define H2C_CMD_RA_INFO 0x40
|
||||
#define H2C_CMD_RSSI_MONITOR 0x42
|
||||
|
||||
#define H2C_CMD_COEX_TDMA_TYPE 0x60
|
||||
#define H2C_CMD_QUERY_BT_INFO 0x61
|
||||
#define H2C_CMD_FORCE_BT_TX_POWER 0x62
|
||||
#define H2C_CMD_IGNORE_WLAN_ACTION 0x63
|
||||
#define H2C_CMD_WL_CH_INFO 0x66
|
||||
#define H2C_CMD_QUERY_BT_MP_INFO 0x67
|
||||
#define H2C_CMD_BT_WIFI_CONTROL 0x69
|
||||
|
||||
#define SET_H2C_CMD_ID_CLASS(h2c_pkt, value) \
|
||||
le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(7, 0))
|
||||
|
||||
@ -191,6 +209,50 @@ static inline void rtw_h2c_pkt_set_header(u8 *h2c_pkt, u8 sub_id)
|
||||
le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(23, 16))
|
||||
#define SET_RA_INFO_RA_MASK3(h2c_pkt, value) \
|
||||
le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(31, 24))
|
||||
#define SET_QUERY_BT_INFO(h2c_pkt, value) \
|
||||
le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
|
||||
#define SET_WL_CH_INFO_LINK(h2c_pkt, value) \
|
||||
le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
|
||||
#define SET_WL_CH_INFO_CHNL(h2c_pkt, value) \
|
||||
le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
|
||||
#define SET_WL_CH_INFO_BW(h2c_pkt, value) \
|
||||
le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
|
||||
#define SET_BT_MP_INFO_SEQ(h2c_pkt, value) \
|
||||
le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 12))
|
||||
#define SET_BT_MP_INFO_OP_CODE(h2c_pkt, value) \
|
||||
le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
|
||||
#define SET_BT_MP_INFO_PARA1(h2c_pkt, value) \
|
||||
le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
|
||||
#define SET_BT_MP_INFO_PARA2(h2c_pkt, value) \
|
||||
le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0))
|
||||
#define SET_BT_MP_INFO_PARA3(h2c_pkt, value) \
|
||||
le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8))
|
||||
#define SET_BT_TX_POWER_INDEX(h2c_pkt, value) \
|
||||
le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
|
||||
#define SET_IGNORE_WLAN_ACTION_EN(h2c_pkt, value) \
|
||||
le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
|
||||
#define SET_COEX_TDMA_TYPE_PARA1(h2c_pkt, value) \
|
||||
le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
|
||||
#define SET_COEX_TDMA_TYPE_PARA2(h2c_pkt, value) \
|
||||
le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
|
||||
#define SET_COEX_TDMA_TYPE_PARA3(h2c_pkt, value) \
|
||||
le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
|
||||
#define SET_COEX_TDMA_TYPE_PARA4(h2c_pkt, value) \
|
||||
le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0))
|
||||
#define SET_COEX_TDMA_TYPE_PARA5(h2c_pkt, value) \
|
||||
le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8))
|
||||
#define SET_BT_WIFI_CONTROL_OP_CODE(h2c_pkt, value) \
|
||||
le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
|
||||
#define SET_BT_WIFI_CONTROL_DATA1(h2c_pkt, value) \
|
||||
le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
|
||||
#define SET_BT_WIFI_CONTROL_DATA2(h2c_pkt, value) \
|
||||
le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
|
||||
#define SET_BT_WIFI_CONTROL_DATA3(h2c_pkt, value) \
|
||||
le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0))
|
||||
#define SET_BT_WIFI_CONTROL_DATA4(h2c_pkt, value) \
|
||||
le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8))
|
||||
#define SET_BT_WIFI_CONTROL_DATA5(h2c_pkt, value) \
|
||||
le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(23, 16))
|
||||
|
||||
static inline struct rtw_c2h_cmd *get_c2h_from_skb(struct sk_buff *skb)
|
||||
{
|
||||
@ -208,6 +270,15 @@ void rtw_fw_send_phydm_info(struct rtw_dev *rtwdev);
|
||||
|
||||
void rtw_fw_do_iqk(struct rtw_dev *rtwdev, struct rtw_iqk_para *para);
|
||||
void rtw_fw_set_pwr_mode(struct rtw_dev *rtwdev);
|
||||
void rtw_fw_query_bt_info(struct rtw_dev *rtwdev);
|
||||
void rtw_fw_wl_ch_info(struct rtw_dev *rtwdev, u8 link, u8 ch, u8 bw);
|
||||
void rtw_fw_query_bt_mp_info(struct rtw_dev *rtwdev,
|
||||
struct rtw_coex_info_req *req);
|
||||
void rtw_fw_force_bt_tx_power(struct rtw_dev *rtwdev, u8 bt_pwr_dec_lvl);
|
||||
void rtw_fw_bt_ignore_wlan_action(struct rtw_dev *rtwdev, bool enable);
|
||||
void rtw_fw_coex_tdma_type(struct rtw_dev *rtwdev,
|
||||
u8 para1, u8 para2, u8 para3, u8 para4, u8 para5);
|
||||
void rtw_fw_bt_wifi_control(struct rtw_dev *rtwdev, u8 op_code, u8 *data);
|
||||
void rtw_fw_send_rssi_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si);
|
||||
void rtw_fw_send_ra_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si);
|
||||
void rtw_fw_media_status_report(struct rtw_dev *rtwdev, u8 mac_id, bool conn);
|
||||
|
||||
@ -7,6 +7,7 @@
|
||||
#include "tx.h"
|
||||
#include "fw.h"
|
||||
#include "mac.h"
|
||||
#include "coex.h"
|
||||
#include "ps.h"
|
||||
#include "reg.h"
|
||||
#include "debug.h"
|
||||
@ -253,6 +254,7 @@ static void rtw_ops_bss_info_changed(struct ieee80211_hw *hw,
|
||||
enum rtw_net_type net_type;
|
||||
|
||||
if (conf->assoc) {
|
||||
rtw_coex_connect_notify(rtwdev, COEX_ASSOCIATE_FINISH);
|
||||
net_type = RTW_NET_MGD_LINKED;
|
||||
chip->ops->do_iqk(rtwdev);
|
||||
|
||||
@ -262,6 +264,7 @@ static void rtw_ops_bss_info_changed(struct ieee80211_hw *hw,
|
||||
rtw_add_rsvd_page(rtwdev, RSVD_NULL, true);
|
||||
rtw_fw_download_rsvd_page(rtwdev, vif);
|
||||
rtw_send_rsvd_page_h2c(rtwdev);
|
||||
rtw_coex_media_status_notify(rtwdev, conf->assoc);
|
||||
} else {
|
||||
net_type = RTW_NET_NO_LINK;
|
||||
rtwvif->aid = 0;
|
||||
@ -469,6 +472,8 @@ static void rtw_ops_sw_scan_start(struct ieee80211_hw *hw,
|
||||
config |= PORT_SET_MAC_ADDR;
|
||||
rtw_vif_port_config(rtwdev, rtwvif, config);
|
||||
|
||||
rtw_coex_scan_notify(rtwdev, COEX_SCAN_START);
|
||||
|
||||
rtw_flag_set(rtwdev, RTW_FLAG_DIG_DISABLE);
|
||||
rtw_flag_set(rtwdev, RTW_FLAG_SCANNING);
|
||||
|
||||
@ -491,6 +496,19 @@ static void rtw_ops_sw_scan_complete(struct ieee80211_hw *hw,
|
||||
config |= PORT_SET_MAC_ADDR;
|
||||
rtw_vif_port_config(rtwdev, rtwvif, config);
|
||||
|
||||
rtw_coex_scan_notify(rtwdev, COEX_SCAN_FINISH);
|
||||
|
||||
mutex_unlock(&rtwdev->mutex);
|
||||
}
|
||||
|
||||
static void rtw_ops_mgd_prepare_tx(struct ieee80211_hw *hw,
|
||||
struct ieee80211_vif *vif,
|
||||
u16 duration)
|
||||
{
|
||||
struct rtw_dev *rtwdev = hw->priv;
|
||||
|
||||
mutex_lock(&rtwdev->mutex);
|
||||
rtw_coex_connect_notify(rtwdev, COEX_ASSOCIATE_START);
|
||||
mutex_unlock(&rtwdev->mutex);
|
||||
}
|
||||
|
||||
@ -509,5 +527,6 @@ const struct ieee80211_ops rtw_ops = {
|
||||
.ampdu_action = rtw_ops_ampdu_action,
|
||||
.sw_scan_start = rtw_ops_sw_scan_start,
|
||||
.sw_scan_complete = rtw_ops_sw_scan_complete,
|
||||
.mgd_prepare_tx = rtw_ops_mgd_prepare_tx,
|
||||
};
|
||||
EXPORT_SYMBOL(rtw_ops);
|
||||
|
||||
@ -8,6 +8,7 @@
|
||||
#include "ps.h"
|
||||
#include "sec.h"
|
||||
#include "mac.h"
|
||||
#include "coex.h"
|
||||
#include "phy.h"
|
||||
#include "reg.h"
|
||||
#include "efuse.h"
|
||||
@ -149,6 +150,7 @@ static void rtw_watch_dog_work(struct work_struct *work)
|
||||
struct rtw_dev *rtwdev = container_of(work, struct rtw_dev,
|
||||
watch_dog_work.work);
|
||||
struct rtw_watch_dog_iter_data data = {};
|
||||
bool busy_traffic = rtw_flag_check(rtwdev, RTW_FLAG_BUSY_TRAFFIC);
|
||||
|
||||
if (!rtw_flag_check(rtwdev, RTW_FLAG_RUNNING))
|
||||
return;
|
||||
@ -156,6 +158,14 @@ static void rtw_watch_dog_work(struct work_struct *work)
|
||||
ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->watch_dog_work,
|
||||
RTW_WATCH_DOG_DELAY_TIME);
|
||||
|
||||
if (rtwdev->stats.tx_cnt > 100 || rtwdev->stats.rx_cnt > 100)
|
||||
rtw_flag_set(rtwdev, RTW_FLAG_BUSY_TRAFFIC);
|
||||
else
|
||||
rtw_flag_clear(rtwdev, RTW_FLAG_BUSY_TRAFFIC);
|
||||
|
||||
if (busy_traffic != rtw_flag_check(rtwdev, RTW_FLAG_BUSY_TRAFFIC))
|
||||
rtw_coex_wl_status_change_notify(rtwdev);
|
||||
|
||||
/* reset tx/rx statictics */
|
||||
rtwdev->stats.tx_unicast = 0;
|
||||
rtwdev->stats.rx_unicast = 0;
|
||||
@ -298,6 +308,15 @@ void rtw_set_channel(struct rtw_dev *rtwdev)
|
||||
|
||||
chip->ops->set_channel(rtwdev, center_chan, bandwidth, primary_chan_idx);
|
||||
|
||||
if (hal->current_band_type == RTW_BAND_5G) {
|
||||
rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_5G);
|
||||
} else {
|
||||
if (rtw_flag_check(rtwdev, RTW_FLAG_SCANNING))
|
||||
rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_24G);
|
||||
else
|
||||
rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_24G_NOFORSCAN);
|
||||
}
|
||||
|
||||
rtw_phy_set_tx_power_level(rtwdev, center_chan);
|
||||
}
|
||||
|
||||
@ -641,6 +660,7 @@ static int rtw_power_on(struct rtw_dev *rtwdev)
|
||||
{
|
||||
struct rtw_chip_info *chip = rtwdev->chip;
|
||||
struct rtw_fw_state *fw = &rtwdev->fw;
|
||||
bool wifi_only;
|
||||
int ret;
|
||||
|
||||
ret = rtw_hci_setup(rtwdev);
|
||||
@ -684,6 +704,10 @@ static int rtw_power_on(struct rtw_dev *rtwdev)
|
||||
goto err_off;
|
||||
}
|
||||
|
||||
wifi_only = !rtwdev->efuse.btcoex;
|
||||
rtw_coex_power_on_setting(rtwdev);
|
||||
rtw_coex_init_hw_config(rtwdev, wifi_only);
|
||||
|
||||
return 0;
|
||||
|
||||
err_off:
|
||||
@ -722,10 +746,15 @@ static void rtw_power_off(struct rtw_dev *rtwdev)
|
||||
|
||||
void rtw_core_stop(struct rtw_dev *rtwdev)
|
||||
{
|
||||
struct rtw_coex *coex = &rtwdev->coex;
|
||||
|
||||
rtw_flag_clear(rtwdev, RTW_FLAG_RUNNING);
|
||||
rtw_flag_clear(rtwdev, RTW_FLAG_FW_RUNNING);
|
||||
|
||||
cancel_delayed_work_sync(&rtwdev->watch_dog_work);
|
||||
cancel_delayed_work_sync(&coex->bt_relink_work);
|
||||
cancel_delayed_work_sync(&coex->bt_reenable_work);
|
||||
cancel_delayed_work_sync(&coex->defreeze_work);
|
||||
|
||||
rtw_power_off(rtwdev);
|
||||
}
|
||||
@ -876,7 +905,6 @@ static int rtw_chip_parameter_setup(struct rtw_dev *rtwdev)
|
||||
struct rtw_chip_info *chip = rtwdev->chip;
|
||||
struct rtw_hal *hal = &rtwdev->hal;
|
||||
struct rtw_efuse *efuse = &rtwdev->efuse;
|
||||
u32 wl_bt_pwr_ctrl;
|
||||
int ret = 0;
|
||||
|
||||
switch (rtw_hci_type(rtwdev)) {
|
||||
@ -888,9 +916,6 @@ static int rtw_chip_parameter_setup(struct rtw_dev *rtwdev)
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
wl_bt_pwr_ctrl = rtw_read32(rtwdev, REG_WL_BT_PWR_CTRL);
|
||||
if (wl_bt_pwr_ctrl & BIT_BT_FUNC_EN)
|
||||
rtwdev->efuse.btcoex = true;
|
||||
hal->chip_version = rtw_read32(rtwdev, REG_SYS_CFG1);
|
||||
hal->fab_version = BIT_GET_VENDOR_ID(hal->chip_version) >> 2;
|
||||
hal->cut_version = BIT_GET_CHIP_VER(hal->chip_version);
|
||||
@ -1044,11 +1069,14 @@ static int rtw_chip_efuse_info_setup(struct rtw_dev *rtwdev)
|
||||
efuse->lna_type_5g = 0;
|
||||
if (efuse->channel_plan == 0xff)
|
||||
efuse->channel_plan = 0x7f;
|
||||
if (efuse->rf_board_option == 0xff)
|
||||
efuse->rf_board_option = 0;
|
||||
if (efuse->bt_setting & BIT(0))
|
||||
efuse->share_ant = true;
|
||||
if (efuse->regd == 0xff)
|
||||
efuse->regd = 0;
|
||||
|
||||
efuse->btcoex = (efuse->rf_board_option & 0xe0) == 0x20;
|
||||
efuse->ext_pa_2g = efuse->pa_type_2g & BIT(4) ? 1 : 0;
|
||||
efuse->ext_lna_2g = efuse->lna_type_2g & BIT(3) ? 1 : 0;
|
||||
efuse->ext_pa_5g = efuse->pa_type_5g & BIT(0) ? 1 : 0;
|
||||
@ -1111,6 +1139,7 @@ EXPORT_SYMBOL(rtw_chip_info_setup);
|
||||
|
||||
int rtw_core_init(struct rtw_dev *rtwdev)
|
||||
{
|
||||
struct rtw_coex *coex = &rtwdev->coex;
|
||||
int ret;
|
||||
|
||||
INIT_LIST_HEAD(&rtwdev->rsvd_page_list);
|
||||
@ -1120,8 +1149,12 @@ int rtw_core_init(struct rtw_dev *rtwdev)
|
||||
|
||||
INIT_DELAYED_WORK(&rtwdev->watch_dog_work, rtw_watch_dog_work);
|
||||
INIT_DELAYED_WORK(&rtwdev->lps_work, rtw_lps_work);
|
||||
INIT_DELAYED_WORK(&coex->bt_relink_work, rtw_coex_bt_relink_work);
|
||||
INIT_DELAYED_WORK(&coex->bt_reenable_work, rtw_coex_bt_reenable_work);
|
||||
INIT_DELAYED_WORK(&coex->defreeze_work, rtw_coex_defreeze_work);
|
||||
INIT_WORK(&rtwdev->c2h_work, rtw_c2h_work);
|
||||
skb_queue_head_init(&rtwdev->c2h_queue);
|
||||
skb_queue_head_init(&rtwdev->coex.queue);
|
||||
skb_queue_head_init(&rtwdev->tx_report.queue);
|
||||
|
||||
spin_lock_init(&rtwdev->dm_lock);
|
||||
@ -1130,8 +1163,11 @@ int rtw_core_init(struct rtw_dev *rtwdev)
|
||||
spin_lock_init(&rtwdev->tx_report.q_lock);
|
||||
|
||||
mutex_init(&rtwdev->mutex);
|
||||
mutex_init(&rtwdev->coex.mutex);
|
||||
mutex_init(&rtwdev->hal.tx_power_mutex);
|
||||
|
||||
init_waitqueue_head(&rtwdev->coex.wait);
|
||||
|
||||
rtwdev->sec.total_cam_num = 32;
|
||||
rtwdev->hal.current_channel = 1;
|
||||
set_bit(RTW_BC_MC_MACID, rtwdev->mac_id_map);
|
||||
@ -1174,6 +1210,7 @@ void rtw_core_deinit(struct rtw_dev *rtwdev)
|
||||
}
|
||||
|
||||
mutex_destroy(&rtwdev->mutex);
|
||||
mutex_destroy(&rtwdev->coex.mutex);
|
||||
mutex_destroy(&rtwdev->hal.tx_power_mutex);
|
||||
}
|
||||
EXPORT_SYMBOL(rtw_core_deinit);
|
||||
|
||||
@ -310,6 +310,7 @@ enum rtw_flags {
|
||||
RTW_FLAG_INACTIVE_PS,
|
||||
RTW_FLAG_LEISURE_PS,
|
||||
RTW_FLAG_DIG_DISABLE,
|
||||
RTW_FLAG_BUSY_TRAFFIC,
|
||||
|
||||
NUM_OF_RTW_FLAGS,
|
||||
};
|
||||
@ -640,6 +641,16 @@ struct rtw_chip_ops {
|
||||
void (*cfg_ldo25)(struct rtw_dev *rtwdev, bool enable);
|
||||
void (*false_alarm_statistics)(struct rtw_dev *rtwdev);
|
||||
void (*do_iqk)(struct rtw_dev *rtwdev);
|
||||
|
||||
/* for coex */
|
||||
void (*coex_set_init)(struct rtw_dev *rtwdev);
|
||||
void (*coex_set_ant_switch)(struct rtw_dev *rtwdev,
|
||||
u8 ctrl_type, u8 pos_type);
|
||||
void (*coex_set_gnt_fix)(struct rtw_dev *rtwdev);
|
||||
void (*coex_set_gnt_debug)(struct rtw_dev *rtwdev);
|
||||
void (*coex_set_rfe_type)(struct rtw_dev *rtwdev);
|
||||
void (*coex_set_wl_tx_power)(struct rtw_dev *rtwdev, u8 wl_pwr);
|
||||
void (*coex_set_wl_rx_gain)(struct rtw_dev *rtwdev, bool low_gain);
|
||||
};
|
||||
|
||||
#define RTW_PWR_POLLING_CNT 20000
|
||||
@ -852,6 +863,216 @@ struct rtw_chip_info {
|
||||
|
||||
const struct rtw_rfe_def *rfe_defs;
|
||||
u32 rfe_defs_size;
|
||||
|
||||
/* coex paras */
|
||||
u32 coex_para_ver;
|
||||
u8 bt_desired_ver;
|
||||
bool scbd_support;
|
||||
bool new_scbd10_def; /* true: fix 2M(8822c) */
|
||||
u8 pstdma_type; /* 0: LPSoff, 1:LPSon */
|
||||
u8 bt_rssi_type;
|
||||
u8 ant_isolation;
|
||||
u8 rssi_tolerance;
|
||||
u8 table_sant_num;
|
||||
u8 table_nsant_num;
|
||||
u8 tdma_sant_num;
|
||||
u8 tdma_nsant_num;
|
||||
u8 bt_afh_span_bw20;
|
||||
u8 bt_afh_span_bw40;
|
||||
u8 afh_5g_num;
|
||||
u8 wl_rf_para_num;
|
||||
const u8 *bt_rssi_step;
|
||||
const u8 *wl_rssi_step;
|
||||
const struct coex_table_para *table_nsant;
|
||||
const struct coex_table_para *table_sant;
|
||||
const struct coex_tdma_para *tdma_sant;
|
||||
const struct coex_tdma_para *tdma_nsant;
|
||||
const struct coex_rf_para *wl_rf_para_tx;
|
||||
const struct coex_rf_para *wl_rf_para_rx;
|
||||
const struct coex_5g_afh_map *afh_5g;
|
||||
};
|
||||
|
||||
enum rtw_coex_bt_state_cnt {
|
||||
COEX_CNT_BT_RETRY,
|
||||
COEX_CNT_BT_REINIT,
|
||||
COEX_CNT_BT_REENABLE,
|
||||
COEX_CNT_BT_POPEVENT,
|
||||
COEX_CNT_BT_SETUPLINK,
|
||||
COEX_CNT_BT_IGNWLANACT,
|
||||
COEX_CNT_BT_INQ,
|
||||
COEX_CNT_BT_PAGE,
|
||||
COEX_CNT_BT_ROLESWITCH,
|
||||
COEX_CNT_BT_AFHUPDATE,
|
||||
COEX_CNT_BT_INFOUPDATE,
|
||||
COEX_CNT_BT_IQK,
|
||||
COEX_CNT_BT_IQKFAIL,
|
||||
|
||||
COEX_CNT_BT_MAX
|
||||
};
|
||||
|
||||
enum rtw_coex_wl_state_cnt {
|
||||
COEX_CNT_WL_CONNPKT,
|
||||
COEX_CNT_WL_COEXRUN,
|
||||
COEX_CNT_WL_NOISY0,
|
||||
COEX_CNT_WL_NOISY1,
|
||||
COEX_CNT_WL_NOISY2,
|
||||
COEX_CNT_WL_5MS_NOEXTEND,
|
||||
COEX_CNT_WL_FW_NOTIFY,
|
||||
|
||||
COEX_CNT_WL_MAX
|
||||
};
|
||||
|
||||
struct rtw_coex_rfe {
|
||||
bool ant_switch_exist;
|
||||
bool ant_switch_diversity;
|
||||
bool ant_switch_with_bt;
|
||||
u8 rfe_module_type;
|
||||
u8 ant_switch_polarity;
|
||||
|
||||
/* true if WLG at BTG, else at WLAG */
|
||||
bool wlg_at_btg;
|
||||
};
|
||||
|
||||
struct rtw_coex_dm {
|
||||
bool cur_ps_tdma_on;
|
||||
bool cur_wl_rx_low_gain_en;
|
||||
|
||||
u8 reason;
|
||||
u8 bt_rssi_state[4];
|
||||
u8 wl_rssi_state[4];
|
||||
u8 wl_ch_info[3];
|
||||
u8 cur_ps_tdma;
|
||||
u8 cur_table;
|
||||
u8 ps_tdma_para[5];
|
||||
u8 cur_bt_pwr_lvl;
|
||||
u8 cur_bt_lna_lvl;
|
||||
u8 cur_wl_pwr_lvl;
|
||||
u8 bt_status;
|
||||
u32 cur_ant_pos_type;
|
||||
u32 cur_switch_status;
|
||||
u32 setting_tdma;
|
||||
};
|
||||
|
||||
#define COEX_BTINFO_SRC_WL_FW 0x0
|
||||
#define COEX_BTINFO_SRC_BT_RSP 0x1
|
||||
#define COEX_BTINFO_SRC_BT_ACT 0x2
|
||||
#define COEX_BTINFO_SRC_BT_IQK 0x3
|
||||
#define COEX_BTINFO_SRC_BT_SCBD 0x4
|
||||
#define COEX_BTINFO_SRC_MAX 0x5
|
||||
|
||||
#define COEX_INFO_FTP BIT(7)
|
||||
#define COEX_INFO_A2DP BIT(6)
|
||||
#define COEX_INFO_HID BIT(5)
|
||||
#define COEX_INFO_SCO_BUSY BIT(4)
|
||||
#define COEX_INFO_ACL_BUSY BIT(3)
|
||||
#define COEX_INFO_INQ_PAGE BIT(2)
|
||||
#define COEX_INFO_SCO_ESCO BIT(1)
|
||||
#define COEX_INFO_CONNECTION BIT(0)
|
||||
#define COEX_BTINFO_LENGTH_MAX 10
|
||||
|
||||
struct rtw_coex_stat {
|
||||
bool bt_disabled;
|
||||
bool bt_disabled_pre;
|
||||
bool bt_link_exist;
|
||||
bool bt_whck_test;
|
||||
bool bt_inq_page;
|
||||
bool bt_inq;
|
||||
bool bt_page;
|
||||
bool bt_ble_voice;
|
||||
bool bt_ble_exist;
|
||||
bool bt_hfp_exist;
|
||||
bool bt_a2dp_exist;
|
||||
bool bt_hid_exist;
|
||||
bool bt_pan_exist; /* PAN or OPP */
|
||||
bool bt_opp_exist; /* OPP only */
|
||||
bool bt_acl_busy;
|
||||
bool bt_fix_2M;
|
||||
bool bt_setup_link;
|
||||
bool bt_multi_link;
|
||||
bool bt_a2dp_sink;
|
||||
bool bt_a2dp_active;
|
||||
bool bt_reenable;
|
||||
bool bt_ble_scan_en;
|
||||
bool bt_init_scan;
|
||||
bool bt_slave;
|
||||
bool bt_418_hid_exist;
|
||||
bool bt_mailbox_reply;
|
||||
|
||||
bool wl_under_lps;
|
||||
bool wl_under_ips;
|
||||
bool wl_hi_pri_task1;
|
||||
bool wl_hi_pri_task2;
|
||||
bool wl_force_lps_ctrl;
|
||||
bool wl_gl_busy;
|
||||
bool wl_linkscan_proc;
|
||||
bool wl_ps_state_fail;
|
||||
bool wl_tx_limit_en;
|
||||
bool wl_ampdu_limit_en;
|
||||
bool wl_connected;
|
||||
bool wl_slot_extend;
|
||||
bool wl_cck_lock;
|
||||
bool wl_cck_lock_pre;
|
||||
bool wl_cck_lock_ever;
|
||||
|
||||
u32 bt_supported_version;
|
||||
u32 bt_supported_feature;
|
||||
s8 bt_rssi;
|
||||
u8 kt_ver;
|
||||
u8 gnt_workaround_state;
|
||||
u8 tdma_timer_base;
|
||||
u8 bt_profile_num;
|
||||
u8 bt_info_c2h[COEX_BTINFO_SRC_MAX][COEX_BTINFO_LENGTH_MAX];
|
||||
u8 bt_info_lb2;
|
||||
u8 bt_info_lb3;
|
||||
u8 bt_info_hb0;
|
||||
u8 bt_info_hb1;
|
||||
u8 bt_info_hb2;
|
||||
u8 bt_info_hb3;
|
||||
u8 bt_ble_scan_type;
|
||||
u8 bt_hid_pair_num;
|
||||
u8 bt_hid_slot;
|
||||
u8 bt_a2dp_bitpool;
|
||||
u8 bt_iqk_state;
|
||||
|
||||
u8 wl_noisy_level;
|
||||
u8 wl_fw_dbg_info[10];
|
||||
u8 wl_fw_dbg_info_pre[10];
|
||||
u8 wl_coex_mode;
|
||||
u8 ampdu_max_time;
|
||||
u8 wl_tput_dir;
|
||||
|
||||
u16 score_board;
|
||||
u16 retry_limit;
|
||||
|
||||
/* counters to record bt states */
|
||||
u32 cnt_bt[COEX_CNT_BT_MAX];
|
||||
|
||||
/* counters to record wifi states */
|
||||
u32 cnt_wl[COEX_CNT_WL_MAX];
|
||||
|
||||
u32 darfrc;
|
||||
u32 darfrch;
|
||||
};
|
||||
|
||||
struct rtw_coex {
|
||||
/* protects coex info request section */
|
||||
struct mutex mutex;
|
||||
struct sk_buff_head queue;
|
||||
wait_queue_head_t wait;
|
||||
|
||||
bool under_5g;
|
||||
bool stop_dm;
|
||||
bool freeze;
|
||||
bool freerun;
|
||||
bool wl_rf_off;
|
||||
|
||||
struct rtw_coex_stat stat;
|
||||
struct rtw_coex_dm dm;
|
||||
struct rtw_coex_rfe rfe;
|
||||
|
||||
struct delayed_work bt_relink_work;
|
||||
struct delayed_work bt_reenable_work;
|
||||
struct delayed_work defreeze_work;
|
||||
};
|
||||
|
||||
#define DACK_MSBK_BACKUP_NUM 0xf
|
||||
@ -861,6 +1082,16 @@ struct rtw_dm_info {
|
||||
u32 cck_fa_cnt;
|
||||
u32 ofdm_fa_cnt;
|
||||
u32 total_fa_cnt;
|
||||
|
||||
u32 cck_ok_cnt;
|
||||
u32 cck_err_cnt;
|
||||
u32 ofdm_ok_cnt;
|
||||
u32 ofdm_err_cnt;
|
||||
u32 ht_ok_cnt;
|
||||
u32 ht_err_cnt;
|
||||
u32 vht_ok_cnt;
|
||||
u32 vht_err_cnt;
|
||||
|
||||
u8 min_rssi;
|
||||
u8 pre_min_rssi;
|
||||
u16 fa_history[4];
|
||||
@ -888,6 +1119,7 @@ struct rtw_efuse {
|
||||
u8 addr[ETH_ALEN];
|
||||
u8 channel_plan;
|
||||
u8 country_code[2];
|
||||
u8 rf_board_option;
|
||||
u8 rfe_option;
|
||||
u8 thermal_meter;
|
||||
u8 crystal_cap;
|
||||
@ -1047,6 +1279,7 @@ struct rtw_dev {
|
||||
struct rtw_regulatory regd;
|
||||
|
||||
struct rtw_dm_info dm_info;
|
||||
struct rtw_coex coex;
|
||||
|
||||
/* ensures exclusive access from mac80211 callbacks */
|
||||
struct mutex mutex;
|
||||
|
||||
@ -6,6 +6,7 @@
|
||||
#include "fw.h"
|
||||
#include "ps.h"
|
||||
#include "mac.h"
|
||||
#include "coex.h"
|
||||
#include "debug.h"
|
||||
|
||||
static int rtw_ips_pwr_up(struct rtw_dev *rtwdev)
|
||||
@ -26,6 +27,8 @@ int rtw_enter_ips(struct rtw_dev *rtwdev)
|
||||
{
|
||||
rtw_flag_set(rtwdev, RTW_FLAG_INACTIVE_PS);
|
||||
|
||||
rtw_coex_ips_notify(rtwdev, COEX_IPS_ENTER);
|
||||
|
||||
rtw_core_stop(rtwdev);
|
||||
|
||||
return 0;
|
||||
@ -53,6 +56,8 @@ int rtw_leave_ips(struct rtw_dev *rtwdev)
|
||||
|
||||
rtw_iterate_vifs_atomic(rtwdev, rtw_restore_port_cfg_iter, rtwdev);
|
||||
|
||||
rtw_coex_ips_notify(rtwdev, COEX_IPS_LEAVE);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -67,6 +72,8 @@ static void rtw_leave_lps_core(struct rtw_dev *rtwdev)
|
||||
|
||||
rtw_fw_set_pwr_mode(rtwdev);
|
||||
rtw_flag_clear(rtwdev, RTW_FLAG_LEISURE_PS);
|
||||
|
||||
rtw_coex_lps_notify(rtwdev, COEX_LPS_DISABLE);
|
||||
}
|
||||
|
||||
static void rtw_enter_lps_core(struct rtw_dev *rtwdev)
|
||||
@ -78,6 +85,8 @@ static void rtw_enter_lps_core(struct rtw_dev *rtwdev)
|
||||
conf->rlbm = 1;
|
||||
conf->smart_ps = 2;
|
||||
|
||||
rtw_coex_lps_notify(rtwdev, COEX_LPS_ENABLE);
|
||||
|
||||
rtw_fw_set_pwr_mode(rtwdev);
|
||||
rtw_flag_set(rtwdev, RTW_FLAG_LEISURE_PS);
|
||||
}
|
||||
|
||||
@ -37,17 +37,28 @@
|
||||
|
||||
#define REG_GPIO_MUXCFG 0x0040
|
||||
#define BIT_FSPI_EN BIT(19)
|
||||
#define BIT_BT_AOD_GPIO3 BIT(9)
|
||||
#define BIT_BT_PTA_EN BIT(5)
|
||||
#define BIT_WLRFE_4_5_EN BIT(2)
|
||||
|
||||
#define REG_LED_CFG 0x004C
|
||||
#define BIT_LNAON_SEL_EN BIT(26)
|
||||
#define BIT_PAPE_SEL_EN BIT(25)
|
||||
#define BIT_DPDT_WL_SEL BIT(24)
|
||||
#define BIT_DPDT_SEL_EN BIT(23)
|
||||
#define REG_PAD_CTRL1 0x0064
|
||||
#define BIT_PAPE_WLBT_SEL BIT(29)
|
||||
#define BIT_LNAON_WLBT_SEL BIT(28)
|
||||
#define BIT_BTGP_JTAG_EN BIT(24)
|
||||
#define BIT_BTGP_SPI_EN BIT(20)
|
||||
#define BIT_LED1DIS BIT(15)
|
||||
#define BIT_SW_DPDT_SEL_DATA BIT(0)
|
||||
#define REG_WL_BT_PWR_CTRL 0x0068
|
||||
#define BIT_BT_FUNC_EN BIT(18)
|
||||
#define BIT_BT_DIG_CLK_EN BIT(8)
|
||||
#define REG_SYS_SDIO_CTRL 0x0070
|
||||
#define BIT_DBG_GNT_WL_BT BIT(27)
|
||||
#define BIT_LTE_MUX_CTRL_PATH BIT(26)
|
||||
#define REG_HCI_OPT_CTRL 0x0074
|
||||
|
||||
#define REG_MCUFW_CTRL 0x0080
|
||||
@ -70,6 +81,8 @@
|
||||
#define FW_READY_MASK 0xffff
|
||||
|
||||
#define REG_WLRF1 0x00EC
|
||||
#define REG_WIFI_BT_INFO 0x00AA
|
||||
#define BIT_BT_INT_EN BIT(15)
|
||||
#define REG_SYS_CFG1 0x00F0
|
||||
#define BIT_RTL_ID BIT(23)
|
||||
#define BIT_RF_TYPE_ID BIT(27)
|
||||
@ -187,6 +200,7 @@
|
||||
#define REG_LIFETIME_EN 0x0426
|
||||
#define BIT_BA_PARSER_EN BIT(5)
|
||||
#define REG_SPEC_SIFS 0x0428
|
||||
#define REG_RETRY_LIMIT 0x042a
|
||||
#define REG_DARFRC 0x0430
|
||||
#define REG_DARFRCH 0x0434
|
||||
#define REG_RARFRCH 0x043C
|
||||
@ -199,18 +213,25 @@
|
||||
#define REG_AMPDU_MAX_TIME_V1 0x0455
|
||||
#define REG_BCNQ1_BDNY_V1 0x0456
|
||||
#define REG_TX_HANG_CTRL 0x045E
|
||||
#define BIT_EN_GNT_BT_AWAKE BIT(3)
|
||||
#define BIT_EN_EOF_V1 BIT(2)
|
||||
#define REG_DATA_SC 0x0483
|
||||
#define REG_ARFR4 0x049C
|
||||
#define BIT_WL_RFK BIT(0)
|
||||
#define REG_ARFRH4 0x04A0
|
||||
#define REG_ARFR5 0x04A4
|
||||
#define REG_ARFRH5 0x04A8
|
||||
#define REG_SW_AMPDU_BURST_MODE_CTRL 0x04BC
|
||||
#define BIT_PRE_TX_CMD BIT(6)
|
||||
#define REG_QUEUE_CTRL 0x04C6
|
||||
#define BIT_PTA_WL_TX_EN BIT(4)
|
||||
#define BIT_PTA_EDCCA_EN BIT(5)
|
||||
#define REG_PROT_MODE_CTRL 0x04C8
|
||||
#define REG_BAR_MODE_CTRL 0x04CC
|
||||
#define REG_PRECNT_CTRL 0x04E5
|
||||
#define BIT_BTCCA_CTRL (BIT(0) | BIT(1))
|
||||
#define BIT_EN_PRECNT BIT(11)
|
||||
#define REG_DUMMY_PAGE4_V1 0x04FC
|
||||
|
||||
#define REG_EDCA_VO_PARAM 0x0500
|
||||
#define REG_EDCA_VI_PARAM 0x0504
|
||||
@ -297,11 +318,34 @@
|
||||
#define REG_RXFLTMAP0 0x06A0
|
||||
#define REG_RXFLTMAP1 0x06A2
|
||||
#define REG_RXFLTMAP2 0x06A4
|
||||
#define REG_BT_COEX_TABLE0 0x06C0
|
||||
#define REG_BT_COEX_TABLE1 0x06C4
|
||||
#define REG_BT_COEX_BRK_TABLE 0x06C8
|
||||
#define REG_BT_COEX_TABLE_H 0x06CC
|
||||
#define REG_BT_COEX_TABLE_H1 0x06CD
|
||||
#define REG_BT_COEX_TABLE_H2 0x06CE
|
||||
#define REG_BT_COEX_TABLE_H3 0x06CF
|
||||
#define REG_BBPSF_CTRL 0x06DC
|
||||
|
||||
#define REG_BT_COEX_V2 0x0763
|
||||
#define BIT_GNT_BT_POLARITY BIT(4)
|
||||
#define BIT_LTE_COEX_EN BIT(7)
|
||||
#define REG_BT_STAT_CTRL 0x0778
|
||||
#define REG_BT_TDMA_TIME 0x0790
|
||||
#define REG_WMAC_OPTION_FUNCTION 0x07D0
|
||||
#define REG_WMAC_OPTION_FUNCTION_1 0x07D4
|
||||
|
||||
#define REG_RX_GAIN_EN 0x081c
|
||||
|
||||
#define REG_RFE_CTRL_E 0x0974
|
||||
|
||||
#define REG_RFE_CTRL8 0x0cb4
|
||||
#define BIT_MASK_RFE_SEL89 GENMASK(7, 0)
|
||||
#define REG_RFE_INV8 0x0cbd
|
||||
#define BIT_MASK_RFE_INV89 GENMASK(1, 0)
|
||||
#define REG_RFE_INV16 0x0cbe
|
||||
#define BIT_RFE_BUF_EN BIT(3)
|
||||
|
||||
#define REG_ANAPAR_XTAL_0 0x1040
|
||||
#define REG_CPU_DMEM_CON 0x1080
|
||||
#define BIT_WL_PLATFORM_RST BIT(16)
|
||||
@ -407,15 +451,33 @@
|
||||
#define LTECOEX_WRITE_DATA REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1
|
||||
#define LTECOEX_READ_DATA REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1
|
||||
|
||||
#define REG_IGN_GNT_BT1 0x1860
|
||||
|
||||
#define REG_RFESEL_CTRL 0x1990
|
||||
|
||||
#define REG_NOMASK_TXBT 0x1ca7
|
||||
#define REG_ANAPAR 0x1c30
|
||||
#define BIT_ANAPAR_BTPS BIT(22)
|
||||
#define REG_RSTB_SEL 0x1c38
|
||||
|
||||
#define REG_IGN_GNTBT4 0x4160
|
||||
|
||||
#define RF_MODOPT 0x01
|
||||
#define RF_DTXLOK 0x08
|
||||
#define RF_CFGCH 0x18
|
||||
#define RF_RCK 0x1d
|
||||
#define RF_LUTWA 0x33
|
||||
#define RF_LUTWD1 0x3e
|
||||
#define RF_LUTWD0 0x3f
|
||||
#define RF_XTALX2 0xb8
|
||||
#define RF_MALSEL 0xbe
|
||||
#define RF_RCKD 0xde
|
||||
#define RF_LUTDBG 0xdf
|
||||
#define RF_LUTWE2 0xee
|
||||
#define RF_LUTWE 0xef
|
||||
|
||||
#define LTE_COEX_CTRL 0x38
|
||||
#define LTE_WL_TRX_CTRL 0xa0
|
||||
#define LTE_BT_TRX_CTRL 0xa4
|
||||
|
||||
#endif
|
||||
|
||||
@ -3,6 +3,7 @@
|
||||
*/
|
||||
|
||||
#include "main.h"
|
||||
#include "coex.h"
|
||||
#include "fw.h"
|
||||
#include "tx.h"
|
||||
#include "rx.h"
|
||||
@ -31,6 +32,7 @@ static int rtw8822b_read_efuse(struct rtw_dev *rtwdev, u8 *log_map)
|
||||
map = (struct rtw8822b_efuse *)log_map;
|
||||
|
||||
efuse->rfe_option = map->rfe_option;
|
||||
efuse->rf_board_option = map->rf_board_option;
|
||||
efuse->crystal_cap = map->xtal_k;
|
||||
efuse->pa_type_2g = map->pa_type;
|
||||
efuse->pa_type_5g = map->pa_type;
|
||||
@ -104,24 +106,6 @@ static void rtw8822b_phy_set_param(struct rtw_dev *rtwdev)
|
||||
rtw_phy_init(rtwdev);
|
||||
|
||||
rtw8822b_phy_rfe_init(rtwdev);
|
||||
|
||||
/* wifi path controller */
|
||||
rtw_write32_mask(rtwdev, 0x70, 0x4000000, 1);
|
||||
/* BB control */
|
||||
rtw_write32_mask(rtwdev, 0x4c, 0x01800000, 0x2);
|
||||
/* antenna mux switch */
|
||||
rtw_write8(rtwdev, 0x974, 0xff);
|
||||
rtw_write32_mask(rtwdev, 0x1990, 0x300, 0);
|
||||
rtw_write32_mask(rtwdev, 0xcbc, 0x80000, 0x0);
|
||||
/* SW control */
|
||||
rtw_write8(rtwdev, 0xcb4, 0x77);
|
||||
/* switch to WL side controller and gnt_wl gnt_bt debug signal */
|
||||
rtw_write32_mask(rtwdev, 0x70, 0xff000000, 0x0e);
|
||||
/* gnt_wl = 1, gnt_bt = 0 */
|
||||
rtw_write32(rtwdev, 0x1704, 0x7700);
|
||||
rtw_write32(rtwdev, 0x1700, 0xc00f0038);
|
||||
/* switch for WL 2G */
|
||||
rtw_write8(rtwdev, 0xcbd, 0x2);
|
||||
}
|
||||
|
||||
#define WLAN_SLOT_TIME 0x09
|
||||
@ -960,6 +944,7 @@ static void rtw8822b_false_alarm_statistics(struct rtw_dev *rtwdev)
|
||||
u32 cck_enable;
|
||||
u32 cck_fa_cnt;
|
||||
u32 ofdm_fa_cnt;
|
||||
u32 crc32_cnt;
|
||||
|
||||
cck_enable = rtw_read32(rtwdev, 0x808) & BIT(28);
|
||||
cck_fa_cnt = rtw_read16(rtwdev, 0xa5c);
|
||||
@ -970,6 +955,19 @@ static void rtw8822b_false_alarm_statistics(struct rtw_dev *rtwdev)
|
||||
dm_info->total_fa_cnt = ofdm_fa_cnt;
|
||||
dm_info->total_fa_cnt += cck_enable ? cck_fa_cnt : 0;
|
||||
|
||||
crc32_cnt = rtw_read32(rtwdev, 0xf04);
|
||||
dm_info->cck_ok_cnt = crc32_cnt & 0xffff;
|
||||
dm_info->cck_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
|
||||
crc32_cnt = rtw_read32(rtwdev, 0xf14);
|
||||
dm_info->ofdm_ok_cnt = crc32_cnt & 0xffff;
|
||||
dm_info->ofdm_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
|
||||
crc32_cnt = rtw_read32(rtwdev, 0xf10);
|
||||
dm_info->ht_ok_cnt = crc32_cnt & 0xffff;
|
||||
dm_info->ht_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
|
||||
crc32_cnt = rtw_read32(rtwdev, 0xf0c);
|
||||
dm_info->vht_ok_cnt = crc32_cnt & 0xffff;
|
||||
dm_info->vht_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
|
||||
|
||||
rtw_write32_set(rtwdev, 0x9a4, BIT(17));
|
||||
rtw_write32_clr(rtwdev, 0x9a4, BIT(17));
|
||||
rtw_write32_clr(rtwdev, 0xa2c, BIT(15));
|
||||
@ -1003,6 +1001,254 @@ static void rtw8822b_do_iqk(struct rtw_dev *rtwdev)
|
||||
counter, reload, ++do_iqk_cnt, iqk_fail_mask);
|
||||
}
|
||||
|
||||
static void rtw8822b_coex_cfg_init(struct rtw_dev *rtwdev)
|
||||
{
|
||||
/* enable TBTT nterrupt */
|
||||
rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION);
|
||||
|
||||
/* BT report packet sample rate */
|
||||
/* 0x790[5:0]=0x5 */
|
||||
rtw_write8_set(rtwdev, REG_BT_TDMA_TIME, 0x05);
|
||||
|
||||
/* enable BT counter statistics */
|
||||
rtw_write8(rtwdev, REG_BT_STAT_CTRL, 0x1);
|
||||
|
||||
/* enable PTA (3-wire function form BT side) */
|
||||
rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_PTA_EN);
|
||||
rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_AOD_GPIO3);
|
||||
|
||||
/* enable PTA (tx/rx signal form WiFi side) */
|
||||
rtw_write8_set(rtwdev, REG_QUEUE_CTRL, BIT_PTA_WL_TX_EN);
|
||||
/* wl tx signal to PTA not case EDCCA */
|
||||
rtw_write8_clr(rtwdev, REG_QUEUE_CTRL, BIT_PTA_EDCCA_EN);
|
||||
/* GNT_BT=1 while select both */
|
||||
rtw_write8_set(rtwdev, REG_BT_COEX_V2, BIT_GNT_BT_POLARITY);
|
||||
}
|
||||
|
||||
static void rtw8822b_coex_cfg_ant_switch(struct rtw_dev *rtwdev,
|
||||
u8 ctrl_type, u8 pos_type)
|
||||
{
|
||||
struct rtw_coex *coex = &rtwdev->coex;
|
||||
struct rtw_coex_dm *coex_dm = &coex->dm;
|
||||
struct rtw_coex_rfe *coex_rfe = &coex->rfe;
|
||||
bool polarity_inverse;
|
||||
u8 regval = 0;
|
||||
|
||||
if (((ctrl_type << 8) + pos_type) == coex_dm->cur_switch_status)
|
||||
return;
|
||||
|
||||
coex_dm->cur_switch_status = (ctrl_type << 8) + pos_type;
|
||||
|
||||
if (coex_rfe->ant_switch_diversity &&
|
||||
ctrl_type == COEX_SWITCH_CTRL_BY_BBSW)
|
||||
ctrl_type = COEX_SWITCH_CTRL_BY_ANTDIV;
|
||||
|
||||
polarity_inverse = (coex_rfe->ant_switch_polarity == 1);
|
||||
|
||||
switch (ctrl_type) {
|
||||
default:
|
||||
case COEX_SWITCH_CTRL_BY_BBSW:
|
||||
/* 0x4c[23] = 0 */
|
||||
rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0);
|
||||
/* 0x4c[24] = 1 */
|
||||
rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x1);
|
||||
/* BB SW, DPDT use RFE_ctrl8 and RFE_ctrl9 as ctrl pin */
|
||||
rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 0x77);
|
||||
|
||||
if (pos_type == COEX_SWITCH_TO_WLG_BT) {
|
||||
if (coex_rfe->rfe_module_type != 0x4 &&
|
||||
coex_rfe->rfe_module_type != 0x2)
|
||||
regval = 0x3;
|
||||
else
|
||||
regval = (!polarity_inverse ? 0x2 : 0x1);
|
||||
} else if (pos_type == COEX_SWITCH_TO_WLG) {
|
||||
regval = (!polarity_inverse ? 0x2 : 0x1);
|
||||
} else {
|
||||
regval = (!polarity_inverse ? 0x1 : 0x2);
|
||||
}
|
||||
|
||||
rtw_write8_mask(rtwdev, REG_RFE_INV8, BIT_MASK_RFE_INV89, regval);
|
||||
break;
|
||||
case COEX_SWITCH_CTRL_BY_PTA:
|
||||
/* 0x4c[23] = 0 */
|
||||
rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0);
|
||||
/* 0x4c[24] = 1 */
|
||||
rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x1);
|
||||
/* PTA, DPDT use RFE_ctrl8 and RFE_ctrl9 as ctrl pin */
|
||||
rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 0x66);
|
||||
|
||||
regval = (!polarity_inverse ? 0x2 : 0x1);
|
||||
rtw_write8_mask(rtwdev, REG_RFE_INV8, BIT_MASK_RFE_INV89, regval);
|
||||
break;
|
||||
case COEX_SWITCH_CTRL_BY_ANTDIV:
|
||||
/* 0x4c[23] = 0 */
|
||||
rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0);
|
||||
/* 0x4c[24] = 1 */
|
||||
rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x1);
|
||||
rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 0x88);
|
||||
break;
|
||||
case COEX_SWITCH_CTRL_BY_MAC:
|
||||
/* 0x4c[23] = 1 */
|
||||
rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x1);
|
||||
|
||||
regval = (!polarity_inverse ? 0x0 : 0x1);
|
||||
rtw_write8_mask(rtwdev, REG_PAD_CTRL1, BIT_SW_DPDT_SEL_DATA, regval);
|
||||
break;
|
||||
case COEX_SWITCH_CTRL_BY_FW:
|
||||
/* 0x4c[23] = 0 */
|
||||
rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0);
|
||||
/* 0x4c[24] = 1 */
|
||||
rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x1);
|
||||
break;
|
||||
case COEX_SWITCH_CTRL_BY_BT:
|
||||
/* 0x4c[23] = 0 */
|
||||
rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0);
|
||||
/* 0x4c[24] = 0 */
|
||||
rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x0);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static void rtw8822b_coex_cfg_gnt_fix(struct rtw_dev *rtwdev)
|
||||
{
|
||||
}
|
||||
|
||||
static void rtw8822b_coex_cfg_gnt_debug(struct rtw_dev *rtwdev)
|
||||
{
|
||||
rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 2, BIT_BTGP_SPI_EN >> 16, 0);
|
||||
rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 3, BIT_BTGP_JTAG_EN >> 24, 0);
|
||||
rtw_write8_mask(rtwdev, REG_GPIO_MUXCFG + 2, BIT_FSPI_EN >> 16, 0);
|
||||
rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 1, BIT_LED1DIS >> 8, 0);
|
||||
rtw_write8_mask(rtwdev, REG_SYS_SDIO_CTRL + 3, BIT_DBG_GNT_WL_BT >> 24, 0);
|
||||
}
|
||||
|
||||
static void rtw8822b_coex_cfg_rfe_type(struct rtw_dev *rtwdev)
|
||||
{
|
||||
struct rtw_coex *coex = &rtwdev->coex;
|
||||
struct rtw_coex_rfe *coex_rfe = &coex->rfe;
|
||||
struct rtw_efuse *efuse = &rtwdev->efuse;
|
||||
bool is_ext_fem = false;
|
||||
|
||||
coex_rfe->rfe_module_type = rtwdev->efuse.rfe_option;
|
||||
coex_rfe->ant_switch_polarity = 0;
|
||||
coex_rfe->ant_switch_diversity = false;
|
||||
if (coex_rfe->rfe_module_type == 0x12 ||
|
||||
coex_rfe->rfe_module_type == 0x15 ||
|
||||
coex_rfe->rfe_module_type == 0x16)
|
||||
coex_rfe->ant_switch_exist = false;
|
||||
else
|
||||
coex_rfe->ant_switch_exist = true;
|
||||
|
||||
if (coex_rfe->rfe_module_type == 2 ||
|
||||
coex_rfe->rfe_module_type == 4) {
|
||||
rtw_coex_write_scbd(rtwdev, COEX_SCBD_EXTFEM, true);
|
||||
is_ext_fem = true;
|
||||
} else {
|
||||
rtw_coex_write_scbd(rtwdev, COEX_SCBD_EXTFEM, false);
|
||||
}
|
||||
|
||||
coex_rfe->wlg_at_btg = false;
|
||||
|
||||
if (efuse->share_ant &&
|
||||
coex_rfe->ant_switch_exist && !is_ext_fem)
|
||||
coex_rfe->ant_switch_with_bt = true;
|
||||
else
|
||||
coex_rfe->ant_switch_with_bt = false;
|
||||
|
||||
/* Ext switch buffer mux */
|
||||
rtw_write8(rtwdev, REG_RFE_CTRL_E, 0xff);
|
||||
rtw_write8_mask(rtwdev, REG_RFESEL_CTRL + 1, 0x3, 0x0);
|
||||
rtw_write8_mask(rtwdev, REG_RFE_INV16, BIT_RFE_BUF_EN, 0x0);
|
||||
|
||||
/* Disable LTE Coex Function in WiFi side */
|
||||
rtw_coex_write_indirect_reg(rtwdev, LTE_COEX_CTRL, BIT_LTE_COEX_EN, 0);
|
||||
|
||||
/* BTC_CTT_WL_VS_LTE */
|
||||
rtw_coex_write_indirect_reg(rtwdev, LTE_WL_TRX_CTRL, MASKLWORD, 0xffff);
|
||||
|
||||
/* BTC_CTT_BT_VS_LTE */
|
||||
rtw_coex_write_indirect_reg(rtwdev, LTE_BT_TRX_CTRL, MASKLWORD, 0xffff);
|
||||
}
|
||||
|
||||
static void rtw8822b_coex_cfg_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr)
|
||||
{
|
||||
struct rtw_coex *coex = &rtwdev->coex;
|
||||
struct rtw_coex_dm *coex_dm = &coex->dm;
|
||||
static const u16 reg_addr[] = {0xc58, 0xe58};
|
||||
static const u8 wl_tx_power[] = {0xd8, 0xd4, 0xd0, 0xcc, 0xc8};
|
||||
u8 i, pwr;
|
||||
|
||||
if (wl_pwr == coex_dm->cur_wl_pwr_lvl)
|
||||
return;
|
||||
|
||||
coex_dm->cur_wl_pwr_lvl = wl_pwr;
|
||||
|
||||
if (coex_dm->cur_wl_pwr_lvl >= ARRAY_SIZE(wl_tx_power))
|
||||
coex_dm->cur_wl_pwr_lvl = ARRAY_SIZE(wl_tx_power) - 1;
|
||||
|
||||
pwr = wl_tx_power[coex_dm->cur_wl_pwr_lvl];
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(reg_addr); i++)
|
||||
rtw_write8_mask(rtwdev, reg_addr[i], 0xff, pwr);
|
||||
}
|
||||
|
||||
static void rtw8822b_coex_cfg_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain)
|
||||
{
|
||||
struct rtw_coex *coex = &rtwdev->coex;
|
||||
struct rtw_coex_dm *coex_dm = &coex->dm;
|
||||
/* WL Rx Low gain on */
|
||||
static const u32 wl_rx_low_gain_on[] = {
|
||||
0xff000003, 0xbd120003, 0xbe100003, 0xbf080003, 0xbf060003,
|
||||
0xbf050003, 0xbc140003, 0xbb160003, 0xba180003, 0xb91a0003,
|
||||
0xb81c0003, 0xb71e0003, 0xb4200003, 0xb5220003, 0xb4240003,
|
||||
0xb3260003, 0xb2280003, 0xb12a0003, 0xb02c0003, 0xaf2e0003,
|
||||
0xae300003, 0xad320003, 0xac340003, 0xab360003, 0x8d380003,
|
||||
0x8c3a0003, 0x8b3c0003, 0x8a3e0003, 0x6e400003, 0x6d420003,
|
||||
0x6c440003, 0x6b460003, 0x6a480003, 0x694a0003, 0x684c0003,
|
||||
0x674e0003, 0x66500003, 0x65520003, 0x64540003, 0x64560003,
|
||||
0x007e0403
|
||||
};
|
||||
|
||||
/* WL Rx Low gain off */
|
||||
static const u32 wl_rx_low_gain_off[] = {
|
||||
0xff000003, 0xf4120003, 0xf5100003, 0xf60e0003, 0xf70c0003,
|
||||
0xf80a0003, 0xf3140003, 0xf2160003, 0xf1180003, 0xf01a0003,
|
||||
0xef1c0003, 0xee1e0003, 0xed200003, 0xec220003, 0xeb240003,
|
||||
0xea260003, 0xe9280003, 0xe82a0003, 0xe72c0003, 0xe62e0003,
|
||||
0xe5300003, 0xc8320003, 0xc7340003, 0xc6360003, 0xc5380003,
|
||||
0xc43a0003, 0xc33c0003, 0xc23e0003, 0xc1400003, 0xc0420003,
|
||||
0xa5440003, 0xa4460003, 0xa3480003, 0xa24a0003, 0xa14c0003,
|
||||
0x834e0003, 0x82500003, 0x81520003, 0x80540003, 0x65560003,
|
||||
0x007e0403
|
||||
};
|
||||
u8 i;
|
||||
|
||||
if (low_gain == coex_dm->cur_wl_rx_low_gain_en)
|
||||
return;
|
||||
|
||||
coex_dm->cur_wl_rx_low_gain_en = low_gain;
|
||||
|
||||
if (coex_dm->cur_wl_rx_low_gain_en) {
|
||||
for (i = 0; i < ARRAY_SIZE(wl_rx_low_gain_on); i++)
|
||||
rtw_write32(rtwdev, REG_RX_GAIN_EN, wl_rx_low_gain_on[i]);
|
||||
|
||||
/* set Rx filter corner RCK offset */
|
||||
rtw_write_rf(rtwdev, RF_PATH_A, RF_RCKD, 0x2, 0x1);
|
||||
rtw_write_rf(rtwdev, RF_PATH_A, RF_RCK, 0x3f, 0x3f);
|
||||
rtw_write_rf(rtwdev, RF_PATH_B, RF_RCKD, 0x2, 0x1);
|
||||
rtw_write_rf(rtwdev, RF_PATH_B, RF_RCK, 0x3f, 0x3f);
|
||||
} else {
|
||||
for (i = 0; i < ARRAY_SIZE(wl_rx_low_gain_off); i++)
|
||||
rtw_write32(rtwdev, 0x81c, wl_rx_low_gain_off[i]);
|
||||
|
||||
/* set Rx filter corner RCK offset */
|
||||
rtw_write_rf(rtwdev, RF_PATH_A, RF_RCK, 0x3f, 0x4);
|
||||
rtw_write_rf(rtwdev, RF_PATH_A, RF_RCKD, 0x2, 0x0);
|
||||
rtw_write_rf(rtwdev, RF_PATH_B, RF_RCK, 0x3f, 0x4);
|
||||
rtw_write_rf(rtwdev, RF_PATH_B, RF_RCKD, 0x2, 0x0);
|
||||
}
|
||||
}
|
||||
|
||||
static struct rtw_pwr_seq_cmd trans_carddis_to_cardemu_8822b[] = {
|
||||
{0x0086,
|
||||
RTW_PWR_CUT_ALL_MSK,
|
||||
@ -1549,8 +1795,160 @@ static struct rtw_chip_ops rtw8822b_ops = {
|
||||
.cfg_ldo25 = rtw8822b_cfg_ldo25,
|
||||
.false_alarm_statistics = rtw8822b_false_alarm_statistics,
|
||||
.do_iqk = rtw8822b_do_iqk,
|
||||
|
||||
.coex_set_init = rtw8822b_coex_cfg_init,
|
||||
.coex_set_ant_switch = rtw8822b_coex_cfg_ant_switch,
|
||||
.coex_set_gnt_fix = rtw8822b_coex_cfg_gnt_fix,
|
||||
.coex_set_gnt_debug = rtw8822b_coex_cfg_gnt_debug,
|
||||
.coex_set_rfe_type = rtw8822b_coex_cfg_rfe_type,
|
||||
.coex_set_wl_tx_power = rtw8822b_coex_cfg_wl_tx_power,
|
||||
.coex_set_wl_rx_gain = rtw8822b_coex_cfg_wl_rx_gain,
|
||||
};
|
||||
|
||||
/* Shared-Antenna Coex Table */
|
||||
static const struct coex_table_para table_sant_8822b[] = {
|
||||
{0xffffffff, 0xffffffff}, /* case-0 */
|
||||
{0x55555555, 0x55555555},
|
||||
{0x66555555, 0x66555555},
|
||||
{0xaaaaaaaa, 0xaaaaaaaa},
|
||||
{0x5a5a5a5a, 0x5a5a5a5a},
|
||||
{0xfafafafa, 0xfafafafa}, /* case-5 */
|
||||
{0x6a5a6a5a, 0xaaaaaaaa},
|
||||
{0x6a5a56aa, 0x6a5a56aa},
|
||||
{0x6a5a5a5a, 0x6a5a5a5a},
|
||||
{0x66555555, 0x5a5a5a5a},
|
||||
{0x66555555, 0x6a5a5a5a}, /* case-10 */
|
||||
{0x66555555, 0xfafafafa},
|
||||
{0x66555555, 0x6a5a5aaa},
|
||||
{0x66555555, 0x5aaa5aaa},
|
||||
{0x66555555, 0xaaaa5aaa},
|
||||
{0x66555555, 0xaaaaaaaa}, /* case-15 */
|
||||
{0xffff55ff, 0xfafafafa},
|
||||
{0xffff55ff, 0x6afa5afa},
|
||||
{0xaaffffaa, 0xfafafafa},
|
||||
{0xaa5555aa, 0x5a5a5a5a},
|
||||
{0xaa5555aa, 0x6a5a5a5a}, /* case-20 */
|
||||
{0xaa5555aa, 0xaaaaaaaa},
|
||||
{0xffffffff, 0x5a5a5a5a},
|
||||
{0xffffffff, 0x6a5a5a5a},
|
||||
{0xffffffff, 0x55555555},
|
||||
{0xffffffff, 0x6a5a5aaa}, /* case-25 */
|
||||
{0x55555555, 0x5a5a5a5a},
|
||||
{0x55555555, 0xaaaaaaaa},
|
||||
{0x55555555, 0x6a5a6a5a},
|
||||
{0x66556655, 0x66556655}
|
||||
};
|
||||
|
||||
/* Non-Shared-Antenna Coex Table */
|
||||
static const struct coex_table_para table_nsant_8822b[] = {
|
||||
{0xffffffff, 0xffffffff}, /* case-100 */
|
||||
{0x55555555, 0x55555555},
|
||||
{0x66555555, 0x66555555},
|
||||
{0xaaaaaaaa, 0xaaaaaaaa},
|
||||
{0x5a5a5a5a, 0x5a5a5a5a},
|
||||
{0xfafafafa, 0xfafafafa}, /* case-105 */
|
||||
{0x5afa5afa, 0x5afa5afa},
|
||||
{0x55555555, 0xfafafafa},
|
||||
{0x66555555, 0xfafafafa},
|
||||
{0x66555555, 0x5a5a5a5a},
|
||||
{0x66555555, 0x6a5a5a5a}, /* case-110 */
|
||||
{0x66555555, 0xaaaaaaaa},
|
||||
{0xffff55ff, 0xfafafafa},
|
||||
{0xffff55ff, 0x5afa5afa},
|
||||
{0xffff55ff, 0xaaaaaaaa},
|
||||
{0xaaffffaa, 0xfafafafa}, /* case-115 */
|
||||
{0xaaffffaa, 0x5afa5afa},
|
||||
{0xaaffffaa, 0xaaaaaaaa},
|
||||
{0xffffffff, 0xfafafafa},
|
||||
{0xffffffff, 0x5afa5afa},
|
||||
{0xffffffff, 0xaaaaaaaa}, /* case-120 */
|
||||
{0x55ff55ff, 0x5afa5afa},
|
||||
{0x55ff55ff, 0xaaaaaaaa},
|
||||
{0x55ff55ff, 0x55ff55ff}
|
||||
};
|
||||
|
||||
/* Shared-Antenna TDMA */
|
||||
static const struct coex_tdma_para tdma_sant_8822b[] = {
|
||||
{ {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */
|
||||
{ {0x61, 0x45, 0x03, 0x11, 0x11} },
|
||||
{ {0x61, 0x3a, 0x03, 0x11, 0x11} },
|
||||
{ {0x61, 0x30, 0x03, 0x11, 0x11} },
|
||||
{ {0x61, 0x20, 0x03, 0x11, 0x11} },
|
||||
{ {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-5 */
|
||||
{ {0x61, 0x45, 0x03, 0x11, 0x10} },
|
||||
{ {0x61, 0x3a, 0x03, 0x11, 0x10} },
|
||||
{ {0x61, 0x30, 0x03, 0x11, 0x10} },
|
||||
{ {0x61, 0x20, 0x03, 0x11, 0x10} },
|
||||
{ {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */
|
||||
{ {0x61, 0x08, 0x03, 0x11, 0x14} },
|
||||
{ {0x61, 0x08, 0x03, 0x10, 0x14} },
|
||||
{ {0x51, 0x08, 0x03, 0x10, 0x54} },
|
||||
{ {0x51, 0x08, 0x03, 0x10, 0x55} },
|
||||
{ {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */
|
||||
{ {0x51, 0x45, 0x03, 0x10, 0x10} },
|
||||
{ {0x51, 0x3a, 0x03, 0x10, 0x50} },
|
||||
{ {0x51, 0x30, 0x03, 0x10, 0x50} },
|
||||
{ {0x51, 0x20, 0x03, 0x10, 0x50} },
|
||||
{ {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */
|
||||
{ {0x51, 0x4a, 0x03, 0x10, 0x50} },
|
||||
{ {0x51, 0x0c, 0x03, 0x10, 0x54} },
|
||||
{ {0x55, 0x08, 0x03, 0x10, 0x54} },
|
||||
{ {0x65, 0x10, 0x03, 0x11, 0x11} },
|
||||
{ {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */
|
||||
{ {0x51, 0x08, 0x03, 0x10, 0x50} }
|
||||
};
|
||||
|
||||
/* Non-Shared-Antenna TDMA */
|
||||
static const struct coex_tdma_para tdma_nsant_8822b[] = {
|
||||
{ {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-100 */
|
||||
{ {0x61, 0x45, 0x03, 0x11, 0x11} },
|
||||
{ {0x61, 0x3a, 0x03, 0x11, 0x11} },
|
||||
{ {0x61, 0x30, 0x03, 0x11, 0x11} },
|
||||
{ {0x61, 0x20, 0x03, 0x11, 0x11} },
|
||||
{ {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */
|
||||
{ {0x61, 0x45, 0x03, 0x11, 0x10} },
|
||||
{ {0x61, 0x3a, 0x03, 0x11, 0x10} },
|
||||
{ {0x61, 0x30, 0x03, 0x11, 0x10} },
|
||||
{ {0x61, 0x20, 0x03, 0x11, 0x10} },
|
||||
{ {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */
|
||||
{ {0x61, 0x08, 0x03, 0x11, 0x14} },
|
||||
{ {0x61, 0x08, 0x03, 0x10, 0x14} },
|
||||
{ {0x51, 0x08, 0x03, 0x10, 0x54} },
|
||||
{ {0x51, 0x08, 0x03, 0x10, 0x55} },
|
||||
{ {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */
|
||||
{ {0x51, 0x45, 0x03, 0x10, 0x50} },
|
||||
{ {0x51, 0x3a, 0x03, 0x10, 0x50} },
|
||||
{ {0x51, 0x30, 0x03, 0x10, 0x50} },
|
||||
{ {0x51, 0x20, 0x03, 0x10, 0x50} },
|
||||
{ {0x51, 0x10, 0x03, 0x10, 0x50} } /* case-120 */
|
||||
};
|
||||
|
||||
/* rssi in percentage % (dbm = % - 100) */
|
||||
static const u8 wl_rssi_step_8822b[] = {60, 50, 44, 30};
|
||||
static const u8 bt_rssi_step_8822b[] = {30, 30, 30, 30};
|
||||
static const struct coex_5g_afh_map afh_5g_8822b[] = { {0, 0, 0} };
|
||||
|
||||
/* wl_tx_dec_power, bt_tx_dec_power, wl_rx_gain, bt_rx_lna_constrain */
|
||||
static const struct coex_rf_para rf_para_tx_8822b[] = {
|
||||
{0, 0, false, 7}, /* for normal */
|
||||
{0, 16, false, 7}, /* for WL-CPT */
|
||||
{4, 0, true, 1},
|
||||
{3, 6, true, 1},
|
||||
{2, 9, true, 1},
|
||||
{1, 13, true, 1}
|
||||
};
|
||||
|
||||
static const struct coex_rf_para rf_para_rx_8822b[] = {
|
||||
{0, 0, false, 7}, /* for normal */
|
||||
{0, 16, false, 7}, /* for WL-CPT */
|
||||
{4, 0, true, 1},
|
||||
{3, 6, true, 1},
|
||||
{2, 9, true, 1},
|
||||
{1, 13, true, 1}
|
||||
};
|
||||
|
||||
static_assert(ARRAY_SIZE(rf_para_tx_8822b) == ARRAY_SIZE(rf_para_rx_8822b));
|
||||
|
||||
struct rtw_chip_info rtw8822b_hw_spec = {
|
||||
.ops = &rtw8822b_ops,
|
||||
.id = RTW_CHIP_TYPE_8822B,
|
||||
@ -1588,6 +1986,32 @@ struct rtw_chip_info rtw8822b_hw_spec = {
|
||||
.rf_tbl = {&rtw8822b_rf_a_tbl, &rtw8822b_rf_b_tbl},
|
||||
.rfe_defs = rtw8822b_rfe_defs,
|
||||
.rfe_defs_size = ARRAY_SIZE(rtw8822b_rfe_defs),
|
||||
|
||||
.coex_para_ver = 0x19062706,
|
||||
.bt_desired_ver = 0x6,
|
||||
.scbd_support = true,
|
||||
.new_scbd10_def = false,
|
||||
.pstdma_type = COEX_PSTDMA_FORCE_LPSOFF,
|
||||
.bt_rssi_type = COEX_BTRSSI_RATIO,
|
||||
.ant_isolation = 15,
|
||||
.rssi_tolerance = 2,
|
||||
.wl_rssi_step = wl_rssi_step_8822b,
|
||||
.bt_rssi_step = bt_rssi_step_8822b,
|
||||
.table_sant_num = ARRAY_SIZE(table_sant_8822b),
|
||||
.table_sant = table_sant_8822b,
|
||||
.table_nsant_num = ARRAY_SIZE(table_nsant_8822b),
|
||||
.table_nsant = table_nsant_8822b,
|
||||
.tdma_sant_num = ARRAY_SIZE(tdma_sant_8822b),
|
||||
.tdma_sant = tdma_sant_8822b,
|
||||
.tdma_nsant_num = ARRAY_SIZE(tdma_nsant_8822b),
|
||||
.tdma_nsant = tdma_nsant_8822b,
|
||||
.wl_rf_para_num = ARRAY_SIZE(rf_para_tx_8822b),
|
||||
.wl_rf_para_tx = rf_para_tx_8822b,
|
||||
.wl_rf_para_rx = rf_para_rx_8822b,
|
||||
.bt_afh_span_bw20 = 0x24,
|
||||
.bt_afh_span_bw40 = 0x36,
|
||||
.afh_5g_num = ARRAY_SIZE(afh_5g_8822b),
|
||||
.afh_5g = afh_5g_8822b,
|
||||
};
|
||||
EXPORT_SYMBOL(rtw8822b_hw_spec);
|
||||
|
||||
|
||||
@ -3,6 +3,7 @@
|
||||
*/
|
||||
|
||||
#include "main.h"
|
||||
#include "coex.h"
|
||||
#include "fw.h"
|
||||
#include "tx.h"
|
||||
#include "rx.h"
|
||||
@ -31,6 +32,7 @@ static int rtw8822c_read_efuse(struct rtw_dev *rtwdev, u8 *log_map)
|
||||
map = (struct rtw8822c_efuse *)log_map;
|
||||
|
||||
efuse->rfe_option = map->rfe_option;
|
||||
efuse->rf_board_option = map->rf_board_option;
|
||||
efuse->crystal_cap = map->xtal_k;
|
||||
efuse->channel_plan = map->channel_plan;
|
||||
efuse->country_code[0] = map->country_code[0];
|
||||
@ -1041,12 +1043,6 @@ static void rtw8822c_phy_set_param(struct rtw_dev *rtwdev)
|
||||
dm_info->cck_gi_l_bnd = ((cck_gi_l_bnd_msb << 4) | (cck_gi_l_bnd_lsb));
|
||||
|
||||
rtw8822c_rf_init(rtwdev);
|
||||
/* wifi path controller */
|
||||
rtw_write32_mask(rtwdev, 0x70, 0xff000000, 0x0e);
|
||||
rtw_write32_mask(rtwdev, 0x1704, 0xffffffff, 0x7700);
|
||||
rtw_write32_mask(rtwdev, 0x1700, 0xffffffff, 0xc00f0038);
|
||||
rtw_write32_mask(rtwdev, 0x6c0, 0xffffffff, 0xaaaaaaaa);
|
||||
rtw_write32_mask(rtwdev, 0x6c4, 0xffffffff, 0xaaaaaaaa);
|
||||
}
|
||||
|
||||
#define WLAN_TXQ_RPT_EN 0x1F
|
||||
@ -1817,6 +1813,7 @@ static void rtw8822c_false_alarm_statistics(struct rtw_dev *rtwdev)
|
||||
struct rtw_dm_info *dm_info = &rtwdev->dm_info;
|
||||
u32 cck_enable;
|
||||
u32 cck_fa_cnt;
|
||||
u32 crc32_cnt;
|
||||
u32 ofdm_fa_cnt;
|
||||
u32 ofdm_fa_cnt1, ofdm_fa_cnt2, ofdm_fa_cnt3, ofdm_fa_cnt4, ofdm_fa_cnt5;
|
||||
u16 parity_fail, rate_illegal, crc8_fail, mcs_fail, sb_search_fail,
|
||||
@ -1848,6 +1845,19 @@ static void rtw8822c_false_alarm_statistics(struct rtw_dev *rtwdev)
|
||||
dm_info->total_fa_cnt = ofdm_fa_cnt;
|
||||
dm_info->total_fa_cnt += cck_enable ? cck_fa_cnt : 0;
|
||||
|
||||
crc32_cnt = rtw_read32(rtwdev, 0x2c04);
|
||||
dm_info->cck_ok_cnt = crc32_cnt & 0xffff;
|
||||
dm_info->cck_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
|
||||
crc32_cnt = rtw_read32(rtwdev, 0x2c14);
|
||||
dm_info->ofdm_ok_cnt = crc32_cnt & 0xffff;
|
||||
dm_info->ofdm_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
|
||||
crc32_cnt = rtw_read32(rtwdev, 0x2c10);
|
||||
dm_info->ht_ok_cnt = crc32_cnt & 0xffff;
|
||||
dm_info->ht_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
|
||||
crc32_cnt = rtw_read32(rtwdev, 0x2c0c);
|
||||
dm_info->vht_ok_cnt = crc32_cnt & 0xffff;
|
||||
dm_info->vht_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
|
||||
|
||||
rtw_write32_mask(rtwdev, REG_CCANRX, BIT_CCK_FA_RST, 0);
|
||||
rtw_write32_mask(rtwdev, REG_CCANRX, BIT_CCK_FA_RST, 2);
|
||||
rtw_write32_mask(rtwdev, REG_CCANRX, BIT_OFDM_FA_RST, 0);
|
||||
@ -1864,6 +1874,161 @@ static void rtw8822c_do_iqk(struct rtw_dev *rtwdev)
|
||||
{
|
||||
}
|
||||
|
||||
/* for coex */
|
||||
static void rtw8822c_coex_cfg_init(struct rtw_dev *rtwdev)
|
||||
{
|
||||
/* enable TBTT nterrupt */
|
||||
rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION);
|
||||
|
||||
/* BT report packet sample rate */
|
||||
/* 0x790[5:0]=0x5 */
|
||||
rtw_write8_set(rtwdev, REG_BT_TDMA_TIME, 0x05);
|
||||
|
||||
/* enable BT counter statistics */
|
||||
rtw_write8(rtwdev, REG_BT_STAT_CTRL, 0x1);
|
||||
|
||||
/* enable PTA (3-wire function form BT side) */
|
||||
rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_PTA_EN);
|
||||
rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_AOD_GPIO3);
|
||||
|
||||
/* enable PTA (tx/rx signal form WiFi side) */
|
||||
rtw_write8_set(rtwdev, REG_QUEUE_CTRL, BIT_PTA_WL_TX_EN);
|
||||
/* wl tx signal to PTA not case EDCCA */
|
||||
rtw_write8_clr(rtwdev, REG_QUEUE_CTRL, BIT_PTA_EDCCA_EN);
|
||||
/* GNT_BT=1 while select both */
|
||||
rtw_write8_set(rtwdev, REG_BT_COEX_V2, BIT_GNT_BT_POLARITY);
|
||||
/* BT_CCA = ~GNT_WL_BB, (not or GNT_BT_BB, LTE_Rx */
|
||||
rtw_write8_clr(rtwdev, REG_DUMMY_PAGE4_V1, BIT_BTCCA_CTRL);
|
||||
|
||||
/* to avoid RF parameter error */
|
||||
rtw_write_rf(rtwdev, RF_PATH_B, 0x1, 0xfffff, 0x40000);
|
||||
}
|
||||
|
||||
static void rtw8822c_coex_cfg_gnt_fix(struct rtw_dev *rtwdev)
|
||||
{
|
||||
struct rtw_coex *coex = &rtwdev->coex;
|
||||
struct rtw_coex_stat *coex_stat = &coex->stat;
|
||||
struct rtw_efuse *efuse = &rtwdev->efuse;
|
||||
u32 rf_0x1;
|
||||
|
||||
if (coex_stat->gnt_workaround_state == coex_stat->wl_coex_mode)
|
||||
return;
|
||||
|
||||
coex_stat->gnt_workaround_state = coex_stat->wl_coex_mode;
|
||||
|
||||
if ((coex_stat->kt_ver == 0 && coex->under_5g) || coex->freerun)
|
||||
rf_0x1 = 0x40021;
|
||||
else
|
||||
rf_0x1 = 0x40000;
|
||||
|
||||
/* BT at S1 for Shared-Ant */
|
||||
if (efuse->share_ant)
|
||||
rf_0x1 |= BIT(13);
|
||||
|
||||
rtw_write_rf(rtwdev, RF_PATH_B, 0x1, 0xfffff, rf_0x1);
|
||||
|
||||
/* WL-S0 2G RF TRX cannot be masked by GNT_BT
|
||||
* enable "WLS0 BB chage RF mode if GNT_BT = 1" for shared-antenna type
|
||||
* disable:0x1860[3] = 1, enable:0x1860[3] = 0
|
||||
*
|
||||
* enable "DAC off if GNT_WL = 0" for non-shared-antenna
|
||||
* disable 0x1c30[22] = 0,
|
||||
* enable: 0x1c30[22] = 1, 0x1c38[12] = 0, 0x1c38[28] = 1
|
||||
*
|
||||
* disable WL-S1 BB chage RF mode if GNT_BT
|
||||
* since RF TRx mask can do it
|
||||
*/
|
||||
rtw_write8_mask(rtwdev, 0x1c32, BIT(6), 1);
|
||||
rtw_write8_mask(rtwdev, 0x1c39, BIT(4), 0);
|
||||
rtw_write8_mask(rtwdev, 0x1c3b, BIT(4), 1);
|
||||
rtw_write8_mask(rtwdev, 0x4160, BIT(3), 1);
|
||||
|
||||
/* disable WL-S0 BB chage RF mode if wifi is at 5G,
|
||||
* or antenna path is separated
|
||||
*/
|
||||
if (coex_stat->wl_coex_mode == COEX_WLINK_5G ||
|
||||
coex->under_5g || !efuse->share_ant) {
|
||||
if (coex_stat->kt_ver >= 3) {
|
||||
rtw_write8_mask(rtwdev, 0x1860, BIT(3), 0);
|
||||
rtw_write8_mask(rtwdev, 0x1ca7, BIT(3), 1);
|
||||
} else {
|
||||
rtw_write8_mask(rtwdev, 0x1860, BIT(3), 1);
|
||||
}
|
||||
} else {
|
||||
/* shared-antenna */
|
||||
rtw_write8_mask(rtwdev, 0x1860, BIT(3), 0);
|
||||
if (coex_stat->kt_ver >= 3)
|
||||
rtw_write8_mask(rtwdev, 0x1ca7, BIT(3), 0);
|
||||
}
|
||||
}
|
||||
|
||||
static void rtw8822c_coex_cfg_gnt_debug(struct rtw_dev *rtwdev)
|
||||
{
|
||||
rtw_write8_mask(rtwdev, 0x66, BIT(4), 0);
|
||||
rtw_write8_mask(rtwdev, 0x67, BIT(0), 0);
|
||||
rtw_write8_mask(rtwdev, 0x42, BIT(3), 0);
|
||||
rtw_write8_mask(rtwdev, 0x65, BIT(7), 0);
|
||||
rtw_write8_mask(rtwdev, 0x73, BIT(3), 0);
|
||||
}
|
||||
|
||||
static void rtw8822c_coex_cfg_rfe_type(struct rtw_dev *rtwdev)
|
||||
{
|
||||
struct rtw_coex *coex = &rtwdev->coex;
|
||||
struct rtw_coex_rfe *coex_rfe = &coex->rfe;
|
||||
struct rtw_efuse *efuse = &rtwdev->efuse;
|
||||
|
||||
coex_rfe->rfe_module_type = rtwdev->efuse.rfe_option;
|
||||
coex_rfe->ant_switch_polarity = 0;
|
||||
coex_rfe->ant_switch_exist = false;
|
||||
coex_rfe->ant_switch_with_bt = false;
|
||||
coex_rfe->ant_switch_diversity = false;
|
||||
|
||||
if (efuse->share_ant)
|
||||
coex_rfe->wlg_at_btg = true;
|
||||
else
|
||||
coex_rfe->wlg_at_btg = false;
|
||||
|
||||
/* disable LTE coex in wifi side */
|
||||
rtw_coex_write_indirect_reg(rtwdev, 0x38, BIT_LTE_COEX_EN, 0x0);
|
||||
rtw_coex_write_indirect_reg(rtwdev, 0xa0, MASKLWORD, 0xffff);
|
||||
rtw_coex_write_indirect_reg(rtwdev, 0xa4, MASKLWORD, 0xffff);
|
||||
}
|
||||
|
||||
static void rtw8822c_coex_cfg_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr)
|
||||
{
|
||||
struct rtw_coex *coex = &rtwdev->coex;
|
||||
struct rtw_coex_dm *coex_dm = &coex->dm;
|
||||
|
||||
if (wl_pwr == coex_dm->cur_wl_pwr_lvl)
|
||||
return;
|
||||
|
||||
coex_dm->cur_wl_pwr_lvl = wl_pwr;
|
||||
}
|
||||
|
||||
static void rtw8822c_coex_cfg_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain)
|
||||
{
|
||||
struct rtw_coex *coex = &rtwdev->coex;
|
||||
struct rtw_coex_dm *coex_dm = &coex->dm;
|
||||
|
||||
if (low_gain == coex_dm->cur_wl_rx_low_gain_en)
|
||||
return;
|
||||
|
||||
coex_dm->cur_wl_rx_low_gain_en = low_gain;
|
||||
|
||||
if (coex_dm->cur_wl_rx_low_gain_en) {
|
||||
/* set Rx filter corner RCK offset */
|
||||
rtw_write_rf(rtwdev, RF_PATH_A, 0xde, 0xfffff, 0x22);
|
||||
rtw_write_rf(rtwdev, RF_PATH_A, 0x1d, 0xfffff, 0x36);
|
||||
rtw_write_rf(rtwdev, RF_PATH_B, 0xde, 0xfffff, 0x22);
|
||||
rtw_write_rf(rtwdev, RF_PATH_B, 0x1d, 0xfffff, 0x36);
|
||||
} else {
|
||||
/* set Rx filter corner RCK offset */
|
||||
rtw_write_rf(rtwdev, RF_PATH_A, 0xde, 0xfffff, 0x20);
|
||||
rtw_write_rf(rtwdev, RF_PATH_A, 0x1d, 0xfffff, 0x0);
|
||||
rtw_write_rf(rtwdev, RF_PATH_B, 0x1d, 0xfffff, 0x0);
|
||||
}
|
||||
}
|
||||
|
||||
static struct rtw_pwr_seq_cmd trans_carddis_to_cardemu_8822c[] = {
|
||||
{0x0086,
|
||||
RTW_PWR_CUT_ALL_MSK,
|
||||
@ -2232,8 +2397,160 @@ static struct rtw_chip_ops rtw8822c_ops = {
|
||||
.cfg_ldo25 = rtw8822c_cfg_ldo25,
|
||||
.false_alarm_statistics = rtw8822c_false_alarm_statistics,
|
||||
.do_iqk = rtw8822c_do_iqk,
|
||||
|
||||
.coex_set_init = rtw8822c_coex_cfg_init,
|
||||
.coex_set_ant_switch = NULL,
|
||||
.coex_set_gnt_fix = rtw8822c_coex_cfg_gnt_fix,
|
||||
.coex_set_gnt_debug = rtw8822c_coex_cfg_gnt_debug,
|
||||
.coex_set_rfe_type = rtw8822c_coex_cfg_rfe_type,
|
||||
.coex_set_wl_tx_power = rtw8822c_coex_cfg_wl_tx_power,
|
||||
.coex_set_wl_rx_gain = rtw8822c_coex_cfg_wl_rx_gain,
|
||||
};
|
||||
|
||||
/* Shared-Antenna Coex Table */
|
||||
static const struct coex_table_para table_sant_8822c[] = {
|
||||
{0xffffffff, 0xffffffff}, /* case-0 */
|
||||
{0x55555555, 0x55555555},
|
||||
{0x66555555, 0x66555555},
|
||||
{0xaaaaaaaa, 0xaaaaaaaa},
|
||||
{0x5a5a5a5a, 0x5a5a5a5a},
|
||||
{0xfafafafa, 0xfafafafa}, /* case-5 */
|
||||
{0x6a5a6a5a, 0xaaaaaaaa},
|
||||
{0x6a5a56aa, 0x6a5a56aa},
|
||||
{0x6a5a5a5a, 0x6a5a5a5a},
|
||||
{0x66555555, 0x5a5a5a5a},
|
||||
{0x66555555, 0x6a5a5a5a}, /* case-10 */
|
||||
{0x66555555, 0xfafafafa},
|
||||
{0x66555555, 0x6a5a5aaa},
|
||||
{0x66555555, 0x5aaa5aaa},
|
||||
{0x66555555, 0xaaaa5aaa},
|
||||
{0x66555555, 0xaaaaaaaa}, /* case-15 */
|
||||
{0xffff55ff, 0xfafafafa},
|
||||
{0xffff55ff, 0x6afa5afa},
|
||||
{0xaaffffaa, 0xfafafafa},
|
||||
{0xaa5555aa, 0x5a5a5a5a},
|
||||
{0xaa5555aa, 0x6a5a5a5a}, /* case-20 */
|
||||
{0xaa5555aa, 0xaaaaaaaa},
|
||||
{0xffffffff, 0x5a5a5a5a},
|
||||
{0xffffffff, 0x6a5a5a5a},
|
||||
{0xffffffff, 0x55555555},
|
||||
{0xffffffff, 0x6a5a5aaa}, /* case-25 */
|
||||
{0x55555555, 0x5a5a5a5a},
|
||||
{0x55555555, 0xaaaaaaaa},
|
||||
{0x55555555, 0x6a5a6a5a},
|
||||
{0x66556655, 0x66556655}
|
||||
};
|
||||
|
||||
/* Non-Shared-Antenna Coex Table */
|
||||
static const struct coex_table_para table_nsant_8822c[] = {
|
||||
{0xffffffff, 0xffffffff}, /* case-100 */
|
||||
{0x55555555, 0x55555555},
|
||||
{0x66555555, 0x66555555},
|
||||
{0xaaaaaaaa, 0xaaaaaaaa},
|
||||
{0x5a5a5a5a, 0x5a5a5a5a},
|
||||
{0xfafafafa, 0xfafafafa}, /* case-105 */
|
||||
{0x5afa5afa, 0x5afa5afa},
|
||||
{0x55555555, 0xfafafafa},
|
||||
{0x66555555, 0xfafafafa},
|
||||
{0x66555555, 0x5a5a5a5a},
|
||||
{0x66555555, 0x6a5a5a5a}, /* case-110 */
|
||||
{0x66555555, 0xaaaaaaaa},
|
||||
{0xffff55ff, 0xfafafafa},
|
||||
{0xffff55ff, 0x5afa5afa},
|
||||
{0xffff55ff, 0xaaaaaaaa},
|
||||
{0xaaffffaa, 0xfafafafa}, /* case-115 */
|
||||
{0xaaffffaa, 0x5afa5afa},
|
||||
{0xaaffffaa, 0xaaaaaaaa},
|
||||
{0xffffffff, 0xfafafafa},
|
||||
{0xffffffff, 0x5afa5afa},
|
||||
{0xffffffff, 0xaaaaaaaa},/* case-120 */
|
||||
{0x55ff55ff, 0x5afa5afa},
|
||||
{0x55ff55ff, 0xaaaaaaaa},
|
||||
{0x55ff55ff, 0x55ff55ff}
|
||||
};
|
||||
|
||||
/* Shared-Antenna TDMA */
|
||||
static const struct coex_tdma_para tdma_sant_8822c[] = {
|
||||
{ {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */
|
||||
{ {0x61, 0x45, 0x03, 0x11, 0x11} },
|
||||
{ {0x61, 0x3a, 0x03, 0x11, 0x11} },
|
||||
{ {0x61, 0x30, 0x03, 0x11, 0x11} },
|
||||
{ {0x61, 0x20, 0x03, 0x11, 0x11} },
|
||||
{ {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-5 */
|
||||
{ {0x61, 0x45, 0x03, 0x11, 0x10} },
|
||||
{ {0x61, 0x3a, 0x03, 0x11, 0x10} },
|
||||
{ {0x61, 0x30, 0x03, 0x11, 0x10} },
|
||||
{ {0x61, 0x20, 0x03, 0x11, 0x10} },
|
||||
{ {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */
|
||||
{ {0x61, 0x08, 0x03, 0x11, 0x14} },
|
||||
{ {0x61, 0x08, 0x03, 0x10, 0x14} },
|
||||
{ {0x51, 0x08, 0x03, 0x10, 0x54} },
|
||||
{ {0x51, 0x08, 0x03, 0x10, 0x55} },
|
||||
{ {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */
|
||||
{ {0x51, 0x45, 0x03, 0x10, 0x10} },
|
||||
{ {0x51, 0x3a, 0x03, 0x10, 0x50} },
|
||||
{ {0x51, 0x30, 0x03, 0x10, 0x50} },
|
||||
{ {0x51, 0x20, 0x03, 0x10, 0x50} },
|
||||
{ {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */
|
||||
{ {0x51, 0x4a, 0x03, 0x10, 0x50} },
|
||||
{ {0x51, 0x0c, 0x03, 0x10, 0x54} },
|
||||
{ {0x55, 0x08, 0x03, 0x10, 0x54} },
|
||||
{ {0x65, 0x10, 0x03, 0x11, 0x11} },
|
||||
{ {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */
|
||||
{ {0x51, 0x08, 0x03, 0x10, 0x50} }
|
||||
};
|
||||
|
||||
/* Non-Shared-Antenna TDMA */
|
||||
static const struct coex_tdma_para tdma_nsant_8822c[] = {
|
||||
{ {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-100 */
|
||||
{ {0x61, 0x45, 0x03, 0x11, 0x11} },
|
||||
{ {0x61, 0x3a, 0x03, 0x11, 0x11} },
|
||||
{ {0x61, 0x30, 0x03, 0x11, 0x11} },
|
||||
{ {0x61, 0x20, 0x03, 0x11, 0x11} },
|
||||
{ {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */
|
||||
{ {0x61, 0x45, 0x03, 0x11, 0x10} },
|
||||
{ {0x61, 0x3a, 0x03, 0x11, 0x10} },
|
||||
{ {0x61, 0x30, 0x03, 0x11, 0x10} },
|
||||
{ {0x61, 0x20, 0x03, 0x11, 0x10} },
|
||||
{ {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */
|
||||
{ {0x61, 0x08, 0x03, 0x11, 0x14} },
|
||||
{ {0x61, 0x08, 0x03, 0x10, 0x14} },
|
||||
{ {0x51, 0x08, 0x03, 0x10, 0x54} },
|
||||
{ {0x51, 0x08, 0x03, 0x10, 0x55} },
|
||||
{ {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */
|
||||
{ {0x51, 0x45, 0x03, 0x10, 0x50} },
|
||||
{ {0x51, 0x3a, 0x03, 0x10, 0x50} },
|
||||
{ {0x51, 0x30, 0x03, 0x10, 0x50} },
|
||||
{ {0x51, 0x20, 0x03, 0x10, 0x50} },
|
||||
{ {0x51, 0x10, 0x03, 0x10, 0x50} } /* case-120 */
|
||||
};
|
||||
|
||||
/* rssi in percentage % (dbm = % - 100) */
|
||||
static const u8 wl_rssi_step_8822c[] = {60, 50, 44, 30};
|
||||
static const u8 bt_rssi_step_8822c[] = {8, 15, 20, 25};
|
||||
static const struct coex_5g_afh_map afh_5g_8822c[] = { {0, 0, 0} };
|
||||
|
||||
/* wl_tx_dec_power, bt_tx_dec_power, wl_rx_gain, bt_rx_lna_constrain */
|
||||
static const struct coex_rf_para rf_para_tx_8822c[] = {
|
||||
{0, 0, false, 7}, /* for normal */
|
||||
{0, 16, false, 7}, /* for WL-CPT */
|
||||
{8, 17, true, 4},
|
||||
{7, 18, true, 4},
|
||||
{6, 19, true, 4},
|
||||
{5, 20, true, 4}
|
||||
};
|
||||
|
||||
static const struct coex_rf_para rf_para_rx_8822c[] = {
|
||||
{0, 0, false, 7}, /* for normal */
|
||||
{0, 16, false, 7}, /* for WL-CPT */
|
||||
{3, 24, true, 5},
|
||||
{2, 26, true, 5},
|
||||
{1, 27, true, 5},
|
||||
{0, 28, true, 5}
|
||||
};
|
||||
|
||||
static_assert(ARRAY_SIZE(rf_para_tx_8822c) == ARRAY_SIZE(rf_para_rx_8822c));
|
||||
|
||||
struct rtw_chip_info rtw8822c_hw_spec = {
|
||||
.ops = &rtw8822c_ops,
|
||||
.id = RTW_CHIP_TYPE_8822C,
|
||||
@ -2272,6 +2589,32 @@ struct rtw_chip_info rtw8822c_hw_spec = {
|
||||
.rf_tbl = {&rtw8822c_rf_a_tbl, &rtw8822c_rf_b_tbl},
|
||||
.rfe_defs = rtw8822c_rfe_defs,
|
||||
.rfe_defs_size = ARRAY_SIZE(rtw8822c_rfe_defs),
|
||||
|
||||
.coex_para_ver = 0x19062706,
|
||||
.bt_desired_ver = 0x6,
|
||||
.scbd_support = true,
|
||||
.new_scbd10_def = true,
|
||||
.pstdma_type = COEX_PSTDMA_FORCE_LPSOFF,
|
||||
.bt_rssi_type = COEX_BTRSSI_DBM,
|
||||
.ant_isolation = 15,
|
||||
.rssi_tolerance = 2,
|
||||
.wl_rssi_step = wl_rssi_step_8822c,
|
||||
.bt_rssi_step = bt_rssi_step_8822c,
|
||||
.table_sant_num = ARRAY_SIZE(table_sant_8822c),
|
||||
.table_sant = table_sant_8822c,
|
||||
.table_nsant_num = ARRAY_SIZE(table_nsant_8822c),
|
||||
.table_nsant = table_nsant_8822c,
|
||||
.tdma_sant_num = ARRAY_SIZE(tdma_sant_8822c),
|
||||
.tdma_sant = tdma_sant_8822c,
|
||||
.tdma_nsant_num = ARRAY_SIZE(tdma_nsant_8822c),
|
||||
.tdma_nsant = tdma_nsant_8822c,
|
||||
.wl_rf_para_num = ARRAY_SIZE(rf_para_tx_8822c),
|
||||
.wl_rf_para_tx = rf_para_tx_8822c,
|
||||
.wl_rf_para_rx = rf_para_rx_8822c,
|
||||
.bt_afh_span_bw20 = 0x24,
|
||||
.bt_afh_span_bw40 = 0x36,
|
||||
.afh_5g_num = ARRAY_SIZE(afh_5g_8822c),
|
||||
.afh_5g = afh_5g_8822c,
|
||||
};
|
||||
EXPORT_SYMBOL(rtw8822c_hw_spec);
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user