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iwlwifi: TX update chicken bits
This instructs FH to increment the retry count of a packet when it is brought from the memory to TX-FIFO to save transactions during aggregation flow. Signed-off-by: Tomas Winkler <tomas.winkler@intel.com> Signed-off-by: Reinette Chatre <reinette.chatre@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -695,6 +695,7 @@ static int iwl4965_alive_notify(struct iwl_priv *priv)
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unsigned long flags;
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int ret;
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int i, chan;
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u32 reg_val;
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spin_lock_irqsave(&priv->lock, flags);
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@ -724,6 +725,11 @@ static int iwl4965_alive_notify(struct iwl_priv *priv)
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FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
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FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
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/* Update FH chicken bits */
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reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG);
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iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG,
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reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
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/* Disable chain mode for all queues */
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iwl_write_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, 0);
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@ -703,6 +703,7 @@ static int iwl5000_alive_notify(struct iwl_priv *priv)
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unsigned long flags;
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int ret;
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int i, chan;
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u32 reg_val;
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spin_lock_irqsave(&priv->lock, flags);
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@ -732,6 +733,11 @@ static int iwl5000_alive_notify(struct iwl_priv *priv)
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FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
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FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
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/* Update FH chicken bits */
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reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG);
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iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG,
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reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
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iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL,
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IWL50_SCD_QUEUECHAIN_SEL_ALL(priv->hw_params.max_txq_num));
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iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0);
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@ -396,6 +396,11 @@
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#define FH_SRVC_CHNL_SRAM_ADDR_REG(_chnl) \
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(FH_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4)
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#define FH_TX_CHICKEN_BITS_REG (FH_MEM_LOWER_BOUND + 0xE98)
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/* Instruct FH to increment the retry count of a packet when
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* it is brought from the memory to TX-FIFO
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*/
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#define FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN (0x00000002)
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/**
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* struct iwl_rb_status - reseve buffer status
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