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caif: Add CAIF HSI Link layer driver
This patch introduces the CAIF HSI Protocol Driver for the CAIF Link Layer. This driver implements a platform driver to accommodate for a platform specific HSI devices. A general platform driver is not possible as there are no HSI side Kernel API defined. Signed-off-by: Sjur Brændeland <sjur.brandeland@stericsson.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Dmitry.Tarnyagin
David S. Miller
parent
a198c142aa
commit
40d69043fc
@ -38,3 +38,12 @@ config CAIF_SHM
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default n
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---help---
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The CAIF shared memory protocol driver for the STE UX5500 platform.
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config CAIF_HSI
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tristate "CAIF HSI transport driver"
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depends on CAIF
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default n
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---help---
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The caif low level driver for CAIF over HSI.
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Be aware that if you enable this then you also need to
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enable a low-level HSI driver.
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@ -10,3 +10,6 @@ obj-$(CONFIG_CAIF_SPI_SLAVE) += cfspi_slave.o
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# Shared memory
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caif_shm-objs := caif_shmcore.o caif_shm_u5500.o
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obj-$(CONFIG_CAIF_SHM) += caif_shm.o
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# HSI interface
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obj-$(CONFIG_CAIF_HSI) += caif_hsi.o
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1220
drivers/net/caif/caif_hsi.c
Normal file
1220
drivers/net/caif/caif_hsi.c
Normal file
File diff suppressed because it is too large
Load Diff
145
include/net/caif/caif_hsi.h
Normal file
145
include/net/caif/caif_hsi.h
Normal file
@ -0,0 +1,145 @@
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/*
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* Copyright (C) ST-Ericsson AB 2010
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* Contact: Sjur Brendeland / sjur.brandeland@stericsson.com
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* Author: Daniel Martensson / daniel.martensson@stericsson.com
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* Dmitry.Tarnyagin / dmitry.tarnyagin@stericsson.com
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* License terms: GNU General Public License (GPL) version 2
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*/
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#ifndef CAIF_HSI_H_
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#define CAIF_HSI_H_
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#include <net/caif/caif_layer.h>
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#include <net/caif/caif_device.h>
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#include <linux/atomic.h>
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/*
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* Maximum number of CAIF frames that can reside in the same HSI frame.
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*/
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#define CFHSI_MAX_PKTS 15
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/*
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* Maximum number of bytes used for the frame that can be embedded in the
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* HSI descriptor.
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*/
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#define CFHSI_MAX_EMB_FRM_SZ 96
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/*
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* Decides if HSI buffers should be prefilled with 0xFF pattern for easier
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* debugging. Both TX and RX buffers will be filled before the transfer.
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*/
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#define CFHSI_DBG_PREFILL 0
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/* Structure describing a HSI packet descriptor. */
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#pragma pack(1) /* Byte alignment. */
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struct cfhsi_desc {
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u8 header;
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u8 offset;
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u16 cffrm_len[CFHSI_MAX_PKTS];
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u8 emb_frm[CFHSI_MAX_EMB_FRM_SZ];
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};
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#pragma pack() /* Default alignment. */
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/* Size of the complete HSI packet descriptor. */
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#define CFHSI_DESC_SZ (sizeof(struct cfhsi_desc))
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/*
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* Size of the complete HSI packet descriptor excluding the optional embedded
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* CAIF frame.
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*/
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#define CFHSI_DESC_SHORT_SZ (CFHSI_DESC_SZ - CFHSI_MAX_EMB_FRM_SZ)
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/*
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* Maximum bytes transferred in one transfer.
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*/
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/* TODO: 4096 is temporary... */
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#define CFHSI_MAX_PAYLOAD_SZ (CFHSI_MAX_PKTS * 4096)
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/* Size of the complete HSI TX buffer. */
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#define CFHSI_BUF_SZ_TX (CFHSI_DESC_SZ + CFHSI_MAX_PAYLOAD_SZ)
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/* Size of the complete HSI RX buffer. */
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#define CFHSI_BUF_SZ_RX ((2 * CFHSI_DESC_SZ) + CFHSI_MAX_PAYLOAD_SZ)
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/* Bitmasks for the HSI descriptor. */
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#define CFHSI_PIGGY_DESC (0x01 << 7)
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#define CFHSI_TX_STATE_IDLE 0
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#define CFHSI_TX_STATE_XFER 1
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#define CFHSI_RX_STATE_DESC 0
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#define CFHSI_RX_STATE_PAYLOAD 1
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/* Bitmasks for power management. */
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#define CFHSI_WAKE_UP 0
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#define CFHSI_WAKE_UP_ACK 1
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#define CFHSI_WAKE_DOWN_ACK 2
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#define CFHSI_AWAKE 3
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#define CFHSI_PENDING_RX 4
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#define CFHSI_SHUTDOWN 6
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#define CFHSI_FLUSH_FIFO 7
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#ifndef CFHSI_INACTIVITY_TOUT
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#define CFHSI_INACTIVITY_TOUT (1 * HZ)
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#endif /* CFHSI_INACTIVITY_TOUT */
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#ifndef CFHSI_WAKEUP_TOUT
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#define CFHSI_WAKEUP_TOUT (3 * HZ)
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#endif /* CFHSI_WAKEUP_TOUT */
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/* Structure implemented by the CAIF HSI driver. */
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struct cfhsi_drv {
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void (*tx_done_cb) (struct cfhsi_drv *drv);
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void (*rx_done_cb) (struct cfhsi_drv *drv);
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void (*wake_up_cb) (struct cfhsi_drv *drv);
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void (*wake_down_cb) (struct cfhsi_drv *drv);
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};
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/* Structure implemented by HSI device. */
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struct cfhsi_dev {
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int (*cfhsi_up) (struct cfhsi_dev *dev);
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int (*cfhsi_down) (struct cfhsi_dev *dev);
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int (*cfhsi_tx) (u8 *ptr, int len, struct cfhsi_dev *dev);
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int (*cfhsi_rx) (u8 *ptr, int len, struct cfhsi_dev *dev);
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int (*cfhsi_wake_up) (struct cfhsi_dev *dev);
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int (*cfhsi_wake_down) (struct cfhsi_dev *dev);
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int (*cfhsi_fifo_occupancy)(struct cfhsi_dev *dev, size_t *occupancy);
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int (*cfhsi_rx_cancel)(struct cfhsi_dev *dev);
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struct cfhsi_drv *drv;
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};
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/* Structure implemented by CAIF HSI drivers. */
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struct cfhsi {
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struct caif_dev_common cfdev;
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struct net_device *ndev;
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struct platform_device *pdev;
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struct sk_buff_head qhead;
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struct cfhsi_drv drv;
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struct cfhsi_dev *dev;
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int tx_state;
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int rx_state;
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int rx_len;
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u8 *rx_ptr;
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u8 *tx_buf;
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u8 *rx_buf;
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spinlock_t lock;
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int flow_off_sent;
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u32 q_low_mark;
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u32 q_high_mark;
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struct list_head list;
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struct work_struct wake_up_work;
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struct work_struct wake_down_work;
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struct work_struct rx_done_work;
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struct work_struct tx_done_work;
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struct workqueue_struct *wq;
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wait_queue_head_t wake_up_wait;
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wait_queue_head_t wake_down_wait;
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wait_queue_head_t flush_fifo_wait;
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struct timer_list timer;
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unsigned long bits;
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};
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extern struct platform_driver cfhsi_driver;
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#endif /* CAIF_HSI_H_ */
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