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MIPS: Octeon: fix CN6640 hang on XAUI init

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Some CN66XX series Octeon II chips seem to hang if a reset is issued on
XAUI initialization. Avoid the hang by disabling the reset.

Tested on SNIC10E.

Signed-off-by: Stijn Tintel <stijn@linux-ipv6.be>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
This commit is contained in:
Stijn Tintel 2022-04-03 05:59:49 +03:00 committed by Thomas Bogendoerfer
parent 4107fa700f
commit 407710a3b5
1 changed files with 3 additions and 2 deletions
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5
arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c
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@ -156,8 +156,9 @@ int __cvmx_helper_xaui_enable(int interface)
xauiCtl.u64 = cvmx_read_csr(CVMX_PCSXX_CONTROL1_REG(interface)); xauiCtl.u64 = cvmx_read_csr(CVMX_PCSXX_CONTROL1_REG(interface));
xauiCtl.s.lo_pwr = 0; xauiCtl.s.lo_pwr = 0;
/* Issuing a reset here seems to hang some CN68XX chips. */ /* Issuing a reset here seems to hang some CN66XX/CN68XX chips. */
if (!OCTEON_IS_MODEL(OCTEON_CN68XX_PASS1_X) && if (!OCTEON_IS_MODEL(OCTEON_CN66XX) &&
!OCTEON_IS_MODEL(OCTEON_CN68XX_PASS1_X) &&
!OCTEON_IS_MODEL(OCTEON_CN68XX_PASS2_X)) !OCTEON_IS_MODEL(OCTEON_CN68XX_PASS2_X))
xauiCtl.s.reset = 1; xauiCtl.s.reset = 1;