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ARM: dts: Add pcie controller node for Samsung EXYNOS5440 SoC
Exynos5440 has two PCIe controllers which can be used as root complex for PCIe interface. Signed-off-by: Jingoo Han <jg1.han@samsung.com> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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3f06d15782
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406a9324b4
@ -216,4 +216,42 @@
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clock-names = "rtc";
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status = "disabled";
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};
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pcie@290000 {
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compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
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reg = <0x290000 0x1000
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0x270000 0x1000
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0x271000 0x40>;
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interrupts = <0 20 0>, <0 21 0>, <0 22 0>;
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clocks = <&clock 28>, <&clock 27>;
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clock-names = "pcie", "pcie_bus";
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges = <0x00000800 0 0x40000000 0x40000000 0 0x00001000 /* configuration space */
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0x81000000 0 0 0x40001000 0 0x00010000 /* downstream I/O */
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0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0x0 0 &gic 53>;
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};
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pcie@2a0000 {
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compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
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reg = <0x2a0000 0x1000
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0x272000 0x1000
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0x271040 0x40>;
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interrupts = <0 23 0>, <0 24 0>, <0 25 0>;
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clocks = <&clock 29>, <&clock 27>;
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clock-names = "pcie", "pcie_bus";
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges = <0x00000800 0 0x60000000 0x60000000 0 0x00001000 /* configuration space */
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0x81000000 0 0 0x60001000 0 0x00010000 /* downstream I/O */
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0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0x0 0 &gic 56>;
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};
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};
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