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bnx2: Reorganize timeout constants.
Move all related timeout constants to the same location. BNX2 prefix is also added to make them more consistent. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Benjamin Li <benli@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -1656,7 +1656,7 @@ bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port)
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* exchanging base pages plus 3 next pages and
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* normally completes in about 120 msec.
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*/
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bp->current_interval = SERDES_AN_TIMEOUT;
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bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
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bp->serdes_an_pending = 1;
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mod_timer(&bp->timer, jiffies + bp->current_interval);
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} else {
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@ -2278,7 +2278,7 @@ bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int ack, int silent)
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return 0;
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/* wait for an acknowledgement. */
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for (i = 0; i < (FW_ACK_TIME_OUT_MS / 10); i++) {
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for (i = 0; i < (BNX2_FW_ACK_TIME_OUT_MS / 10); i++) {
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msleep(10);
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val = bnx2_shmem_rd(bp, BNX2_FW_MB);
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@ -5705,7 +5705,7 @@ bnx2_5708_serdes_timer(struct bnx2 *bp)
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bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
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if (bmcr & BMCR_ANENABLE) {
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bnx2_enable_forced_2g5(bp);
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bp->current_interval = SERDES_FORCED_TIMEOUT;
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bp->current_interval = BNX2_SERDES_FORCED_TIMEOUT;
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} else {
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bnx2_disable_forced_2g5(bp);
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bp->serdes_an_pending = 2;
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@ -6522,7 +6522,7 @@ bnx2_nway_reset(struct net_device *dev)
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spin_lock_bh(&bp->phy_lock);
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bp->current_interval = SERDES_AN_TIMEOUT;
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bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
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bp->serdes_an_pending = 1;
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mod_timer(&bp->timer, jiffies + bp->current_interval);
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}
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@ -6679,8 +6679,6 @@ struct bnx2_napi {
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struct bnx2_tx_ring_info tx_ring;
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};
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#define BNX2_TIMER_INTERVAL HZ
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struct bnx2 {
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/* Fields used in the tx and intr/napi performance paths are grouped */
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/* together in the beginning of the structure. */
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@ -6728,7 +6726,11 @@ struct bnx2 {
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/* End of fields used in the performance code paths. */
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int current_interval;
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unsigned int current_interval;
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#define BNX2_TIMER_INTERVAL HZ
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#define BNX2_SERDES_AN_TIMEOUT (HZ / 3)
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#define BNX2_SERDES_FORCED_TIMEOUT (HZ / 10)
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struct timer_list timer;
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struct work_struct reset_task;
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@ -6860,8 +6862,6 @@ struct bnx2 {
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#define PHY_LOOPBACK 2
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u8 serdes_an_pending;
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#define SERDES_AN_TIMEOUT (HZ / 3)
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#define SERDES_FORCED_TIMEOUT (HZ / 10)
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u8 mac_addr[8];
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@ -6959,14 +6959,14 @@ struct fw_info {
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/* This value (in milliseconds) determines the frequency of the driver
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* issuing the PULSE message code. The firmware monitors this periodic
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* pulse to determine when to switch to an OS-absent mode. */
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#define DRV_PULSE_PERIOD_MS 250
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#define BNX2_DRV_PULSE_PERIOD_MS 250
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/* This value (in milliseconds) determines how long the driver should
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* wait for an acknowledgement from the firmware before timing out. Once
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* the firmware has timed out, the driver will assume there is no firmware
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* running and there won't be any firmware-driver synchronization during a
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* driver reset. */
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#define FW_ACK_TIME_OUT_MS 1000
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#define BNX2_FW_ACK_TIME_OUT_MS 1000
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#define BNX2_DRV_RESET_SIGNATURE 0x00000000
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