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MIPS: generic: Convert SEAD-3 to a generic board
Convert the MIPS SEAD-3 board support to be a generic board, supported by generic kernels. Because the SEAD-3 boot protocol was defined long ago and we don't want to force a switch to the UHI protocol, SEAD-3 is added as a legacy board which is detected by reading the REVISION register. This may technically not be a valid memory read & future work will include attempting to handle that gracefully. In practice since SEAD-3 is the only legacy board supported by the generic kernel so far the read will only happen on SEAD-3 boards, and even once Malta is converted the same REVISION register exists there too. Other boards such as Boston, Ci20 & Ci40 will use the UHI boot protocol & thus not run any of the legacy board detect functions. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14354/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Paul Burton
Ralf Baechle
parent
eed0eabd12
commit
3f5f0a4475
@ -19,7 +19,6 @@ platforms += lasat
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platforms += loongson32
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platforms += loongson64
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platforms += mti-malta
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platforms += mti-sead3
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platforms += netlogic
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platforms += paravirt
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platforms += pic32
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@ -546,41 +546,6 @@ config MACH_PIC32
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Microchip PIC32 is a family of general-purpose 32 bit MIPS core
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microcontrollers.
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config MIPS_SEAD3
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bool "MIPS SEAD3 board"
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select BOOT_ELF32
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select BOOT_RAW
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select BUILTIN_DTB
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select CEVT_R4K
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select CSRC_R4K
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select CLKSRC_MIPS_GIC
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select COMMON_CLK
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select CPU_MIPSR2_IRQ_VI
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select CPU_MIPSR2_IRQ_EI
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select DMA_NONCOHERENT
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select IRQ_MIPS_CPU
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select MIPS_GIC
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select LIBFDT
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select MIPS_MSC
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select SYS_HAS_CPU_MIPS32_R1
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select SYS_HAS_CPU_MIPS32_R2
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select SYS_HAS_CPU_MIPS32_R6
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select SYS_HAS_CPU_MIPS64_R1
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select SYS_SUPPORTS_32BIT_KERNEL
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select SYS_SUPPORTS_64BIT_KERNEL
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select SYS_SUPPORTS_BIG_ENDIAN
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select SYS_SUPPORTS_LITTLE_ENDIAN
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select SYS_SUPPORTS_SMARTMIPS
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select SYS_SUPPORTS_MICROMIPS
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select SYS_SUPPORTS_MIPS16
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select SYS_SUPPORTS_RELOCATABLE
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select USB_EHCI_BIG_ENDIAN_DESC
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select USB_EHCI_BIG_ENDIAN_MMIO
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select USE_OF
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help
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This enables support for the MIPS Technologies SEAD3 evaluation
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board.
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config NEC_MARKEINS
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bool "NEC EMMA2RH Mark-eins board"
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select SOC_EMMA2RH
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@ -2976,7 +2941,7 @@ endchoice
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choice
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prompt "Kernel command line type" if !CMDLINE_OVERRIDE
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default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
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!MIPS_MALTA && !MIPS_SEAD3 && \
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!MIPS_MALTA && \
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!CAVIUM_OCTEON_SOC
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default MIPS_CMDLINE_FROM_BOOTLOADER
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@ -488,3 +488,16 @@ $(generic_defconfigs):
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# Prevent generic merge_config rules attempting to merge single fragments
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#
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$(generic_config_dir)/%.config: ;
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#
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# Legacy defconfig compatibility - these targets used to be real defconfigs but
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# now that the boards have been converted to use the generic kernel they are
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# wrappers around the generic rules above.
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#
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.PHONY: sead3_defconfig
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sead3_defconfig:
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$(Q)$(MAKE) 32r2el_defconfig BOARDS=sead-3
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.PHONY: sead3micro_defconfig
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sead3micro_defconfig:
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$(Q)$(MAKE) micro32r2el_defconfig BOARDS=sead-3
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@ -1,5 +1,5 @@
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dtb-$(CONFIG_MIPS_MALTA) += malta.dtb
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dtb-$(CONFIG_MIPS_SEAD3) += sead3.dtb
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dtb-$(CONFIG_LEGACY_BOARD_SEAD3) += sead3.dtb
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obj-y += $(patsubst %.dtb, %.dtb.o, $(dtb-y))
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@ -10,6 +10,7 @@
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "mti,sead-3";
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model = "MIPS SEAD-3";
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interrupt-parent = <&gic>;
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chosen {
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32
arch/mips/configs/generic/board-sead-3.config
Normal file
32
arch/mips/configs/generic/board-sead-3.config
Normal file
@ -0,0 +1,32 @@
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CONFIG_LEGACY_BOARD_SEAD3=y
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CONFIG_AUXDISPLAY=y
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CONFIG_IMG_ASCII_LCD=y
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CONFIG_NEW_LEDS=y
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CONFIG_LEDS_CLASS=y
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CONFIG_LEDS_SYSCON=y
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CONFIG_MMC=y
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CONFIG_MMC_SPI=y
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CONFIG_MTD=y
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CONFIG_MTD_BLOCK=y
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CONFIG_MTD_CFI=y
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CONFIG_MTD_CFI_INTELEXT=y
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CONFIG_MTD_OF_PARTS=y
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CONFIG_MTD_PHYSMAP=y
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CONFIG_MTD_PHYSMAP_OF=y
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CONFIG_MTD_UBI=y
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CONFIG_MTD_UBI_GLUEBI=y
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CONFIG_NETDEVICES=y
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CONFIG_SMSC911X=y
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CONFIG_SMSC_PHY=y
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CONFIG_SERIAL_8250=y
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CONFIG_SERIAL_8250_CONSOLE=y
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CONFIG_SERIAL_OF_PLATFORM=y
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CONFIG_USB=y
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CONFIG_USB_EHCI_HCD=y
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@ -1,129 +0,0 @@
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CONFIG_MIPS_SEAD3=y
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CONFIG_CPU_LITTLE_ENDIAN=y
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CONFIG_CPU_MIPS32_R2=y
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CONFIG_HZ_100=y
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CONFIG_SYSVIPC=y
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CONFIG_POSIX_MQUEUE=y
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CONFIG_NO_HZ=y
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CONFIG_HIGH_RES_TIMERS=y
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CONFIG_IKCONFIG=y
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CONFIG_IKCONFIG_PROC=y
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CONFIG_LOG_BUF_SHIFT=15
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CONFIG_EMBEDDED=y
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CONFIG_SLAB=y
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CONFIG_PROFILING=y
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CONFIG_OPROFILE=y
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CONFIG_MODULES=y
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# CONFIG_BLK_DEV_BSG is not set
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CONFIG_CMDLINE_BOOL=y
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CONFIG_CMDLINE="earlycon"
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# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
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CONFIG_NET=y
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CONFIG_PACKET=y
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CONFIG_UNIX=y
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CONFIG_INET=y
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CONFIG_IP_PNP=y
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CONFIG_IP_PNP_DHCP=y
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CONFIG_IP_PNP_BOOTP=y
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# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
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# CONFIG_INET_XFRM_MODE_TUNNEL is not set
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# CONFIG_INET_XFRM_MODE_BEET is not set
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# CONFIG_INET_LRO is not set
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# CONFIG_INET_DIAG is not set
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# CONFIG_IPV6 is not set
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# CONFIG_WIRELESS is not set
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CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
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CONFIG_DEVTMPFS=y
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CONFIG_MTD=y
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CONFIG_MTD_BLOCK=y
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CONFIG_MTD_CFI=y
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CONFIG_MTD_CFI_INTELEXT=y
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CONFIG_MTD_PHYSMAP=y
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CONFIG_MTD_UBI=y
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CONFIG_MTD_UBI_GLUEBI=y
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CONFIG_OF=y
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CONFIG_BLK_DEV_LOOP=y
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CONFIG_BLK_DEV_CRYPTOLOOP=m
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CONFIG_SCSI=y
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# CONFIG_SCSI_PROC_FS is not set
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CONFIG_BLK_DEV_SD=y
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CONFIG_CHR_DEV_SG=y
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# CONFIG_SCSI_LOWLEVEL is not set
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CONFIG_NETDEVICES=y
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CONFIG_SMSC911X=y
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# CONFIG_NET_VENDOR_WIZNET is not set
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CONFIG_MARVELL_PHY=y
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CONFIG_DAVICOM_PHY=y
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CONFIG_QSEMI_PHY=y
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CONFIG_LXT_PHY=y
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CONFIG_CICADA_PHY=y
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CONFIG_VITESSE_PHY=y
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CONFIG_SMSC_PHY=y
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CONFIG_BROADCOM_PHY=y
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CONFIG_ICPLUS_PHY=y
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# CONFIG_WLAN is not set
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# CONFIG_INPUT_MOUSEDEV is not set
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# CONFIG_INPUT_KEYBOARD is not set
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# CONFIG_INPUT_MOUSE is not set
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# CONFIG_SERIO is not set
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# CONFIG_CONSOLE_TRANSLATIONS is not set
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CONFIG_VT_HW_CONSOLE_BINDING=y
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CONFIG_LEGACY_PTY_COUNT=32
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CONFIG_SERIAL_8250=y
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CONFIG_SERIAL_8250_CONSOLE=y
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CONFIG_SERIAL_8250_NR_UARTS=2
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CONFIG_SERIAL_8250_RUNTIME_UARTS=2
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CONFIG_SERIAL_OF_PLATFORM=y
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# CONFIG_HW_RANDOM is not set
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CONFIG_I2C=y
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# CONFIG_I2C_COMPAT is not set
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CONFIG_I2C_CHARDEV=y
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# CONFIG_I2C_HELPER_AUTO is not set
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CONFIG_SPI=y
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CONFIG_POWER_RESET=y
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CONFIG_POWER_RESET_RESTART=y
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CONFIG_POWER_RESET_SYSCON=y
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CONFIG_SENSORS_ADT7475=y
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CONFIG_BACKLIGHT_LCD_SUPPORT=y
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CONFIG_LCD_CLASS_DEVICE=y
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CONFIG_BACKLIGHT_CLASS_DEVICE=y
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# CONFIG_VGA_CONSOLE is not set
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CONFIG_USB=y
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CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
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CONFIG_USB_EHCI_HCD=y
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CONFIG_USB_EHCI_ROOT_HUB_TT=y
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CONFIG_USB_STORAGE=y
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CONFIG_MMC=y
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CONFIG_MMC_DEBUG=y
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CONFIG_MMC_SPI=y
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CONFIG_NEW_LEDS=y
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CONFIG_LEDS_CLASS=y
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CONFIG_LEDS_SYSCON=y
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CONFIG_LEDS_TRIGGERS=y
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CONFIG_LEDS_TRIGGER_HEARTBEAT=y
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CONFIG_RTC_CLASS=y
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CONFIG_RTC_DRV_M41T80=y
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CONFIG_EXT3_FS=y
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# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
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CONFIG_XFS_FS=y
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CONFIG_XFS_QUOTA=y
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CONFIG_XFS_POSIX_ACL=y
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CONFIG_QUOTA=y
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# CONFIG_PRINT_QUOTA_WARNING is not set
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CONFIG_MSDOS_FS=m
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CONFIG_VFAT_FS=m
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CONFIG_TMPFS=y
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CONFIG_JFFS2_FS=y
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CONFIG_NFS_FS=y
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CONFIG_ROOT_NFS=y
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CONFIG_NLS_CODEPAGE_437=y
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CONFIG_NLS_ASCII=y
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CONFIG_NLS_ISO8859_1=y
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CONFIG_NLS_ISO8859_15=y
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CONFIG_NLS_UTF8=y
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# CONFIG_FTRACE is not set
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CONFIG_CRYPTO_CBC=y
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CONFIG_CRYPTO_ECB=y
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CONFIG_CRYPTO_ARC4=y
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# CONFIG_CRYPTO_ANSI_CPRNG is not set
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# CONFIG_CRYPTO_HW is not set
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@ -1,122 +0,0 @@
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CONFIG_MIPS_SEAD3=y
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CONFIG_CPU_LITTLE_ENDIAN=y
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CONFIG_CPU_MIPS32_R2=y
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CONFIG_CPU_MICROMIPS=y
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CONFIG_HZ_100=y
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CONFIG_SYSVIPC=y
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CONFIG_POSIX_MQUEUE=y
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CONFIG_NO_HZ=y
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CONFIG_HIGH_RES_TIMERS=y
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CONFIG_IKCONFIG=y
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CONFIG_IKCONFIG_PROC=y
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CONFIG_LOG_BUF_SHIFT=15
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CONFIG_EMBEDDED=y
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CONFIG_SLAB=y
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CONFIG_PROFILING=y
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CONFIG_OPROFILE=y
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CONFIG_MODULES=y
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# CONFIG_BLK_DEV_BSG is not set
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# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
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CONFIG_NET=y
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CONFIG_PACKET=y
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CONFIG_UNIX=y
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CONFIG_INET=y
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CONFIG_IP_PNP=y
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CONFIG_IP_PNP_DHCP=y
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CONFIG_IP_PNP_BOOTP=y
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# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
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# CONFIG_INET_XFRM_MODE_TUNNEL is not set
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# CONFIG_INET_XFRM_MODE_BEET is not set
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# CONFIG_INET_LRO is not set
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# CONFIG_INET_DIAG is not set
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# CONFIG_IPV6 is not set
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# CONFIG_WIRELESS is not set
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CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
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CONFIG_DEVTMPFS=y
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CONFIG_MTD=y
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CONFIG_MTD_BLOCK=y
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CONFIG_MTD_CFI=y
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CONFIG_MTD_CFI_INTELEXT=y
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CONFIG_MTD_PHYSMAP=y
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CONFIG_MTD_UBI=y
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CONFIG_MTD_UBI_GLUEBI=y
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CONFIG_BLK_DEV_LOOP=y
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CONFIG_BLK_DEV_CRYPTOLOOP=m
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CONFIG_SCSI=y
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# CONFIG_SCSI_PROC_FS is not set
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CONFIG_BLK_DEV_SD=y
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CONFIG_CHR_DEV_SG=y
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# CONFIG_SCSI_LOWLEVEL is not set
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CONFIG_NETDEVICES=y
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CONFIG_SMSC911X=y
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# CONFIG_NET_VENDOR_WIZNET is not set
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CONFIG_MARVELL_PHY=y
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CONFIG_DAVICOM_PHY=y
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CONFIG_QSEMI_PHY=y
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CONFIG_LXT_PHY=y
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CONFIG_CICADA_PHY=y
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CONFIG_VITESSE_PHY=y
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CONFIG_SMSC_PHY=y
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CONFIG_BROADCOM_PHY=y
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CONFIG_ICPLUS_PHY=y
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# CONFIG_WLAN is not set
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# CONFIG_INPUT_MOUSEDEV is not set
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# CONFIG_INPUT_KEYBOARD is not set
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# CONFIG_INPUT_MOUSE is not set
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# CONFIG_SERIO is not set
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# CONFIG_CONSOLE_TRANSLATIONS is not set
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CONFIG_VT_HW_CONSOLE_BINDING=y
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CONFIG_LEGACY_PTY_COUNT=32
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CONFIG_SERIAL_8250=y
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CONFIG_SERIAL_8250_CONSOLE=y
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CONFIG_SERIAL_8250_NR_UARTS=2
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CONFIG_SERIAL_8250_RUNTIME_UARTS=2
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# CONFIG_HW_RANDOM is not set
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CONFIG_I2C=y
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# CONFIG_I2C_COMPAT is not set
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CONFIG_I2C_CHARDEV=y
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# CONFIG_I2C_HELPER_AUTO is not set
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CONFIG_SPI=y
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CONFIG_SENSORS_ADT7475=y
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CONFIG_BACKLIGHT_LCD_SUPPORT=y
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CONFIG_LCD_CLASS_DEVICE=y
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CONFIG_BACKLIGHT_CLASS_DEVICE=y
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# CONFIG_VGA_CONSOLE is not set
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CONFIG_USB=y
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CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
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CONFIG_USB_EHCI_HCD=y
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CONFIG_USB_EHCI_ROOT_HUB_TT=y
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CONFIG_USB_STORAGE=y
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CONFIG_MMC=y
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CONFIG_MMC_DEBUG=y
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CONFIG_MMC_SPI=y
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CONFIG_NEW_LEDS=y
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CONFIG_LEDS_CLASS=y
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CONFIG_LEDS_TRIGGERS=y
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CONFIG_LEDS_TRIGGER_HEARTBEAT=y
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CONFIG_RTC_CLASS=y
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CONFIG_RTC_DRV_M41T80=y
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CONFIG_EXT3_FS=y
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# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
|
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CONFIG_XFS_FS=y
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CONFIG_XFS_QUOTA=y
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CONFIG_XFS_POSIX_ACL=y
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CONFIG_QUOTA=y
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# CONFIG_PRINT_QUOTA_WARNING is not set
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CONFIG_MSDOS_FS=m
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CONFIG_VFAT_FS=m
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CONFIG_TMPFS=y
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CONFIG_JFFS2_FS=y
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CONFIG_NFS_FS=y
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CONFIG_ROOT_NFS=y
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CONFIG_NLS_CODEPAGE_437=y
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CONFIG_NLS_ASCII=y
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CONFIG_NLS_ISO8859_1=y
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CONFIG_NLS_ISO8859_15=y
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CONFIG_NLS_UTF8=y
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# CONFIG_FTRACE is not set
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CONFIG_CRYPTO_CBC=y
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CONFIG_CRYPTO_ECB=y
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CONFIG_CRYPTO_ARC4=y
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# CONFIG_CRYPTO_ANSI_CPRNG is not set
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# CONFIG_CRYPTO_HW is not set
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@ -9,4 +9,11 @@ config LEGACY_BOARDS
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kernel is booted without being provided with an FDT via the UHI
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boot protocol.
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config LEGACY_BOARD_SEAD3
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bool "Support MIPS SEAD-3 boards"
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select LEGACY_BOARDS
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help
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Enable this to include support for booting on MIPS SEAD-3 FPGA-based
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development boards, which boot using a legacy boot protocol.
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endif
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@ -11,3 +11,5 @@
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obj-y += init.o
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obj-y += irq.o
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obj-y += proc.o
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obj-$(CONFIG_LEGACY_BOARD_SEAD3) += board-sead3.o
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@ -4,11 +4,11 @@
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*
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* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
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*/
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|
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#define pr_fmt(fmt) "sead3-dtshim: " fmt
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#define pr_fmt(fmt) "sead3: " fmt
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#include <linux/errno.h>
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#include <linux/libfdt.h>
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@ -16,13 +16,49 @@
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#include <asm/fw/fw.h>
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#include <asm/io.h>
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#include <asm/machine.h>
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#define SEAD_CONFIG CKSEG1ADDR(0x1b100110)
|
||||
#define SEAD_CONFIG_GIC_PRESENT BIT(1)
|
||||
|
||||
static unsigned char fdt_buf[16 << 10] __initdata;
|
||||
#define MIPS_REVISION CKSEG1ADDR(0x1fc00010)
|
||||
#define MIPS_REVISION_MACHINE (0xf << 4)
|
||||
#define MIPS_REVISION_MACHINE_SEAD3 (0x4 << 4)
|
||||
|
||||
static int append_memory(void *fdt)
|
||||
static __init bool sead3_detect(void)
|
||||
{
|
||||
uint32_t rev;
|
||||
|
||||
rev = __raw_readl((void *)MIPS_REVISION);
|
||||
return (rev & MIPS_REVISION_MACHINE) == MIPS_REVISION_MACHINE_SEAD3;
|
||||
}
|
||||
|
||||
static __init int append_cmdline(void *fdt)
|
||||
{
|
||||
int err, chosen_off;
|
||||
|
||||
/* find or add chosen node */
|
||||
chosen_off = fdt_path_offset(fdt, "/chosen");
|
||||
if (chosen_off == -FDT_ERR_NOTFOUND)
|
||||
chosen_off = fdt_path_offset(fdt, "/chosen@0");
|
||||
if (chosen_off == -FDT_ERR_NOTFOUND)
|
||||
chosen_off = fdt_add_subnode(fdt, 0, "chosen");
|
||||
if (chosen_off < 0) {
|
||||
pr_err("Unable to find or add DT chosen node: %d\n",
|
||||
chosen_off);
|
||||
return chosen_off;
|
||||
}
|
||||
|
||||
err = fdt_setprop_string(fdt, chosen_off, "bootargs", fw_getcmdline());
|
||||
if (err) {
|
||||
pr_err("Unable to set bootargs property: %d\n", err);
|
||||
return err;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static __init int append_memory(void *fdt)
|
||||
{
|
||||
unsigned long phys_memsize, memsize;
|
||||
__be32 mem_array[2];
|
||||
@ -89,7 +125,7 @@ static int append_memory(void *fdt)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int remove_gic(void *fdt)
|
||||
static __init int remove_gic(void *fdt)
|
||||
{
|
||||
const unsigned int cpu_ehci_int = 2;
|
||||
const unsigned int cpu_uart_int = 4;
|
||||
@ -163,7 +199,7 @@ static int remove_gic(void *fdt)
|
||||
return err;
|
||||
}
|
||||
|
||||
ehci_off = fdt_node_offset_by_compatible(fdt, -1, "mti,sead3-ehci");
|
||||
ehci_off = fdt_node_offset_by_compatible(fdt, -1, "generic-ehci");
|
||||
if (ehci_off < 0) {
|
||||
pr_err("unable to find EHCI DT node: %d\n", ehci_off);
|
||||
return ehci_off;
|
||||
@ -178,7 +214,7 @@ static int remove_gic(void *fdt)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int serial_config(void *fdt)
|
||||
static __init int serial_config(void *fdt)
|
||||
{
|
||||
const char *yamontty, *mode_var;
|
||||
char mode_var_name[9], path[18], parity;
|
||||
@ -257,21 +293,28 @@ static int serial_config(void *fdt)
|
||||
return 0;
|
||||
}
|
||||
|
||||
void __init *sead3_dt_shim(void *fdt)
|
||||
static __init const void *sead3_fixup_fdt(const void *fdt,
|
||||
const void *match_data)
|
||||
{
|
||||
static unsigned char fdt_buf[16 << 10] __initdata;
|
||||
int err;
|
||||
|
||||
if (fdt_check_header(fdt))
|
||||
panic("Corrupt DT");
|
||||
|
||||
/* if this isn't SEAD3, leave the DT alone */
|
||||
if (fdt_node_check_compatible(fdt, 0, "mti,sead-3"))
|
||||
return fdt;
|
||||
/* if this isn't SEAD3, something went wrong */
|
||||
BUG_ON(fdt_node_check_compatible(fdt, 0, "mti,sead-3"));
|
||||
|
||||
fw_init_cmdline();
|
||||
|
||||
err = fdt_open_into(fdt, fdt_buf, sizeof(fdt_buf));
|
||||
if (err)
|
||||
panic("Unable to open FDT: %d", err);
|
||||
|
||||
err = append_cmdline(fdt_buf);
|
||||
if (err)
|
||||
panic("Unable to patch FDT: %d", err);
|
||||
|
||||
err = append_memory(fdt_buf);
|
||||
if (err)
|
||||
panic("Unable to patch FDT: %d", err);
|
||||
@ -290,3 +333,44 @@ void __init *sead3_dt_shim(void *fdt)
|
||||
|
||||
return fdt_buf;
|
||||
}
|
||||
|
||||
static __init unsigned int sead3_measure_hpt_freq(void)
|
||||
{
|
||||
void __iomem *status_reg = (void __iomem *)0xbf000410;
|
||||
unsigned int freq, orig, tick = 0;
|
||||
unsigned long flags;
|
||||
|
||||
local_irq_save(flags);
|
||||
|
||||
orig = readl(status_reg) & 0x2; /* get original sample */
|
||||
/* wait for transition */
|
||||
while ((readl(status_reg) & 0x2) == orig)
|
||||
;
|
||||
orig = orig ^ 0x2; /* flip the bit */
|
||||
|
||||
write_c0_count(0);
|
||||
|
||||
/* wait 1 second (the sampling clock transitions every 10ms) */
|
||||
while (tick < 100) {
|
||||
/* wait for transition */
|
||||
while ((readl(status_reg) & 0x2) == orig)
|
||||
;
|
||||
orig = orig ^ 0x2; /* flip the bit */
|
||||
tick++;
|
||||
}
|
||||
|
||||
freq = read_c0_count();
|
||||
|
||||
local_irq_restore(flags);
|
||||
|
||||
return freq;
|
||||
}
|
||||
|
||||
extern char __dtb_sead3_begin[];
|
||||
|
||||
MIPS_MACHINE(sead3) = {
|
||||
.fdt = __dtb_sead3_begin,
|
||||
.detect = sead3_detect,
|
||||
.fixup_fdt = sead3_fixup_fdt,
|
||||
.measure_hpt_freq = sead3_measure_hpt_freq,
|
||||
};
|
||||
@ -1,72 +0,0 @@
|
||||
/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 2003, 2004 Chris Dearman
|
||||
* Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
|
||||
*/
|
||||
#ifndef __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H
|
||||
#define __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H
|
||||
|
||||
|
||||
/*
|
||||
* CPU feature overrides for MIPS boards
|
||||
*/
|
||||
#ifdef CONFIG_CPU_MIPS32
|
||||
#define cpu_has_tlb 1
|
||||
#define cpu_has_4kex 1
|
||||
#define cpu_has_4k_cache 1
|
||||
/* #define cpu_has_fpu ? */
|
||||
/* #define cpu_has_32fpr ? */
|
||||
#define cpu_has_counter 1
|
||||
/* #define cpu_has_watch ? */
|
||||
#define cpu_has_divec 1
|
||||
#define cpu_has_vce 0
|
||||
/* #define cpu_has_cache_cdex_p ? */
|
||||
/* #define cpu_has_cache_cdex_s ? */
|
||||
/* #define cpu_has_prefetch ? */
|
||||
#define cpu_has_mcheck 1
|
||||
/* #define cpu_has_ejtag ? */
|
||||
#ifdef CONFIG_CPU_MICROMIPS
|
||||
#define cpu_has_llsc 0
|
||||
#else
|
||||
#define cpu_has_llsc 1
|
||||
#endif
|
||||
/* #define cpu_has_vtag_icache ? */
|
||||
/* #define cpu_has_dc_aliases ? */
|
||||
/* #define cpu_has_ic_fills_f_dc ? */
|
||||
#define cpu_has_nofpuex 0
|
||||
/* #define cpu_has_64bits ? */
|
||||
/* #define cpu_has_64bit_zero_reg ? */
|
||||
/* #define cpu_has_inclusive_pcaches ? */
|
||||
#define cpu_icache_snoops_remote_store 1
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_CPU_MIPS64
|
||||
#define cpu_has_tlb 1
|
||||
#define cpu_has_4kex 1
|
||||
#define cpu_has_4k_cache 1
|
||||
/* #define cpu_has_fpu ? */
|
||||
/* #define cpu_has_32fpr ? */
|
||||
#define cpu_has_counter 1
|
||||
/* #define cpu_has_watch ? */
|
||||
#define cpu_has_divec 1
|
||||
#define cpu_has_vce 0
|
||||
/* #define cpu_has_cache_cdex_p ? */
|
||||
/* #define cpu_has_cache_cdex_s ? */
|
||||
/* #define cpu_has_prefetch ? */
|
||||
#define cpu_has_mcheck 1
|
||||
/* #define cpu_has_ejtag ? */
|
||||
#define cpu_has_llsc 1
|
||||
/* #define cpu_has_vtag_icache ? */
|
||||
/* #define cpu_has_dc_aliases ? */
|
||||
/* #define cpu_has_ic_fills_f_dc ? */
|
||||
#define cpu_has_nofpuex 0
|
||||
/* #define cpu_has_64bits ? */
|
||||
/* #define cpu_has_64bit_zero_reg ? */
|
||||
/* #define cpu_has_inclusive_pcaches ? */
|
||||
#define cpu_icache_snoops_remote_store 1
|
||||
#endif
|
||||
|
||||
#endif /* __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H */
|
||||
@ -1,9 +0,0 @@
|
||||
#ifndef __ASM_MACH_MIPS_IRQ_H
|
||||
#define __ASM_MACH_MIPS_IRQ_H
|
||||
|
||||
#define NR_IRQS 256
|
||||
|
||||
|
||||
#include_next <irq.h>
|
||||
|
||||
#endif /* __ASM_MACH_MIPS_IRQ_H */
|
||||
@ -1,21 +0,0 @@
|
||||
/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Chris Dearman (chris@mips.com)
|
||||
* Copyright (C) 2007 Mips Technologies, Inc.
|
||||
*/
|
||||
#ifndef __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H
|
||||
#define __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H
|
||||
|
||||
.macro kernel_entry_setup
|
||||
.endm
|
||||
|
||||
/*
|
||||
* Do SMP slave processor setup necessary before we can safely execute C code.
|
||||
*/
|
||||
.macro smp_slave_setup
|
||||
.endm
|
||||
|
||||
#endif /* __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H */
|
||||
@ -1,29 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2016 Imagination Technologies
|
||||
* Author: Paul Burton <paul.burton@imgtec.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef __MIPS_SEAD3_DTSHIM_H__
|
||||
#define __MIPS_SEAD3_DTSHIM_H__
|
||||
|
||||
#include <linux/init.h>
|
||||
|
||||
#ifdef CONFIG_MIPS_SEAD3
|
||||
|
||||
extern void __init *sead3_dt_shim(void *fdt);
|
||||
|
||||
#else /* !CONFIG_MIPS_SEAD3 */
|
||||
|
||||
static inline void *sead3_dt_shim(void *fdt)
|
||||
{
|
||||
return fdt;
|
||||
}
|
||||
|
||||
#endif /* !CONFIG_MIPS_SEAD3 */
|
||||
|
||||
#endif /* __MIPS_SEAD3_DTSHIM_H__ */
|
||||
@ -1,24 +0,0 @@
|
||||
/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
|
||||
*/
|
||||
#ifndef __ASM_MIPS_MACH_MIPS_WAR_H
|
||||
#define __ASM_MIPS_MACH_MIPS_WAR_H
|
||||
|
||||
#define R4600_V1_INDEX_ICACHEOP_WAR 0
|
||||
#define R4600_V1_HIT_CACHEOP_WAR 0
|
||||
#define R4600_V2_HIT_CACHEOP_WAR 0
|
||||
#define R5432_CP0_INTERRUPT_WAR 0
|
||||
#define BCM1250_M3_WAR 0
|
||||
#define SIBYTE_1956_WAR 0
|
||||
#define MIPS4K_ICACHE_REFILL_WAR 1
|
||||
#define MIPS_CACHE_SYNC_WAR 1
|
||||
#define TX49XX_ICACHE_INDEX_INV_WAR 0
|
||||
#define ICACHE_REFILLS_WORKAROUND_WAR 1
|
||||
#define R10000_LLSC_WAR 0
|
||||
#define MIPS34K_MISSED_ITLB_WAR 0
|
||||
|
||||
#endif /* __ASM_MIPS_MACH_MIPS_WAR_H */
|
||||
@ -1,15 +0,0 @@
|
||||
#
|
||||
# Carsten Langgaard, carstenl@mips.com
|
||||
# Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
|
||||
#
|
||||
# Copyright (C) 2008 Wind River Systems, Inc.
|
||||
# written by Ralf Baechle <ralf@linux-mips.org>
|
||||
#
|
||||
# Copyright (C) 2012 MIPS Technoligies, Inc. All rights reserved.
|
||||
# Steven J. Hill <sjhill@mips.com>
|
||||
#
|
||||
obj-y := sead3-dtshim.o
|
||||
obj-y += sead3-init.o
|
||||
obj-y += sead3-int.o
|
||||
obj-y += sead3-setup.o
|
||||
obj-y += sead3-time.o
|
||||
@ -1,7 +0,0 @@
|
||||
#
|
||||
# MIPS SEAD-3 board
|
||||
#
|
||||
platform-$(CONFIG_MIPS_SEAD3) += mti-sead3/
|
||||
cflags-$(CONFIG_MIPS_SEAD3) += -I$(srctree)/arch/mips/include/asm/mach-sead3
|
||||
load-$(CONFIG_MIPS_SEAD3) += 0xffffffff80100000
|
||||
all-$(CONFIG_MIPS_SEAD3) := $(COMPRESSION_FNAME).srec
|
||||
@ -1,100 +0,0 @@
|
||||
/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
#include <asm/bootinfo.h>
|
||||
#include <asm/cacheflush.h>
|
||||
#include <asm/traps.h>
|
||||
#include <asm/mips-boards/generic.h>
|
||||
#include <asm/fw/fw.h>
|
||||
|
||||
extern char except_vec_nmi;
|
||||
extern char except_vec_ejtag_debug;
|
||||
|
||||
static void __init mips_nmi_setup(void)
|
||||
{
|
||||
void *base;
|
||||
|
||||
base = cpu_has_veic ?
|
||||
(void *)(CAC_BASE + 0xa80) :
|
||||
(void *)(CAC_BASE + 0x380);
|
||||
#ifdef CONFIG_CPU_MICROMIPS
|
||||
/*
|
||||
* Decrement the exception vector address by one for microMIPS.
|
||||
*/
|
||||
memcpy(base, (&except_vec_nmi - 1), 0x80);
|
||||
|
||||
/*
|
||||
* This is a hack. We do not know if the boot loader was built with
|
||||
* microMIPS instructions or not. If it was not, the NMI exception
|
||||
* code at 0x80000a80 will be taken in MIPS32 mode. The hand coded
|
||||
* assembly below forces us into microMIPS mode if we are a pure
|
||||
* microMIPS kernel. The assembly instructions are:
|
||||
*
|
||||
* 3C1A8000 lui k0,0x8000
|
||||
* 375A0381 ori k0,k0,0x381
|
||||
* 03400008 jr k0
|
||||
* 00000000 nop
|
||||
*
|
||||
* The mode switch occurs by jumping to the unaligned exception
|
||||
* vector address at 0x80000381 which would have been 0x80000380
|
||||
* in MIPS32 mode. The jump to the unaligned address transitions
|
||||
* us into microMIPS mode.
|
||||
*/
|
||||
if (!cpu_has_veic) {
|
||||
void *base2 = (void *)(CAC_BASE + 0xa80);
|
||||
*((unsigned int *)base2) = 0x3c1a8000;
|
||||
*((unsigned int *)base2 + 1) = 0x375a0381;
|
||||
*((unsigned int *)base2 + 2) = 0x03400008;
|
||||
*((unsigned int *)base2 + 3) = 0x00000000;
|
||||
flush_icache_range((unsigned long)base2,
|
||||
(unsigned long)base2 + 0x10);
|
||||
}
|
||||
#else
|
||||
memcpy(base, &except_vec_nmi, 0x80);
|
||||
#endif
|
||||
flush_icache_range((unsigned long)base, (unsigned long)base + 0x80);
|
||||
}
|
||||
|
||||
static void __init mips_ejtag_setup(void)
|
||||
{
|
||||
void *base;
|
||||
|
||||
base = cpu_has_veic ?
|
||||
(void *)(CAC_BASE + 0xa00) :
|
||||
(void *)(CAC_BASE + 0x300);
|
||||
#ifdef CONFIG_CPU_MICROMIPS
|
||||
/* Deja vu... */
|
||||
memcpy(base, (&except_vec_ejtag_debug - 1), 0x80);
|
||||
if (!cpu_has_veic) {
|
||||
void *base2 = (void *)(CAC_BASE + 0xa00);
|
||||
*((unsigned int *)base2) = 0x3c1a8000;
|
||||
*((unsigned int *)base2 + 1) = 0x375a0301;
|
||||
*((unsigned int *)base2 + 2) = 0x03400008;
|
||||
*((unsigned int *)base2 + 3) = 0x00000000;
|
||||
flush_icache_range((unsigned long)base2,
|
||||
(unsigned long)base2 + 0x10);
|
||||
}
|
||||
#else
|
||||
memcpy(base, &except_vec_ejtag_debug, 0x80);
|
||||
#endif
|
||||
flush_icache_range((unsigned long)base, (unsigned long)base + 0x80);
|
||||
}
|
||||
|
||||
void __init prom_init(void)
|
||||
{
|
||||
board_nmi_handler_setup = mips_nmi_setup;
|
||||
board_ejtag_handler_setup = mips_ejtag_setup;
|
||||
|
||||
fw_init_cmdline();
|
||||
}
|
||||
|
||||
void __init prom_free_prom_memory(void)
|
||||
{
|
||||
}
|
||||
@ -1,23 +0,0 @@
|
||||
/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/irqchip.h>
|
||||
#include <linux/irqchip/mips-gic.h>
|
||||
|
||||
#include <asm/cpu-info.h>
|
||||
#include <asm/irq.h>
|
||||
|
||||
void __init arch_init_irq(void)
|
||||
{
|
||||
irqchip_init();
|
||||
|
||||
pr_info("GIC: %spresent\n", (gic_present) ? "" : "not ");
|
||||
pr_info("EIC: %s\n",
|
||||
(current_cpu_data.options & MIPS_CPU_VEIC) ? "on" : "off");
|
||||
}
|
||||
|
||||
@ -1,39 +0,0 @@
|
||||
/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
|
||||
* Copyright (C) 2013 Imagination Technologies Ltd.
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/libfdt.h>
|
||||
#include <linux/of_fdt.h>
|
||||
|
||||
#include <asm/prom.h>
|
||||
|
||||
#include <asm/mach-sead3/sead3-dtshim.h>
|
||||
#include <asm/mips-boards/generic.h>
|
||||
|
||||
const char *get_system_type(void)
|
||||
{
|
||||
return "MIPS SEAD3";
|
||||
}
|
||||
|
||||
void __init *plat_get_fdt(void)
|
||||
{
|
||||
return (void *)__dtb_start;
|
||||
}
|
||||
|
||||
void __init plat_mem_setup(void)
|
||||
{
|
||||
void *fdt = plat_get_fdt();
|
||||
|
||||
fdt = sead3_dt_shim(fdt);
|
||||
__dt_setup_arch(fdt);
|
||||
}
|
||||
|
||||
void __init device_tree_init(void)
|
||||
{
|
||||
unflatten_and_copy_device_tree();
|
||||
}
|
||||
@ -1,91 +0,0 @@
|
||||
/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/irqchip/mips-gic.h>
|
||||
|
||||
#include <asm/cpu.h>
|
||||
#include <asm/setup.h>
|
||||
#include <asm/time.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/mips-boards/generic.h>
|
||||
|
||||
static void __iomem *status_reg = (void __iomem *)0xbf000410;
|
||||
|
||||
/*
|
||||
* Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect.
|
||||
*/
|
||||
static unsigned int __init estimate_cpu_frequency(void)
|
||||
{
|
||||
unsigned int prid = read_c0_prid() & (PRID_COMP_MASK | PRID_IMP_MASK);
|
||||
unsigned int tick = 0;
|
||||
unsigned int freq;
|
||||
unsigned int orig;
|
||||
unsigned long flags;
|
||||
|
||||
local_irq_save(flags);
|
||||
|
||||
orig = readl(status_reg) & 0x2; /* get original sample */
|
||||
/* wait for transition */
|
||||
while ((readl(status_reg) & 0x2) == orig)
|
||||
;
|
||||
orig = orig ^ 0x2; /* flip the bit */
|
||||
|
||||
write_c0_count(0);
|
||||
|
||||
/* wait 1 second (the sampling clock transitions every 10ms) */
|
||||
while (tick < 100) {
|
||||
/* wait for transition */
|
||||
while ((readl(status_reg) & 0x2) == orig)
|
||||
;
|
||||
orig = orig ^ 0x2; /* flip the bit */
|
||||
tick++;
|
||||
}
|
||||
|
||||
freq = read_c0_count();
|
||||
|
||||
local_irq_restore(flags);
|
||||
|
||||
mips_hpt_frequency = freq;
|
||||
|
||||
/* Adjust for processor */
|
||||
if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) &&
|
||||
(prid != (PRID_COMP_MIPS | PRID_IMP_25KF)))
|
||||
freq *= 2;
|
||||
|
||||
freq += 5000; /* rounding */
|
||||
freq -= freq%10000;
|
||||
|
||||
return freq ;
|
||||
}
|
||||
|
||||
int get_c0_perfcount_int(void)
|
||||
{
|
||||
if (gic_present)
|
||||
return gic_get_c0_perfcount_int();
|
||||
if (cp0_perfcount_irq >= 0)
|
||||
return MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
|
||||
return -1;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(get_c0_perfcount_int);
|
||||
|
||||
unsigned int get_c0_compare_int(void)
|
||||
{
|
||||
if (gic_present)
|
||||
return gic_get_c0_compare_int();
|
||||
return MIPS_CPU_IRQ_BASE + cp0_compare_irq;
|
||||
}
|
||||
|
||||
void __init plat_time_init(void)
|
||||
{
|
||||
unsigned int est_freq;
|
||||
|
||||
est_freq = estimate_cpu_frequency();
|
||||
|
||||
pr_debug("CPU frequency %d.%02d MHz\n", (est_freq / 1000000),
|
||||
(est_freq % 1000000) * 100 / 1000000);
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user