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net/mlx5e: SHAMPO, clean MLX5E_MAX_KLM_PER_WQE macro
This commit reduces unused variable from MLX5E_MAX_KLM_PER_WQE macro that
introduced by commit d7b896acbd
("net/mlx5e: Add support to klm_umr_wqe").
Signed-off-by: Ben Ben-Ishay <benishay@nvidia.com>
Reviewed-by: Tariq Toukan <tariqt@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
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@ -173,7 +173,7 @@ struct page_pool;
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#define MLX5E_KLM_ENTRIES_PER_WQE(wqe_size)\
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ALIGN_DOWN(MLX5E_KLM_MAX_ENTRIES_PER_WQE(wqe_size), MLX5_UMR_KLM_ALIGNMENT)
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#define MLX5E_MAX_KLM_PER_WQE(mdev) \
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#define MLX5E_MAX_KLM_PER_WQE \
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MLX5E_KLM_ENTRIES_PER_WQE(MLX5E_TX_MPW_MAX_NUM_DS << MLX5_MKEY_BSF_OCTO_SIZE)
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#define MLX5E_MSG_LEVEL NETIF_MSG_LINK
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@ -717,7 +717,7 @@ static u32 mlx5e_shampo_icosq_sz(struct mlx5_core_dev *mdev,
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int wq_size = BIT(MLX5_GET(wq, wqc, log_wq_sz));
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u32 wqebbs;
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max_klm_per_umr = MLX5E_MAX_KLM_PER_WQE(mdev);
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max_klm_per_umr = MLX5E_MAX_KLM_PER_WQE;
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max_hd_per_wqe = mlx5e_shampo_hd_per_wqe(mdev, params, rq_param);
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max_num_of_umr_per_wqe = max_hd_per_wqe / max_klm_per_umr;
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rest = max_hd_per_wqe % max_klm_per_umr;
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@ -619,7 +619,7 @@ static int mlx5e_alloc_rx_hd_mpwqe(struct mlx5e_rq *rq)
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struct mlx5e_icosq *sq = rq->icosq;
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int i, err, max_klm_entries, len;
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max_klm_entries = MLX5E_MAX_KLM_PER_WQE(rq->mdev);
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max_klm_entries = MLX5E_MAX_KLM_PER_WQE;
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klm_entries = bitmap_find_window(shampo->bitmap,
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shampo->hd_per_wqe,
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shampo->hd_per_wq, shampo->pi);
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