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iio: Add driver for Murata IRS-D200
Murata IRS-D200 is a PIR sensor for human detection. It has support for raw data measurements and detection event notification. Add a driver with support for triggered buffer and events. Map the various settings to the `iio` framework, e.g. threshold values, sampling frequency, filter frequencies etc. Signed-off-by: Waqar Hameed <waqar.hameed@axis.com> Link: https://lore.kernel.org/r/d218a1bc75402b5ebd6e12a563f7315f83fe966c.1689753076.git.waqar.hameed@axis.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
This commit is contained in:
Waqar Hameed
Jonathan Cameron
parent
5e1cd3e97e
commit
3db3562bc6
@ -32,6 +32,18 @@ config CROS_EC_MKBP_PROXIMITY
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To compile this driver as a module, choose M here: the
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module will be called cros_ec_mkbp_proximity.
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config IRSD200
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tristate "Murata IRS-D200 PIR sensor"
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select IIO_BUFFER
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select IIO_TRIGGERED_BUFFER
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select REGMAP_I2C
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depends on I2C
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help
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Say Y here to build a driver for the Murata IRS-D200 PIR sensor.
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To compile this driver as a module, choose M here: the module will be
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called irsd200.
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config ISL29501
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tristate "Intersil ISL29501 Time Of Flight sensor"
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depends on I2C
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@ -6,6 +6,7 @@
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# When adding new entries keep the list in alphabetical order
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obj-$(CONFIG_AS3935) += as3935.o
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obj-$(CONFIG_CROS_EC_MKBP_PROXIMITY) += cros_ec_mkbp_proximity.o
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obj-$(CONFIG_IRSD200) += irsd200.o
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obj-$(CONFIG_ISL29501) += isl29501.o
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obj-$(CONFIG_LIDAR_LITE_V2) += pulsedlight-lidar-lite-v2.o
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obj-$(CONFIG_MB1232) += mb1232.o
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958
drivers/iio/proximity/irsd200.c
Normal file
958
drivers/iio/proximity/irsd200.c
Normal file
@ -0,0 +1,958 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Driver for Murata IRS-D200 PIR sensor.
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*
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* Copyright (C) 2023 Axis Communications AB
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*/
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#include <asm/unaligned.h>
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#include <linux/bitfield.h>
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#include <linux/gpio.h>
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#include <linux/i2c.h>
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#include <linux/module.h>
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#include <linux/regmap.h>
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#include <linux/iio/buffer.h>
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#include <linux/iio/events.h>
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#include <linux/iio/iio.h>
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#include <linux/iio/trigger.h>
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#include <linux/iio/trigger_consumer.h>
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#include <linux/iio/triggered_buffer.h>
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#include <linux/iio/types.h>
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#define IRS_DRV_NAME "irsd200"
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/* Registers. */
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#define IRS_REG_OP 0x00 /* Operation mode. */
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#define IRS_REG_DATA_LO 0x02 /* Sensor data LSB. */
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#define IRS_REG_DATA_HI 0x03 /* Sensor data MSB. */
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#define IRS_REG_STATUS 0x04 /* Interrupt status. */
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#define IRS_REG_COUNT 0x05 /* Count of exceeding threshold. */
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#define IRS_REG_DATA_RATE 0x06 /* Output data rate. */
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#define IRS_REG_FILTER 0x07 /* High-pass and low-pass filter. */
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#define IRS_REG_INTR 0x09 /* Interrupt mode. */
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#define IRS_REG_NR_COUNT 0x0a /* Number of counts before interrupt. */
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#define IRS_REG_THR_HI 0x0b /* Upper threshold. */
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#define IRS_REG_THR_LO 0x0c /* Lower threshold. */
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#define IRS_REG_TIMER_LO 0x0d /* Timer setting LSB. */
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#define IRS_REG_TIMER_HI 0x0e /* Timer setting MSB. */
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/* Interrupt status bits. */
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#define IRS_INTR_DATA 0 /* Data update. */
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#define IRS_INTR_TIMER 1 /* Timer expiration. */
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#define IRS_INTR_COUNT_THR_AND 2 /* Count "AND" threshold. */
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#define IRS_INTR_COUNT_THR_OR 3 /* Count "OR" threshold. */
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/* Operation states. */
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#define IRS_OP_ACTIVE 0x00
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#define IRS_OP_SLEEP 0x01
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/*
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* Quantization scale value for threshold. Used for conversion from/to register
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* value.
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*/
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#define IRS_THR_QUANT_SCALE 128
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#define IRS_UPPER_COUNT(count) FIELD_GET(GENMASK(7, 4), count)
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#define IRS_LOWER_COUNT(count) FIELD_GET(GENMASK(3, 0), count)
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/* Index corresponds to the value of IRS_REG_DATA_RATE register. */
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static const int irsd200_data_rates[] = {
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50,
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100,
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};
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/* Index corresponds to the (field) value of IRS_REG_FILTER register. */
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static const unsigned int irsd200_lp_filter_freq[] = {
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10,
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7,
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};
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/*
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* Index corresponds to the (field) value of IRS_REG_FILTER register. Note that
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* this represents a fractional value (e.g the first value corresponds to 3 / 10
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* = 0.3 Hz).
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*/
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static const unsigned int irsd200_hp_filter_freq[][2] = {
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{ 3, 10 },
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{ 5, 10 },
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};
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/* Register fields. */
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enum irsd200_regfield {
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/* Data interrupt. */
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IRS_REGF_INTR_DATA,
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/* Timer interrupt. */
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IRS_REGF_INTR_TIMER,
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/* AND count threshold interrupt. */
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IRS_REGF_INTR_COUNT_THR_AND,
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/* OR count threshold interrupt. */
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IRS_REGF_INTR_COUNT_THR_OR,
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/* Low-pass filter frequency. */
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IRS_REGF_LP_FILTER,
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/* High-pass filter frequency. */
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IRS_REGF_HP_FILTER,
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/* Sentinel value. */
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IRS_REGF_MAX
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};
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static const struct reg_field irsd200_regfields[] = {
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[IRS_REGF_INTR_DATA] =
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REG_FIELD(IRS_REG_INTR, IRS_INTR_DATA, IRS_INTR_DATA),
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[IRS_REGF_INTR_TIMER] =
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REG_FIELD(IRS_REG_INTR, IRS_INTR_TIMER, IRS_INTR_TIMER),
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[IRS_REGF_INTR_COUNT_THR_AND] = REG_FIELD(
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IRS_REG_INTR, IRS_INTR_COUNT_THR_AND, IRS_INTR_COUNT_THR_AND),
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[IRS_REGF_INTR_COUNT_THR_OR] = REG_FIELD(
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IRS_REG_INTR, IRS_INTR_COUNT_THR_OR, IRS_INTR_COUNT_THR_OR),
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[IRS_REGF_LP_FILTER] = REG_FIELD(IRS_REG_FILTER, 1, 1),
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[IRS_REGF_HP_FILTER] = REG_FIELD(IRS_REG_FILTER, 0, 0),
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};
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static const struct regmap_config irsd200_regmap_config = {
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.reg_bits = 8,
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.val_bits = 8,
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.max_register = IRS_REG_TIMER_HI,
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};
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struct irsd200_data {
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struct regmap *regmap;
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struct regmap_field *regfields[IRS_REGF_MAX];
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struct device *dev;
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};
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static int irsd200_setup(struct irsd200_data *data)
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{
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unsigned int val;
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int ret;
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/* Disable all interrupt sources. */
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ret = regmap_write(data->regmap, IRS_REG_INTR, 0);
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if (ret) {
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dev_err(data->dev, "Could not set interrupt sources (%d)\n",
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ret);
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return ret;
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}
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/* Set operation to active. */
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ret = regmap_write(data->regmap, IRS_REG_OP, IRS_OP_ACTIVE);
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if (ret) {
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dev_err(data->dev, "Could not set operation mode (%d)\n", ret);
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return ret;
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}
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/* Clear threshold count. */
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ret = regmap_read(data->regmap, IRS_REG_COUNT, &val);
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if (ret) {
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dev_err(data->dev, "Could not clear threshold count (%d)\n",
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ret);
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return ret;
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}
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/* Clear status. */
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ret = regmap_write(data->regmap, IRS_REG_STATUS, 0x0f);
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if (ret) {
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dev_err(data->dev, "Could not clear status (%d)\n", ret);
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return ret;
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}
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return 0;
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}
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static int irsd200_read_threshold(struct irsd200_data *data,
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enum iio_event_direction dir, int *val)
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{
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unsigned int regval;
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unsigned int reg;
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int scale;
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int ret;
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/* Set quantization scale. */
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if (dir == IIO_EV_DIR_RISING) {
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scale = IRS_THR_QUANT_SCALE;
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reg = IRS_REG_THR_HI;
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} else if (dir == IIO_EV_DIR_FALLING) {
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scale = -IRS_THR_QUANT_SCALE;
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reg = IRS_REG_THR_LO;
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} else {
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return -EINVAL;
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}
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ret = regmap_read(data->regmap, reg, ®val);
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if (ret) {
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dev_err(data->dev, "Could not read threshold (%d)\n", ret);
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return ret;
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}
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*val = ((int)regval) * scale;
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return 0;
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}
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static int irsd200_write_threshold(struct irsd200_data *data,
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enum iio_event_direction dir, int val)
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{
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unsigned int regval;
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unsigned int reg;
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int scale;
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int ret;
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/* Set quantization scale. */
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if (dir == IIO_EV_DIR_RISING) {
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if (val < 0)
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return -ERANGE;
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scale = IRS_THR_QUANT_SCALE;
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reg = IRS_REG_THR_HI;
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} else if (dir == IIO_EV_DIR_FALLING) {
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if (val > 0)
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return -ERANGE;
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scale = -IRS_THR_QUANT_SCALE;
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reg = IRS_REG_THR_LO;
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} else {
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return -EINVAL;
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}
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regval = val / scale;
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if (regval >= BIT(8))
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return -ERANGE;
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ret = regmap_write(data->regmap, reg, regval);
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if (ret) {
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dev_err(data->dev, "Could not write threshold (%d)\n", ret);
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return ret;
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}
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return 0;
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}
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static int irsd200_read_data(struct irsd200_data *data, s16 *val)
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{
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__le16 buf;
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int ret;
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ret = regmap_bulk_read(data->regmap, IRS_REG_DATA_LO, &buf,
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sizeof(buf));
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if (ret) {
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dev_err(data->dev, "Could not bulk read data (%d)\n", ret);
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return ret;
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}
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*val = le16_to_cpu(buf);
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return 0;
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}
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static int irsd200_read_data_rate(struct irsd200_data *data, int *val)
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{
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unsigned int regval;
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int ret;
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ret = regmap_read(data->regmap, IRS_REG_DATA_RATE, ®val);
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if (ret) {
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dev_err(data->dev, "Could not read data rate (%d)\n", ret);
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return ret;
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}
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if (regval >= ARRAY_SIZE(irsd200_data_rates))
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return -ERANGE;
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*val = irsd200_data_rates[regval];
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return 0;
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}
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static int irsd200_write_data_rate(struct irsd200_data *data, int val)
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{
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size_t idx;
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int ret;
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for (idx = 0; idx < ARRAY_SIZE(irsd200_data_rates); ++idx) {
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if (irsd200_data_rates[idx] == val)
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break;
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}
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if (idx == ARRAY_SIZE(irsd200_data_rates))
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return -ERANGE;
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ret = regmap_write(data->regmap, IRS_REG_DATA_RATE, idx);
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if (ret) {
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dev_err(data->dev, "Could not write data rate (%d)\n", ret);
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return ret;
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}
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/*
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* Data sheet says the device needs 3 seconds of settling time. The
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* device operates normally during this period though. This is more of a
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* "guarantee" than trying to prevent other user space reads/writes.
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*/
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ssleep(3);
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return 0;
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}
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static int irsd200_read_timer(struct irsd200_data *data, int *val, int *val2)
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{
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__le16 buf;
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int ret;
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ret = regmap_bulk_read(data->regmap, IRS_REG_TIMER_LO, &buf,
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sizeof(buf));
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if (ret) {
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dev_err(data->dev, "Could not bulk read timer (%d)\n", ret);
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return ret;
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}
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ret = irsd200_read_data_rate(data, val2);
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if (ret)
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return ret;
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*val = le16_to_cpu(buf);
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return 0;
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}
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static int irsd200_write_timer(struct irsd200_data *data, int val, int val2)
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{
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unsigned int regval;
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int data_rate;
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__le16 buf;
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int ret;
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if (val < 0 || val2 < 0)
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return -ERANGE;
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ret = irsd200_read_data_rate(data, &data_rate);
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if (ret)
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return ret;
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/* Quantize from seconds. */
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regval = val * data_rate + (val2 * data_rate) / 1000000;
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/* Value is 10 bits. */
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if (regval >= BIT(10))
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return -ERANGE;
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buf = cpu_to_le16((u16)regval);
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ret = regmap_bulk_write(data->regmap, IRS_REG_TIMER_LO, &buf,
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sizeof(buf));
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if (ret) {
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dev_err(data->dev, "Could not bulk write timer (%d)\n", ret);
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return ret;
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}
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return 0;
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}
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static int irsd200_read_nr_count(struct irsd200_data *data, int *val)
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{
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unsigned int regval;
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int ret;
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ret = regmap_read(data->regmap, IRS_REG_NR_COUNT, ®val);
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if (ret) {
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dev_err(data->dev, "Could not read nr count (%d)\n", ret);
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return ret;
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}
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*val = regval;
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return 0;
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}
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static int irsd200_write_nr_count(struct irsd200_data *data, int val)
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{
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unsigned int regval;
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int ret;
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/* A value of zero means that IRS_REG_STATUS is never set. */
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if (val <= 0 || val >= 8)
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return -ERANGE;
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regval = val;
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if (regval >= 2) {
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/*
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* According to the data sheet, timer must be also set in this
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* case (i.e. be non-zero). Check and enforce that.
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*/
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ret = irsd200_read_timer(data, &val, &val);
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if (ret)
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return ret;
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if (val == 0) {
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dev_err(data->dev,
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"Timer must be non-zero when nr count is %u\n",
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regval);
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return -EPERM;
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}
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}
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ret = regmap_write(data->regmap, IRS_REG_NR_COUNT, regval);
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if (ret) {
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dev_err(data->dev, "Could not write nr count (%d)\n", ret);
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return ret;
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}
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return 0;
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}
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static int irsd200_read_lp_filter(struct irsd200_data *data, int *val)
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{
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unsigned int regval;
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int ret;
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ret = regmap_field_read(data->regfields[IRS_REGF_LP_FILTER], ®val);
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if (ret) {
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dev_err(data->dev, "Could not read lp filter frequency (%d)\n",
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ret);
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return ret;
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}
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*val = irsd200_lp_filter_freq[regval];
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return 0;
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}
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static int irsd200_write_lp_filter(struct irsd200_data *data, int val)
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{
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size_t idx;
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int ret;
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for (idx = 0; idx < ARRAY_SIZE(irsd200_lp_filter_freq); ++idx) {
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if (irsd200_lp_filter_freq[idx] == val)
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break;
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}
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if (idx == ARRAY_SIZE(irsd200_lp_filter_freq))
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return -ERANGE;
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ret = regmap_field_write(data->regfields[IRS_REGF_LP_FILTER], idx);
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if (ret) {
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dev_err(data->dev, "Could not write lp filter frequency (%d)\n",
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ret);
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return ret;
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}
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return 0;
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}
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static int irsd200_read_hp_filter(struct irsd200_data *data, int *val,
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int *val2)
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{
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unsigned int regval;
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int ret;
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|
||||
ret = regmap_field_read(data->regfields[IRS_REGF_HP_FILTER], ®val);
|
||||
if (ret) {
|
||||
dev_err(data->dev, "Could not read hp filter frequency (%d)\n",
|
||||
ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
*val = irsd200_hp_filter_freq[regval][0];
|
||||
*val2 = irsd200_hp_filter_freq[regval][1];
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int irsd200_write_hp_filter(struct irsd200_data *data, int val, int val2)
|
||||
{
|
||||
size_t idx;
|
||||
int ret;
|
||||
|
||||
/* Truncate fractional part to one digit. */
|
||||
val2 /= 100000;
|
||||
|
||||
for (idx = 0; idx < ARRAY_SIZE(irsd200_hp_filter_freq); ++idx) {
|
||||
if (irsd200_hp_filter_freq[idx][0] == val2)
|
||||
break;
|
||||
}
|
||||
|
||||
if (idx == ARRAY_SIZE(irsd200_hp_filter_freq) || val != 0)
|
||||
return -ERANGE;
|
||||
|
||||
ret = regmap_field_write(data->regfields[IRS_REGF_HP_FILTER], idx);
|
||||
if (ret) {
|
||||
dev_err(data->dev, "Could not write hp filter frequency (%d)\n",
|
||||
ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int irsd200_read_raw(struct iio_dev *indio_dev,
|
||||
struct iio_chan_spec const *chan, int *val,
|
||||
int *val2, long mask)
|
||||
{
|
||||
struct irsd200_data *data = iio_priv(indio_dev);
|
||||
int ret;
|
||||
s16 buf;
|
||||
|
||||
switch (mask) {
|
||||
case IIO_CHAN_INFO_RAW:
|
||||
ret = irsd200_read_data(data, &buf);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
*val = buf;
|
||||
return IIO_VAL_INT;
|
||||
case IIO_CHAN_INFO_SAMP_FREQ:
|
||||
ret = irsd200_read_data_rate(data, val);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return IIO_VAL_INT;
|
||||
case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
|
||||
ret = irsd200_read_lp_filter(data, val);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return IIO_VAL_INT;
|
||||
case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
|
||||
ret = irsd200_read_hp_filter(data, val, val2);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return IIO_VAL_FRACTIONAL;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
static int irsd200_read_avail(struct iio_dev *indio_dev,
|
||||
struct iio_chan_spec const *chan,
|
||||
const int **vals, int *type, int *length,
|
||||
long mask)
|
||||
{
|
||||
switch (mask) {
|
||||
case IIO_CHAN_INFO_SAMP_FREQ:
|
||||
*vals = irsd200_data_rates;
|
||||
*type = IIO_VAL_INT;
|
||||
*length = ARRAY_SIZE(irsd200_data_rates);
|
||||
return IIO_AVAIL_LIST;
|
||||
case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
|
||||
*vals = irsd200_lp_filter_freq;
|
||||
*type = IIO_VAL_INT;
|
||||
*length = ARRAY_SIZE(irsd200_lp_filter_freq);
|
||||
return IIO_AVAIL_LIST;
|
||||
case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
|
||||
*vals = (int *)irsd200_hp_filter_freq;
|
||||
*type = IIO_VAL_FRACTIONAL;
|
||||
*length = 2 * ARRAY_SIZE(irsd200_hp_filter_freq);
|
||||
return IIO_AVAIL_LIST;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
static int irsd200_write_raw(struct iio_dev *indio_dev,
|
||||
struct iio_chan_spec const *chan, int val,
|
||||
int val2, long mask)
|
||||
{
|
||||
struct irsd200_data *data = iio_priv(indio_dev);
|
||||
|
||||
switch (mask) {
|
||||
case IIO_CHAN_INFO_SAMP_FREQ:
|
||||
return irsd200_write_data_rate(data, val);
|
||||
case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
|
||||
return irsd200_write_lp_filter(data, val);
|
||||
case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
|
||||
return irsd200_write_hp_filter(data, val, val2);
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
static int irsd200_read_event(struct iio_dev *indio_dev,
|
||||
const struct iio_chan_spec *chan,
|
||||
enum iio_event_type type,
|
||||
enum iio_event_direction dir,
|
||||
enum iio_event_info info, int *val, int *val2)
|
||||
{
|
||||
struct irsd200_data *data = iio_priv(indio_dev);
|
||||
int ret;
|
||||
|
||||
switch (info) {
|
||||
case IIO_EV_INFO_VALUE:
|
||||
ret = irsd200_read_threshold(data, dir, val);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return IIO_VAL_INT;
|
||||
case IIO_EV_INFO_RUNNING_PERIOD:
|
||||
ret = irsd200_read_timer(data, val, val2);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return IIO_VAL_FRACTIONAL;
|
||||
case IIO_EV_INFO_RUNNING_COUNT:
|
||||
ret = irsd200_read_nr_count(data, val);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return IIO_VAL_INT;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
static int irsd200_write_event(struct iio_dev *indio_dev,
|
||||
const struct iio_chan_spec *chan,
|
||||
enum iio_event_type type,
|
||||
enum iio_event_direction dir,
|
||||
enum iio_event_info info, int val, int val2)
|
||||
{
|
||||
struct irsd200_data *data = iio_priv(indio_dev);
|
||||
|
||||
switch (info) {
|
||||
case IIO_EV_INFO_VALUE:
|
||||
return irsd200_write_threshold(data, dir, val);
|
||||
case IIO_EV_INFO_RUNNING_PERIOD:
|
||||
return irsd200_write_timer(data, val, val2);
|
||||
case IIO_EV_INFO_RUNNING_COUNT:
|
||||
return irsd200_write_nr_count(data, val);
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
static int irsd200_read_event_config(struct iio_dev *indio_dev,
|
||||
const struct iio_chan_spec *chan,
|
||||
enum iio_event_type type,
|
||||
enum iio_event_direction dir)
|
||||
{
|
||||
struct irsd200_data *data = iio_priv(indio_dev);
|
||||
unsigned int val;
|
||||
int ret;
|
||||
|
||||
switch (type) {
|
||||
case IIO_EV_TYPE_THRESH:
|
||||
ret = regmap_field_read(
|
||||
data->regfields[IRS_REGF_INTR_COUNT_THR_OR], &val);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return val;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
static int irsd200_write_event_config(struct iio_dev *indio_dev,
|
||||
const struct iio_chan_spec *chan,
|
||||
enum iio_event_type type,
|
||||
enum iio_event_direction dir, int state)
|
||||
{
|
||||
struct irsd200_data *data = iio_priv(indio_dev);
|
||||
unsigned int tmp;
|
||||
int ret;
|
||||
|
||||
switch (type) {
|
||||
case IIO_EV_TYPE_THRESH:
|
||||
/* Clear the count register (by reading from it). */
|
||||
ret = regmap_read(data->regmap, IRS_REG_COUNT, &tmp);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return regmap_field_write(
|
||||
data->regfields[IRS_REGF_INTR_COUNT_THR_OR], !!state);
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
static irqreturn_t irsd200_irq_thread(int irq, void *dev_id)
|
||||
{
|
||||
struct iio_dev *indio_dev = dev_id;
|
||||
struct irsd200_data *data = iio_priv(indio_dev);
|
||||
enum iio_event_direction dir;
|
||||
unsigned int lower_count;
|
||||
unsigned int upper_count;
|
||||
unsigned int status = 0;
|
||||
unsigned int source = 0;
|
||||
unsigned int clear = 0;
|
||||
unsigned int count = 0;
|
||||
int ret;
|
||||
|
||||
ret = regmap_read(data->regmap, IRS_REG_INTR, &source);
|
||||
if (ret) {
|
||||
dev_err(data->dev, "Could not read interrupt source (%d)\n",
|
||||
ret);
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
ret = regmap_read(data->regmap, IRS_REG_STATUS, &status);
|
||||
if (ret) {
|
||||
dev_err(data->dev, "Could not acknowledge interrupt (%d)\n",
|
||||
ret);
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
if (status & BIT(IRS_INTR_DATA) && iio_buffer_enabled(indio_dev)) {
|
||||
iio_trigger_poll_nested(indio_dev->trig);
|
||||
clear |= BIT(IRS_INTR_DATA);
|
||||
}
|
||||
|
||||
if (status & BIT(IRS_INTR_COUNT_THR_OR) &&
|
||||
source & BIT(IRS_INTR_COUNT_THR_OR)) {
|
||||
/*
|
||||
* The register value resets to zero after reading. We therefore
|
||||
* need to read once and manually extract the lower and upper
|
||||
* count register fields.
|
||||
*/
|
||||
ret = regmap_read(data->regmap, IRS_REG_COUNT, &count);
|
||||
if (ret)
|
||||
dev_err(data->dev, "Could not read count (%d)\n", ret);
|
||||
|
||||
upper_count = IRS_UPPER_COUNT(count);
|
||||
lower_count = IRS_LOWER_COUNT(count);
|
||||
|
||||
/*
|
||||
* We only check the OR mode to be able to push events for
|
||||
* rising and falling thresholds. AND mode is covered when both
|
||||
* upper and lower count is non-zero, and is signaled with
|
||||
* IIO_EV_DIR_EITHER.
|
||||
*/
|
||||
if (upper_count && !lower_count)
|
||||
dir = IIO_EV_DIR_RISING;
|
||||
else if (!upper_count && lower_count)
|
||||
dir = IIO_EV_DIR_FALLING;
|
||||
else
|
||||
dir = IIO_EV_DIR_EITHER;
|
||||
|
||||
iio_push_event(indio_dev,
|
||||
IIO_UNMOD_EVENT_CODE(IIO_PROXIMITY, 0,
|
||||
IIO_EV_TYPE_THRESH, dir),
|
||||
iio_get_time_ns(indio_dev));
|
||||
|
||||
/*
|
||||
* The OR mode will always trigger when the AND mode does, but
|
||||
* not vice versa. However, it seems like the AND bit needs to
|
||||
* be cleared if data capture _and_ threshold count interrupts
|
||||
* are desirable, even though it hasn't explicitly been selected
|
||||
* (with IRS_REG_INTR). Either way, it doesn't hurt...
|
||||
*/
|
||||
clear |= BIT(IRS_INTR_COUNT_THR_OR) |
|
||||
BIT(IRS_INTR_COUNT_THR_AND);
|
||||
}
|
||||
|
||||
if (!clear)
|
||||
return IRQ_NONE;
|
||||
|
||||
ret = regmap_write(data->regmap, IRS_REG_STATUS, clear);
|
||||
if (ret)
|
||||
dev_err(data->dev,
|
||||
"Could not clear interrupt status (%d)\n", ret);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static irqreturn_t irsd200_trigger_handler(int irq, void *pollf)
|
||||
{
|
||||
struct iio_dev *indio_dev = ((struct iio_poll_func *)pollf)->indio_dev;
|
||||
struct irsd200_data *data = iio_priv(indio_dev);
|
||||
s16 buf = 0;
|
||||
int ret;
|
||||
|
||||
ret = irsd200_read_data(data, &buf);
|
||||
if (ret)
|
||||
goto end;
|
||||
|
||||
iio_push_to_buffers_with_timestamp(indio_dev, &buf,
|
||||
iio_get_time_ns(indio_dev));
|
||||
|
||||
end:
|
||||
iio_trigger_notify_done(indio_dev->trig);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static int irsd200_set_trigger_state(struct iio_trigger *trig, bool state)
|
||||
{
|
||||
struct irsd200_data *data = iio_trigger_get_drvdata(trig);
|
||||
int ret;
|
||||
|
||||
ret = regmap_field_write(data->regfields[IRS_REGF_INTR_DATA], state);
|
||||
if (ret) {
|
||||
dev_err(data->dev, "Could not %s data interrupt source (%d)\n",
|
||||
state ? "enable" : "disable", ret);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct iio_info irsd200_info = {
|
||||
.read_raw = irsd200_read_raw,
|
||||
.read_avail = irsd200_read_avail,
|
||||
.write_raw = irsd200_write_raw,
|
||||
.read_event_value = irsd200_read_event,
|
||||
.write_event_value = irsd200_write_event,
|
||||
.read_event_config = irsd200_read_event_config,
|
||||
.write_event_config = irsd200_write_event_config,
|
||||
};
|
||||
|
||||
static const struct iio_trigger_ops irsd200_trigger_ops = {
|
||||
.set_trigger_state = irsd200_set_trigger_state,
|
||||
.validate_device = iio_trigger_validate_own_device,
|
||||
};
|
||||
|
||||
static const struct iio_event_spec irsd200_event_spec[] = {
|
||||
{
|
||||
.type = IIO_EV_TYPE_THRESH,
|
||||
.dir = IIO_EV_DIR_RISING,
|
||||
.mask_separate = BIT(IIO_EV_INFO_VALUE),
|
||||
},
|
||||
{
|
||||
.type = IIO_EV_TYPE_THRESH,
|
||||
.dir = IIO_EV_DIR_FALLING,
|
||||
.mask_separate = BIT(IIO_EV_INFO_VALUE),
|
||||
},
|
||||
{
|
||||
.type = IIO_EV_TYPE_THRESH,
|
||||
.dir = IIO_EV_DIR_EITHER,
|
||||
.mask_separate =
|
||||
BIT(IIO_EV_INFO_RUNNING_PERIOD) |
|
||||
BIT(IIO_EV_INFO_RUNNING_COUNT) |
|
||||
BIT(IIO_EV_INFO_ENABLE),
|
||||
},
|
||||
};
|
||||
|
||||
static const struct iio_chan_spec irsd200_channels[] = {
|
||||
{
|
||||
.type = IIO_PROXIMITY,
|
||||
.info_mask_separate =
|
||||
BIT(IIO_CHAN_INFO_RAW) |
|
||||
BIT(IIO_CHAN_INFO_SAMP_FREQ) |
|
||||
BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) |
|
||||
BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY),
|
||||
.info_mask_separate_available =
|
||||
BIT(IIO_CHAN_INFO_SAMP_FREQ) |
|
||||
BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) |
|
||||
BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY),
|
||||
.event_spec = irsd200_event_spec,
|
||||
.num_event_specs = ARRAY_SIZE(irsd200_event_spec),
|
||||
.scan_type = {
|
||||
.sign = 's',
|
||||
.realbits = 16,
|
||||
.storagebits = 16,
|
||||
.endianness = IIO_CPU,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static int irsd200_probe(struct i2c_client *client)
|
||||
{
|
||||
struct iio_trigger *trigger;
|
||||
struct irsd200_data *data;
|
||||
struct iio_dev *indio_dev;
|
||||
size_t i;
|
||||
int ret;
|
||||
|
||||
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
|
||||
if (!indio_dev)
|
||||
return dev_err_probe(&client->dev, -ENOMEM,
|
||||
"Could not allocate iio device\n");
|
||||
|
||||
data = iio_priv(indio_dev);
|
||||
data->dev = &client->dev;
|
||||
|
||||
data->regmap = devm_regmap_init_i2c(client, &irsd200_regmap_config);
|
||||
if (IS_ERR(data->regmap))
|
||||
return dev_err_probe(data->dev, PTR_ERR(data->regmap),
|
||||
"Could not initialize regmap\n");
|
||||
|
||||
for (i = 0; i < IRS_REGF_MAX; ++i) {
|
||||
data->regfields[i] = devm_regmap_field_alloc(
|
||||
data->dev, data->regmap, irsd200_regfields[i]);
|
||||
if (IS_ERR(data->regfields[i]))
|
||||
return dev_err_probe(
|
||||
data->dev, PTR_ERR(data->regfields[i]),
|
||||
"Could not allocate register field %zu\n", i);
|
||||
}
|
||||
|
||||
ret = devm_regulator_get_enable(data->dev, "vdd");
|
||||
if (ret)
|
||||
return dev_err_probe(
|
||||
data->dev, ret,
|
||||
"Could not get and enable regulator (%d)\n", ret);
|
||||
|
||||
ret = irsd200_setup(data);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
indio_dev->info = &irsd200_info;
|
||||
indio_dev->name = IRS_DRV_NAME;
|
||||
indio_dev->channels = irsd200_channels;
|
||||
indio_dev->num_channels = ARRAY_SIZE(irsd200_channels);
|
||||
indio_dev->modes = INDIO_DIRECT_MODE;
|
||||
|
||||
if (!client->irq)
|
||||
return dev_err_probe(data->dev, -ENXIO, "No irq available\n");
|
||||
|
||||
ret = devm_iio_triggered_buffer_setup(data->dev, indio_dev, NULL,
|
||||
irsd200_trigger_handler, NULL);
|
||||
if (ret)
|
||||
return dev_err_probe(
|
||||
data->dev, ret,
|
||||
"Could not setup iio triggered buffer (%d)\n", ret);
|
||||
|
||||
ret = devm_request_threaded_irq(data->dev, client->irq, NULL,
|
||||
irsd200_irq_thread,
|
||||
IRQF_TRIGGER_RISING | IRQF_ONESHOT,
|
||||
NULL, indio_dev);
|
||||
if (ret)
|
||||
return dev_err_probe(data->dev, ret,
|
||||
"Could not request irq (%d)\n", ret);
|
||||
|
||||
trigger = devm_iio_trigger_alloc(data->dev, "%s-dev%d", indio_dev->name,
|
||||
iio_device_id(indio_dev));
|
||||
if (!trigger)
|
||||
return dev_err_probe(data->dev, -ENOMEM,
|
||||
"Could not allocate iio trigger\n");
|
||||
|
||||
trigger->ops = &irsd200_trigger_ops;
|
||||
iio_trigger_set_drvdata(trigger, data);
|
||||
|
||||
ret = devm_iio_trigger_register(data->dev, trigger);
|
||||
if (ret)
|
||||
return dev_err_probe(data->dev, ret,
|
||||
"Could not register iio trigger (%d)\n",
|
||||
ret);
|
||||
|
||||
ret = devm_iio_device_register(data->dev, indio_dev);
|
||||
if (ret)
|
||||
return dev_err_probe(data->dev, ret,
|
||||
"Could not register iio device (%d)\n",
|
||||
ret);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id irsd200_of_match[] = {
|
||||
{
|
||||
.compatible = "murata,irsd200",
|
||||
},
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, irsd200_of_match);
|
||||
|
||||
static struct i2c_driver irsd200_driver = {
|
||||
.driver = {
|
||||
.name = IRS_DRV_NAME,
|
||||
.of_match_table = irsd200_of_match,
|
||||
},
|
||||
.probe = irsd200_probe,
|
||||
};
|
||||
module_i2c_driver(irsd200_driver);
|
||||
|
||||
MODULE_AUTHOR("Waqar Hameed <waqar.hameed@axis.com>");
|
||||
MODULE_DESCRIPTION("Murata IRS-D200 PIR sensor driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
Loading…
Reference in New Issue
Block a user