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usb: dwc2: Add platform specific data for Intel's Agilex

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The DWC2 IP on the Agilex platform does not support clock-gating.

Acked-by: Minas Harutyunyan <Minas.Harutyunyan@synopsys.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Link: https://lore.kernel.org/r/20220125161821.1951906-2-dinguyen@kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Dinh Nguyen 2022-01-25 10:18:20 -06:00 committed by Greg Kroah-Hartman
parent 56f26f177b
commit 3d8d3504d2
1 changed files with 10 additions and 0 deletions
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10
drivers/usb/dwc2/params.c
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@ -82,6 +82,14 @@ static void dwc2_set_s3c6400_params(struct dwc2_hsotg *hsotg)
p->phy_utmi_width = 8;
}
static void dwc2_set_socfpga_agilex_params(struct dwc2_hsotg *hsotg)
{
struct dwc2_core_params *p = &hsotg->params;
p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
p->no_clock_gating = true;
}
static void dwc2_set_rk_params(struct dwc2_hsotg *hsotg)
{
struct dwc2_core_params *p = &hsotg->params;
@ -239,6 +247,8 @@ const struct of_device_id dwc2_of_match_table[] = {
.data = dwc2_set_stm32mp15_fsotg_params },
{ .compatible = "st,stm32mp15-hsotg",
.data = dwc2_set_stm32mp15_hsotg_params },
{ .compatible = "intel,socfpga-agilex-hsotg",
.data = dwc2_set_socfpga_agilex_params },
{},
};
MODULE_DEVICE_TABLE(of, dwc2_of_match_table);