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ASoC: Intel: sof-rt5682: support bclk as PLL source on rt5682s

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For rt5682s codec, we could use bclk as PLL source when the frequency
is 3.072MHz but no 2.4MHz. Update the code to select correct pll_id
and clk_id for 3.072MHz bclk.

Reviewed-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Signed-off-by: Brent Lu <brent.lu@intel.com>
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Link: https://lore.kernel.org/r/20240426152529.38345-24-pierre-louis.bossart@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Brent Lu 2024-04-26 10:25:29 -05:00 committed by Mark Brown
parent 4524b1e3ef
commit 3d84e07025
No known key found for this signature in database
GPG Key ID: 24D68B725D5487D0
1 changed files with 13 additions and 8 deletions
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21
sound/soc/intel/boards/sof_rt5682.c
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@ -355,18 +355,23 @@ static int sof_rt5682_hw_params(struct snd_pcm_substream *substream,
clk_id = RT5682_SCLK_S_PLL1;
break;
case CODEC_RT5682S:
/*
* For MCLK = 24.576MHz and sample rate = 96KHz case, use PLL1 We don't test
* pll_out or params_rate() here since rt5682s PLL2 doesn't support 24.576MHz
* input, so we have no choice but to use PLL1. Besides, we will not use PLL at
* all if pll_in == pll_out. ex, MCLK = 24.576Mhz and sample rate = 48KHz
*/
if (pll_in == 24576000) {
/* check plla_table and pllb_table in rt5682s.c */
switch (pll_in) {
case 3072000:
case 24576000:
/*
* For MCLK = 24.576MHz and sample rate = 96KHz case, use PLL1 We don't test
* pll_out or params_rate() here since rt5682s PLL2 doesn't support 24.576MHz
* input, so we have no choice but to use PLL1. Besides, we will not use PLL at
* all if pll_in == pll_out. ex, MCLK = 24.576Mhz and sample rate = 48KHz
*/
pll_id = RT5682S_PLL1;
clk_id = RT5682S_SCLK_S_PLL1;
} else {
break;
default:
pll_id = RT5682S_PLL2;
clk_id = RT5682S_SCLK_S_PLL2;
break;
}
break;
default: