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PCI changes for the 3.5 merge window:

Browse Source 
- Host bridge cleanups from Yinghai
   - Disable Bus Master bit on PCI device shutdown (kexec-related)
   - Stratus ftServer fix
   - pci_dev_reset() locking fix
   - IvyBridge graphics erratum workaround
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Merge tag 'pci-for-3.5' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci

Pull PCI changes from Bjorn Helgaas:
 - Host bridge cleanups from Yinghai
 - Disable Bus Master bit on PCI device shutdown (kexec-related)
 - Stratus ftServer fix
 - pci_dev_reset() locking fix
 - IvyBridge graphics erratum workaround

* tag 'pci-for-3.5' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (21 commits)
  microblaze/PCI: fix "io_offset undeclared" error
  x86/PCI: only check for spinlock being held in SMP kernels
  resources: add resource_overlaps()
  PCI: fix uninitialized variable 'cap_mask'
  MAINTAINERS: update PCI git tree and patchwork
  PCI: disable Bus Master on PCI device shutdown
  PCI: work around IvyBridge internal graphics FLR erratum
  x86/PCI: fix unused variable warning in amd_bus.c
  PCI: move mutex locking out of pci_dev_reset function
  PCI: work around Stratus ftServer broken PCIe hierarchy
  x86/PCI: merge pcibios_scan_root() and pci_scan_bus_on_node()
  x86/PCI: dynamically allocate pci_root_info for native host bridge drivers
  x86/PCI: embed pci_sysdata into pci_root_info on ACPI path
  x86/PCI: embed name into pci_root_info struct
  x86/PCI: add host bridge resource release for _CRS path
  x86/PCI: refactor get_current_resources()
  PCI: add host bridge release support
  PCI: add generic device into pci_host_bridge struct
  PCI: rename pci_host_bridge() to find_pci_root_bridge()
  x86/PCI: fix memleak with get_current_resources()
  ...
This commit is contained in:
Linus Torvalds 2012-05-21 16:24:54 -07:00
commit 3bb07f1b73
20 changed files with 447 additions and 310 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
Documentation/kernel-parameters.txt
View File

@ -2161,6 +2161,9 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
on: Turn realloc on
realloc same as realloc=on
noari do not use PCIe ARI.
pcie_scan_all Scan all possible PCIe devices. Otherwise we
only look for one device below a PCIe downstream
port.
pcie_aspm= [PCIE] Forcibly enable or disable PCIe Active State Power
Management.

10
MAINTAINERS
View File

@ -5128,19 +5128,13 @@ F: Documentation/powerpc/eeh-pci-error-recovery.txt
PCI SUBSYSTEM
M: Bjorn Helgaas <bhelgaas@google.com>
L: linux-pci@vger.kernel.org
Q: http://patchwork.kernel.org/project/linux-pci/list/
T: git git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci.git
Q: http://patchwork.ozlabs.org/project/linux-pci/list/
T: git git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/linux.git
S: Supported
F: Documentation/PCI/
F: drivers/pci/
F: include/linux/pci*
PCI HOTPLUG
M: Bjorn Helgaas <bhelgaas@google.com>
L: linux-pci@vger.kernel.org
S: Supported
F: drivers/pci/hotplug
PCMCIA SUBSYSTEM
P: Linux PCMCIA Team
L: linux-pcmcia@lists.infradead.org

1
arch/microblaze/pci/pci-common.c
View File

@ -1422,6 +1422,7 @@ int pcibios_enable_device(struct pci_dev *dev, int mask)
static void __devinit pcibios_setup_phb_resources(struct pci_controller *hose, struct list_head *resources)
{
unsigned long io_offset;
struct resource *res;
int i;

132
arch/x86/pci/acpi.c
View File

@ -9,11 +9,11 @@
struct pci_root_info {
struct acpi_device *bridge;
char *name;
char name[16];
unsigned int res_num;
struct resource *res;
struct list_head *resources;
int busnum;
struct pci_sysdata sd;
};
static bool pci_use_crs = true;
@ -245,13 +245,6 @@ setup_resource(struct acpi_resource *acpi_res, void *data)
return AE_OK;
}
static bool resource_contains(struct resource *res, resource_size_t point)
{
if (res->start <= point && point <= res->end)
return true;
return false;
}
static void coalesce_windows(struct pci_root_info *info, unsigned long type)
{
int i, j;
@ -272,10 +265,7 @@ static void coalesce_windows(struct pci_root_info *info, unsigned long type)
* our resources no longer match the ACPI _CRS, but
* the kernel resource tree doesn't allow overlaps.
*/
if (resource_contains(res1, res2->start) ||
resource_contains(res1, res2->end) ||
resource_contains(res2, res1->start) ||
resource_contains(res2, res1->end)) {
if (resource_overlaps(res1, res2)) {
res1->start = min(res1->start, res2->start);
res1->end = max(res1->end, res2->end);
dev_info(&info->bridge->dev,
@ -287,7 +277,8 @@ static void coalesce_windows(struct pci_root_info *info, unsigned long type)
}
}
static void add_resources(struct pci_root_info *info)
static void add_resources(struct pci_root_info *info,
struct list_head *resources)
{
int i;
struct resource *res, *root, *conflict;
@ -311,53 +302,74 @@ static void add_resources(struct pci_root_info *info)
"ignoring host bridge window %pR (conflicts with %s %pR)\n",
res, conflict->name, conflict);
else
pci_add_resource(info->resources, res);
pci_add_resource(resources, res);
}
}
static void
get_current_resources(struct acpi_device *device, int busnum,
int domain, struct list_head *resources)
static void free_pci_root_info_res(struct pci_root_info *info)
{
struct pci_root_info info;
size_t size;
kfree(info->res);
info->res = NULL;
info->res_num = 0;
}
info.bridge = device;
info.res_num = 0;
info.resources = resources;
acpi_walk_resources(device->handle, METHOD_NAME__CRS, count_resource,
&info);
if (!info.res_num)
return;
static void __release_pci_root_info(struct pci_root_info *info)
{
int i;
struct resource *res;
size = sizeof(*info.res) * info.res_num;
info.res = kmalloc(size, GFP_KERNEL);
if (!info.res)
return;
for (i = 0; i < info->res_num; i++) {
res = &info->res[i];
info.name = kasprintf(GFP_KERNEL, "PCI Bus %04x:%02x", domain, busnum);
if (!info.name)
goto name_alloc_fail;
if (!res->parent)
continue;
info.res_num = 0;
acpi_walk_resources(device->handle, METHOD_NAME__CRS, setup_resource,
&info);
if (!(res->flags & (IORESOURCE_MEM | IORESOURCE_IO)))
continue;
if (pci_use_crs) {
add_resources(&info);
return;
release_resource(res);
}
kfree(info.name);
free_pci_root_info_res(info);
name_alloc_fail:
kfree(info.res);
kfree(info);
}
static void release_pci_root_info(struct pci_host_bridge *bridge)
{
struct pci_root_info *info = bridge->release_data;
__release_pci_root_info(info);
}
static void
probe_pci_root_info(struct pci_root_info *info, struct acpi_device *device,
int busnum, int domain)
{
size_t size;
info->bridge = device;
info->res_num = 0;
acpi_walk_resources(device->handle, METHOD_NAME__CRS, count_resource,
info);
if (!info->res_num)
return;
size = sizeof(*info->res) * info->res_num;
info->res_num = 0;
info->res = kmalloc(size, GFP_KERNEL);
if (!info->res)
return;
sprintf(info->name, "PCI Bus %04x:%02x", domain, busnum);
acpi_walk_resources(device->handle, METHOD_NAME__CRS, setup_resource,
info);
}
struct pci_bus * __devinit pci_acpi_scan_root(struct acpi_pci_root *root)
{
struct acpi_device *device = root->device;
struct pci_root_info *info = NULL;
int domain = root->segment;
int busnum = root->secondary.start;
LIST_HEAD(resources);
@ -389,17 +401,14 @@ struct pci_bus * __devinit pci_acpi_scan_root(struct acpi_pci_root *root)
if (node != -1 && !node_online(node))
node = -1;
/* Allocate per-root-bus (not per bus) arch-specific data.
* TODO: leak; this memory is never freed.
* It's arguable whether it's worth the trouble to care.
*/
sd = kzalloc(sizeof(*sd), GFP_KERNEL);
if (!sd) {
info = kzalloc(sizeof(*info), GFP_KERNEL);
if (!info) {
printk(KERN_WARNING "pci_bus %04x:%02x: "
"ignored (out of memory)\n", domain, busnum);
return NULL;
}
sd = &info->sd;
sd->domain = domain;
sd->node = node;
/*
@ -413,22 +422,32 @@ struct pci_bus * __devinit pci_acpi_scan_root(struct acpi_pci_root *root)
* be replaced by sd.
*/
memcpy(bus->sysdata, sd, sizeof(*sd));
kfree(sd);
kfree(info);
} else {
get_current_resources(device, busnum, domain, &resources);
probe_pci_root_info(info, device, busnum, domain);
/*
* _CRS with no apertures is normal, so only fall back to
* defaults or native bridge info if we're ignoring _CRS.
*/
if (!pci_use_crs)
if (pci_use_crs)
add_resources(info, &resources);
else {
free_pci_root_info_res(info);
x86_pci_root_bus_resources(busnum, &resources);
}
bus = pci_create_root_bus(NULL, busnum, &pci_root_ops, sd,
&resources);
if (bus)
if (bus) {
bus->subordinate = pci_scan_child_bus(bus);
else
pci_set_host_bridge_release(
to_pci_host_bridge(bus->bridge),
release_pci_root_info, info);
} else {
pci_free_resource_list(&resources);
__release_pci_root_info(info);
}
}
/* After the PCI-E bus has been walked and all devices discovered,
@ -445,9 +464,6 @@ struct pci_bus * __devinit pci_acpi_scan_root(struct acpi_pci_root *root)
}
}
if (!bus)
kfree(sd);
if (bus && node != -1) {
#ifdef CONFIG_ACPI_NUMA
if (pxm >= 0)

91
arch/x86/pci/amd_bus.c
View File

@ -32,6 +32,27 @@ static struct pci_hostbridge_probe pci_probes[] __initdata = {
#define RANGE_NUM 16
static struct pci_root_info __init *find_pci_root_info(int node, int link)
{
struct pci_root_info *info;
/* find the position */
list_for_each_entry(info, &pci_root_infos, list)
if (info->node == node && info->link == link)
return info;
return NULL;
}
static void __init set_mp_bus_range_to_node(int min_bus, int max_bus, int node)
{
#ifdef CONFIG_NUMA
int j;
for (j = min_bus; j <= max_bus; j++)
set_mp_bus_to_node(j, node);
#endif
}
/**
* early_fill_mp_bus_to_node()
* called before pcibios_scan_root and pci_scan_bus
@ -41,7 +62,6 @@ static struct pci_hostbridge_probe pci_probes[] __initdata = {
static int __init early_fill_mp_bus_info(void)
{
int i;
int j;
unsigned bus;
unsigned slot;
int node;
@ -50,7 +70,6 @@ static int __init early_fill_mp_bus_info(void)
int def_link;
struct pci_root_info *info;
u32 reg;
struct resource *res;
u64 start;
u64 end;
struct range range[RANGE_NUM];
@ -86,7 +105,6 @@ static int __init early_fill_mp_bus_info(void)
if (!found)
return 0;
pci_root_num = 0;
for (i = 0; i < 4; i++) {
int min_bus;
int max_bus;
@ -99,19 +117,11 @@ static int __init early_fill_mp_bus_info(void)
min_bus = (reg >> 16) & 0xff;
max_bus = (reg >> 24) & 0xff;
node = (reg >> 4) & 0x07;
#ifdef CONFIG_NUMA
for (j = min_bus; j <= max_bus; j++)
set_mp_bus_to_node(j, node);
#endif
set_mp_bus_range_to_node(min_bus, max_bus, node);
link = (reg >> 8) & 0x03;
info = &pci_root_info[pci_root_num];
info->bus_min = min_bus;
info->bus_max = max_bus;
info->node = node;
info->link = link;
info = alloc_pci_root_info(min_bus, max_bus, node, link);
sprintf(info->name, "PCI Bus #%02x", min_bus);
pci_root_num++;
}
/* get the default node and link for left over res */
@ -134,16 +144,10 @@ static int __init early_fill_mp_bus_info(void)
link = (reg >> 4) & 0x03;
end = (reg & 0xfff000) | 0xfff;
/* find the position */
for (j = 0; j < pci_root_num; j++) {
info = &pci_root_info[j];
if (info->node == node && info->link == link)
break;
}
if (j == pci_root_num)
info = find_pci_root_info(node, link);
if (!info)
continue; /* not found */
info = &pci_root_info[j];
printk(KERN_DEBUG "node %d link %d: io port [%llx, %llx]\n",
node, link, start, end);
@ -155,13 +159,8 @@ static int __init early_fill_mp_bus_info(void)
}
/* add left over io port range to def node/link, [0, 0xffff] */
/* find the position */
for (j = 0; j < pci_root_num; j++) {
info = &pci_root_info[j];
if (info->node == def_node && info->link == def_link)
break;
}
if (j < pci_root_num) {
info = &pci_root_info[j];
info = find_pci_root_info(def_node, def_link);
if (info) {
for (i = 0; i < RANGE_NUM; i++) {
if (!range[i].end)
continue;
@ -214,16 +213,10 @@ static int __init early_fill_mp_bus_info(void)
end <<= 8;
end |= 0xffff;
/* find the position */
for (j = 0; j < pci_root_num; j++) {
info = &pci_root_info[j];
if (info->node == node && info->link == link)
break;
}
if (j == pci_root_num)
continue; /* not found */
info = find_pci_root_info(node, link);
info = &pci_root_info[j];
if (!info)
continue;
printk(KERN_DEBUG "node %d link %d: mmio [%llx, %llx]",
node, link, start, end);
@ -291,14 +284,8 @@ static int __init early_fill_mp_bus_info(void)
* add left over mmio range to def node/link ?
* that is tricky, just record range in from start_min to 4G
*/
for (j = 0; j < pci_root_num; j++) {
info = &pci_root_info[j];
if (info->node == def_node && info->link == def_link)
break;
}
if (j < pci_root_num) {
info = &pci_root_info[j];
info = find_pci_root_info(def_node, def_link);
if (info) {
for (i = 0; i < RANGE_NUM; i++) {
if (!range[i].end)
continue;
@ -309,20 +296,16 @@ static int __init early_fill_mp_bus_info(void)
}
}
for (i = 0; i < pci_root_num; i++) {
int res_num;
list_for_each_entry(info, &pci_root_infos, list) {
int busnum;
struct pci_root_res *root_res;
info = &pci_root_info[i];
res_num = info->res_num;
busnum = info->bus_min;
printk(KERN_DEBUG "bus: [%02x, %02x] on node %x link %x\n",
info->bus_min, info->bus_max, info->node, info->link);
for (j = 0; j < res_num; j++) {
res = &info->res[j];
printk(KERN_DEBUG "bus: %02x index %x %pR\n",
busnum, j, res);
}
list_for_each_entry(root_res, &info->resources, list)
printk(KERN_DEBUG "bus: %02x %pR\n",
busnum, &root_res->res);
}
return 0;

12
arch/x86/pci/broadcom_bus.c
View File

@ -22,19 +22,15 @@
static void __init cnb20le_res(u8 bus, u8 slot, u8 func)
{
struct pci_root_info *info;
struct pci_root_res *root_res;
struct resource res;
u16 word1, word2;
u8 fbus, lbus;
int i;
info = &pci_root_info[pci_root_num];
pci_root_num++;
/* read the PCI bus numbers */
fbus = read_pci_config_byte(bus, slot, func, 0x44);
lbus = read_pci_config_byte(bus, slot, func, 0x45);
info->bus_min = fbus;
info->bus_max = lbus;
info = alloc_pci_root_info(fbus, lbus, 0, 0);
/*
* Add the legacy IDE ports on bus 0
@ -86,8 +82,8 @@ static void __init cnb20le_res(u8 bus, u8 slot, u8 func)
res.flags = IORESOURCE_BUS;
printk(KERN_INFO "CNB20LE PCI Host Bridge (domain 0000 %pR)\n", &res);
for (i = 0; i < info->res_num; i++)
printk(KERN_INFO "host bridge window %pR\n", &info->res[i]);
list_for_each_entry(root_res, &info->resources, list)
printk(KERN_INFO "host bridge window %pR\n", &root_res->res);
}
static int __init broadcom_postcore_init(void)

73
arch/x86/pci/bus_numa.c
View File

@ -4,35 +4,38 @@
#include "bus_numa.h"
int pci_root_num;
struct pci_root_info pci_root_info[PCI_ROOT_NR];
LIST_HEAD(pci_root_infos);
static struct pci_root_info *x86_find_pci_root_info(int bus)
{
struct pci_root_info *info;
if (list_empty(&pci_root_infos))
return NULL;
list_for_each_entry(info, &pci_root_infos, list)
if (info->bus_min == bus)
return info;
return NULL;
}
void x86_pci_root_bus_resources(int bus, struct list_head *resources)
{
int i;
int j;
struct pci_root_info *info;
struct pci_root_info *info = x86_find_pci_root_info(bus);
struct pci_root_res *root_res;
if (!pci_root_num)
goto default_resources;
for (i = 0; i < pci_root_num; i++) {
if (pci_root_info[i].bus_min == bus)
break;
}
if (i == pci_root_num)
if (!info)
goto default_resources;
printk(KERN_DEBUG "PCI: root bus %02x: hardware-probed resources\n",
bus);
info = &pci_root_info[i];
for (j = 0; j < info->res_num; j++) {
list_for_each_entry(root_res, &info->resources, list) {
struct resource *res;
struct resource *root;
res = &info->res[j];
res = &root_res->res;
pci_add_resource(resources, res);
if (res->flags & IORESOURCE_IO)
root = &ioport_resource;
@ -53,11 +56,32 @@ default_resources:
pci_add_resource(resources, &iomem_resource);
}
struct pci_root_info __init *alloc_pci_root_info(int bus_min, int bus_max,
int node, int link)
{
struct pci_root_info *info;
info = kzalloc(sizeof(*info), GFP_KERNEL);
if (!info)
return info;
INIT_LIST_HEAD(&info->resources);
info->bus_min = bus_min;
info->bus_max = bus_max;
info->node = node;
info->link = link;
list_add_tail(&info->list, &pci_root_infos);
return info;
}
void __devinit update_res(struct pci_root_info *info, resource_size_t start,
resource_size_t end, unsigned long flags, int merge)
{
int i;
struct resource *res;
struct pci_root_res *root_res;
if (start > end)
return;
@ -69,11 +93,11 @@ void __devinit update_res(struct pci_root_info *info, resource_size_t start,
goto addit;
/* try to merge it with old one */
for (i = 0; i < info->res_num; i++) {
list_for_each_entry(root_res, &info->resources, list) {
resource_size_t final_start, final_end;
resource_size_t common_start, common_end;
res = &info->res[i];
res = &root_res->res;
if (res->flags != flags)
continue;
@ -93,14 +117,15 @@ void __devinit update_res(struct pci_root_info *info, resource_size_t start,
addit:
/* need to add that */
if (info->res_num >= RES_NUM)
root_res = kzalloc(sizeof(*root_res), GFP_KERNEL);
if (!root_res)
return;
res = &info->res[info->res_num];
res = &root_res->res;
res->name = info->name;
res->flags = flags;
res->start = start;
res->end = end;
res->child = NULL;
info->res_num++;
list_add_tail(&root_res->list, &info->resources);
}

18
arch/x86/pci/bus_numa.h
View File

@ -4,22 +4,24 @@
* sub bus (transparent) will use entres from 3 to store extra from
* root, so need to make sure we have enough slot there.
*/
#define RES_NUM 16
struct pci_root_res {
struct list_head list;
struct resource res;
};
struct pci_root_info {
struct list_head list;
char name[12];
unsigned int res_num;
struct resource res[RES_NUM];
struct list_head resources;
int bus_min;
int bus_max;
int node;
int link;
};
/* 4 at this time, it may become to 32 */
#define PCI_ROOT_NR 4
extern int pci_root_num;
extern struct pci_root_info pci_root_info[PCI_ROOT_NR];
extern struct list_head pci_root_infos;
struct pci_root_info *alloc_pci_root_info(int bus_min, int bus_max,
int node, int link);
extern void update_res(struct pci_root_info *info, resource_size_t start,
resource_size_t end, unsigned long flags, int merge);
#endif

43
arch/x86/pci/common.c
View File

@ -11,6 +11,7 @@
#include <linux/dmi.h>
#include <linux/slab.h>
#include <asm-generic/pci-bridge.h>
#include <asm/acpi.h>
#include <asm/segment.h>
#include <asm/io.h>
@ -229,6 +230,14 @@ static int __devinit assign_all_busses(const struct dmi_system_id *d)
}
#endif
static int __devinit set_scan_all(const struct dmi_system_id *d)
{
printk(KERN_INFO "PCI: %s detected, enabling pci=pcie_scan_all\n",
d->ident);
pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS);
return 0;
}
static const struct dmi_system_id __devinitconst pciprobe_dmi_table[] = {
#ifdef __i386__
/*
@ -420,6 +429,13 @@ static const struct dmi_system_id __devinitconst pciprobe_dmi_table[] = {
DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant DL585 G2"),
},
},
{
.callback = set_scan_all,
.ident = "Stratus/NEC ftServer",
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "ftServer"),
},
},
{}
};
@ -430,9 +446,7 @@ void __init dmi_check_pciprobe(void)
struct pci_bus * __devinit pcibios_scan_root(int busnum)
{
LIST_HEAD(resources);
struct pci_bus *bus = NULL;
struct pci_sysdata *sd;
while ((bus = pci_find_next_bus(bus)) != NULL) {
if (bus->number == busnum) {
@ -441,28 +455,10 @@ struct pci_bus * __devinit pcibios_scan_root(int busnum)
}
}
/* Allocate per-root-bus (not per bus) arch-specific data.
* TODO: leak; this memory is never freed.
* It's arguable whether it's worth the trouble to care.
*/
sd = kzalloc(sizeof(*sd), GFP_KERNEL);
if (!sd) {
printk(KERN_ERR "PCI: OOM, not probing PCI bus %02x\n", busnum);
return NULL;
}
sd->node = get_mp_bus_to_node(busnum);
printk(KERN_DEBUG "PCI: Probing PCI hardware (bus %02x)\n", busnum);
x86_pci_root_bus_resources(busnum, &resources);
bus = pci_scan_root_bus(NULL, busnum, &pci_root_ops, sd, &resources);
if (!bus) {
pci_free_resource_list(&resources);
kfree(sd);
}
return bus;
return pci_scan_bus_on_node(busnum, &pci_root_ops,
get_mp_bus_to_node(busnum));
}
void __init pcibios_set_cache_line_size(void)
{
struct cpuinfo_x86 *c = &boot_cpu_data;
@ -656,6 +652,7 @@ struct pci_bus * __devinit pci_scan_bus_on_node(int busno, struct pci_ops *ops,
}
sd->node = node;
x86_pci_root_bus_resources(busno, &resources);
printk(KERN_DEBUG "PCI: Probing PCI hardware (bus %02x)\n", busno);
bus = pci_scan_root_bus(NULL, busno, ops, sd, &resources);
if (!bus) {
pci_free_resource_list(&resources);

2
arch/x86/pci/i386.c
View File

@ -57,7 +57,7 @@ static struct pcibios_fwaddrmap *pcibios_fwaddrmap_lookup(struct pci_dev *dev)
{
struct pcibios_fwaddrmap *map;
WARN_ON(!spin_is_locked(&pcibios_fwaddrmap_lock));
WARN_ON_SMP(!spin_is_locked(&pcibios_fwaddrmap_lock));
list_for_each_entry(map, &pcibios_fwaddrmappings, list)
if (map->dev == dev)

2
drivers/pci/Makefile
View File

@ -2,7 +2,7 @@
# Makefile for the PCI bus specific drivers.
#
obj-y += access.o bus.o probe.o remove.o pci.o \
obj-y += access.o bus.o probe.o host-bridge.o remove.o pci.o \
pci-driver.o search.o pci-sysfs.o rom.o setup-res.o \
irq.o vpd.o
obj-$(CONFIG_PROC_FS) += proc.o

96
drivers/pci/host-bridge.c Normal file
View File

@ -0,0 +1,96 @@
/*
* host bridge related code
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/module.h>
#include "pci.h"
static struct pci_bus *find_pci_root_bus(struct pci_dev *dev)
{
struct pci_bus *bus;
bus = dev->bus;
while (bus->parent)
bus = bus->parent;
return bus;
}
static struct pci_host_bridge *find_pci_host_bridge(struct pci_dev *dev)
{
struct pci_bus *bus = find_pci_root_bus(dev);
return to_pci_host_bridge(bus->bridge);
}
void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
void (*release_fn)(struct pci_host_bridge *),
void *release_data)
{
bridge->release_fn = release_fn;
bridge->release_data = release_data;
}
static bool resource_contains(struct resource *res1, struct resource *res2)
{
return res1->start <= res2->start && res1->end >= res2->end;
}
void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
struct resource *res)
{
struct pci_host_bridge *bridge = find_pci_host_bridge(dev);
struct pci_host_bridge_window *window;
resource_size_t offset = 0;
list_for_each_entry(window, &bridge->windows, list) {
if (resource_type(res) != resource_type(window->res))
continue;
if (resource_contains(window->res, res)) {
offset = window->offset;
break;
}
}
region->start = res->start - offset;
region->end = res->end - offset;
}
EXPORT_SYMBOL(pcibios_resource_to_bus);
static bool region_contains(struct pci_bus_region *region1,
struct pci_bus_region *region2)
{
return region1->start <= region2->start && region1->end >= region2->end;
}
void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
struct pci_bus_region *region)
{
struct pci_host_bridge *bridge = find_pci_host_bridge(dev);
struct pci_host_bridge_window *window;
resource_size_t offset = 0;
list_for_each_entry(window, &bridge->windows, list) {
struct pci_bus_region bus_region;
if (resource_type(res) != resource_type(window->res))
continue;
bus_region.start = window->res->start - window->offset;
bus_region.end = window->res->end - window->offset;
if (region_contains(&bus_region, region)) {
offset = window->offset;
break;
}
}
res->start = region->start + offset;
res->end = region->end + offset;
}
EXPORT_SYMBOL(pcibios_bus_to_resource);

6
drivers/pci/pci-driver.c
View File

@ -420,6 +420,12 @@ static void pci_device_shutdown(struct device *dev)
pci_msi_shutdown(pci_dev);
pci_msix_shutdown(pci_dev);
/*
* Turn off Bus Master bit on the device to tell it to not
* continue to do DMA
*/
pci_disable_device(pci_dev);
/*
* Devices may be enabled to wake up by runtime PM, but they need not
* be supposed to wake up the system from its "power off" state (e.g.

30
drivers/pci/pci.c
View File

@ -22,6 +22,7 @@
#include <linux/interrupt.h>
#include <linux/device.h>
#include <linux/pm_runtime.h>
#include <asm-generic/pci-bridge.h>
#include <asm/setup.h>
#include "pci.h"
@ -3164,18 +3165,12 @@ static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
return 0;
}
static int pci_dev_reset(struct pci_dev *dev, int probe)
static int __pci_dev_reset(struct pci_dev *dev, int probe)
{
int rc;
might_sleep();
if (!probe) {
pci_cfg_access_lock(dev);
/* block PM suspend, driver probe, etc. */
device_lock(&dev->dev);
}
rc = pci_dev_specific_reset(dev, probe);
if (rc != -ENOTTY)
goto done;
@ -3194,14 +3189,27 @@ static int pci_dev_reset(struct pci_dev *dev, int probe)
rc = pci_parent_bus_reset(dev, probe);
done:
return rc;
}
static int pci_dev_reset(struct pci_dev *dev, int probe)
{
int rc;
if (!probe) {
pci_cfg_access_lock(dev);
/* block PM suspend, driver probe, etc. */
device_lock(&dev->dev);
}
rc = __pci_dev_reset(dev, probe);
if (!probe) {
device_unlock(&dev->dev);
pci_cfg_access_unlock(dev);
}
return rc;
}
/**
* __pci_reset_function - reset a PCI device function
* @dev: PCI device to reset
@ -3246,7 +3254,7 @@ EXPORT_SYMBOL_GPL(__pci_reset_function);
*/
int __pci_reset_function_locked(struct pci_dev *dev)
{
return pci_dev_reset(dev, 1);
return __pci_dev_reset(dev, 0);
}
EXPORT_SYMBOL_GPL(__pci_reset_function_locked);
@ -3893,6 +3901,8 @@ static int __init pci_setup(char *str)
pcie_bus_config = PCIE_BUS_PERFORMANCE;
} else if (!strncmp(str, "pcie_bus_peer2peer", 18)) {
pcie_bus_config = PCIE_BUS_PEER2PEER;
} else if (!strncmp(str, "pcie_scan_all", 13)) {
pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS);
} else {
printk(KERN_ERR "PCI: Unknown option `%s'\n",
str);

2
drivers/pci/pcie/portdrv_core.c
View File

@ -249,7 +249,7 @@ static int get_port_device_capability(struct pci_dev *dev)
int services = 0, pos;
u16 reg16;
u32 reg32;
int cap_mask;
int cap_mask = 0;
int err;
if (pcie_ports_disabled)

156
drivers/pci/probe.c
View File

@ -10,18 +10,16 @@
#include <linux/module.h>
#include <linux/cpumask.h>
#include <linux/pci-aspm.h>
#include <asm-generic/pci-bridge.h>
#include "pci.h"
#define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
#define CARDBUS_RESERVE_BUSNR 3
static LIST_HEAD(pci_host_bridges);
/* Ugh. Need to stop exporting this to modules. */
LIST_HEAD(pci_root_buses);
EXPORT_SYMBOL(pci_root_buses);
static int find_anything(struct device *dev, void *data)
{
return 1;
@ -44,82 +42,6 @@ int no_pci_devices(void)
}
EXPORT_SYMBOL(no_pci_devices);
static struct pci_host_bridge *pci_host_bridge(struct pci_dev *dev)
{
struct pci_bus *bus;
struct pci_host_bridge *bridge;
bus = dev->bus;
while (bus->parent)
bus = bus->parent;
list_for_each_entry(bridge, &pci_host_bridges, list) {
if (bridge->bus == bus)
return bridge;
}
return NULL;
}
static bool resource_contains(struct resource *res1, struct resource *res2)
{
return res1->start <= res2->start && res1->end >= res2->end;
}
void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
struct resource *res)
{
struct pci_host_bridge *bridge = pci_host_bridge(dev);
struct pci_host_bridge_window *window;
resource_size_t offset = 0;
list_for_each_entry(window, &bridge->windows, list) {
if (resource_type(res) != resource_type(window->res))
continue;
if (resource_contains(window->res, res)) {
offset = window->offset;
break;
}
}
region->start = res->start - offset;
region->end = res->end - offset;
}
EXPORT_SYMBOL(pcibios_resource_to_bus);
static bool region_contains(struct pci_bus_region *region1,
struct pci_bus_region *region2)
{
return region1->start <= region2->start && region1->end >= region2->end;
}
void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
struct pci_bus_region *region)
{
struct pci_host_bridge *bridge = pci_host_bridge(dev);
struct pci_host_bridge_window *window;
struct pci_bus_region bus_region;
resource_size_t offset = 0;
list_for_each_entry(window, &bridge->windows, list) {
if (resource_type(res) != resource_type(window->res))
continue;
bus_region.start = window->res->start - window->offset;
bus_region.end = window->res->end - window->offset;
if (region_contains(&bus_region, region)) {
offset = window->offset;
break;
}
}
res->start = region->start + offset;
res->end = region->end + offset;
}
EXPORT_SYMBOL(pcibios_bus_to_resource);
/*
* PCI Bus Class
*/
@ -501,6 +423,19 @@ static struct pci_bus * pci_alloc_bus(void)
return b;
}
static struct pci_host_bridge *pci_alloc_host_bridge(struct pci_bus *b)
{
struct pci_host_bridge *bridge;
bridge = kzalloc(sizeof(*bridge), GFP_KERNEL);
if (bridge) {
INIT_LIST_HEAD(&bridge->windows);
bridge->bus = b;
}
return bridge;
}
static unsigned char pcix_bus_speed[] = {
PCI_SPEED_UNKNOWN, /* 0 */
PCI_SPEED_66MHz_PCIX, /* 1 */
@ -1201,7 +1136,14 @@ int pci_cfg_space_size(struct pci_dev *dev)
static void pci_release_bus_bridge_dev(struct device *dev)
{
kfree(dev);
struct pci_host_bridge *bridge = to_pci_host_bridge(dev);
if (bridge->release_fn)
bridge->release_fn(bridge);
pci_free_resource_list(&bridge->windows);
kfree(bridge);
}
struct pci_dev *alloc_pci_dev(void)
@ -1395,10 +1337,13 @@ static unsigned no_next_fn(struct pci_dev *dev, unsigned fn)
static int only_one_child(struct pci_bus *bus)
{
struct pci_dev *parent = bus->self;
if (!parent || !pci_is_pcie(parent))
return 0;
if (parent->pcie_type == PCI_EXP_TYPE_ROOT_PORT ||
parent->pcie_type == PCI_EXP_TYPE_DOWNSTREAM)
if (parent->pcie_type == PCI_EXP_TYPE_ROOT_PORT)
return 1;
if (parent->pcie_type == PCI_EXP_TYPE_DOWNSTREAM &&
!pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
return 1;
return 0;
}
@ -1650,28 +1595,19 @@ struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
int error;
struct pci_host_bridge *bridge;
struct pci_bus *b, *b2;
struct device *dev;
struct pci_host_bridge_window *window, *n;
struct resource *res;
resource_size_t offset;
char bus_addr[64];
char *fmt;
bridge = kzalloc(sizeof(*bridge), GFP_KERNEL);
if (!bridge)
return NULL;
b = pci_alloc_bus();
if (!b)
goto err_bus;
dev = kzalloc(sizeof(*dev), GFP_KERNEL);
if (!dev)
goto err_dev;
return NULL;
b->sysdata = sysdata;
b->ops = ops;
b2 = pci_find_bus(pci_domain_nr(b), bus);
if (b2) {
/* If we already got to this bus through a different bridge, ignore it */
@ -1679,13 +1615,17 @@ struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
goto err_out;
}
dev->parent = parent;
dev->release = pci_release_bus_bridge_dev;
dev_set_name(dev, "pci%04x:%02x", pci_domain_nr(b), bus);
error = device_register(dev);
bridge = pci_alloc_host_bridge(b);
if (!bridge)
goto err_out;
bridge->dev.parent = parent;
bridge->dev.release = pci_release_bus_bridge_dev;
dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(b), bus);
error = device_register(&bridge->dev);
if (error)
goto dev_reg_err;
b->bridge = get_device(dev);
goto bridge_dev_reg_err;
b->bridge = get_device(&bridge->dev);
device_enable_async_suspend(b->bridge);
pci_set_bus_of_node(b);
@ -1704,9 +1644,6 @@ struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
b->number = b->secondary = bus;
bridge->bus = b;
INIT_LIST_HEAD(&bridge->windows);
if (parent)
dev_info(parent, "PCI host bridge to bus %s\n", dev_name(&b->dev));
else
@ -1732,25 +1669,18 @@ struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
}
down_write(&pci_bus_sem);
list_add_tail(&bridge->list, &pci_host_bridges);
list_add_tail(&b->node, &pci_root_buses);
up_write(&pci_bus_sem);
return b;
class_dev_reg_err:
device_unregister(dev);
dev_reg_err:
down_write(&pci_bus_sem);
list_del(&bridge->list);
list_del(&b->node);
up_write(&pci_bus_sem);
err_out:
kfree(dev);
err_dev:
kfree(b);
err_bus:
put_device(&bridge->dev);
device_unregister(&bridge->dev);
bridge_dev_reg_err:
kfree(bridge);
err_out:
kfree(b);
return NULL;
}

58
drivers/pci/quirks.c
View File

@ -3097,16 +3097,74 @@ static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe)
return 0;
}
#include "../gpu/drm/i915/i915_reg.h"
#define MSG_CTL 0x45010
#define NSDE_PWR_STATE 0xd0100
#define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */
static int reset_ivb_igd(struct pci_dev *dev, int probe)
{
void __iomem *mmio_base;
unsigned long timeout;
u32 val;
if (probe)
return 0;
mmio_base = pci_iomap(dev, 0, 0);
if (!mmio_base)
return -ENOMEM;
iowrite32(0x00000002, mmio_base + MSG_CTL);
/*
* Clobbering SOUTH_CHICKEN2 register is fine only if the next
* driver loaded sets the right bits. However, this's a reset and
* the bits have been set by i915 previously, so we clobber
* SOUTH_CHICKEN2 register directly here.
*/
iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2);
val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe;
iowrite32(val, mmio_base + PCH_PP_CONTROL);
timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT);
do {
val = ioread32(mmio_base + PCH_PP_STATUS);
if ((val & 0xb0000000) == 0)
goto reset_complete;
msleep(10);
} while (time_before(jiffies, timeout));
dev_warn(&dev->dev, "timeout during reset\n");
reset_complete:
iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE);
pci_iounmap(dev, mmio_base);
return 0;
}
#define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
#define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156
#define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166
static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF,
reset_intel_82599_sfp_virtfn },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA,
reset_ivb_igd },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA,
reset_ivb_igd },
{ PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
reset_intel_generic_dev },
{ 0 }
};
/*
* These device-specific reset methods are here rather than in a driver
* because when a host assigns a device to a guest VM, the host may need
* to reset the device but probably doesn't have a driver for it.
*/
int pci_dev_specific_reset(struct pci_dev *dev, int probe)
{
const struct pci_dev_reset_methods *i;

6
include/asm-generic/pci-bridge.h
View File

@ -30,6 +30,12 @@ enum {
PCI_ENABLE_PROC_DOMAINS = 0x00000010,
/* ... except for domain 0 */
PCI_COMPAT_DOMAIN_0 = 0x00000020,
/* PCIe downstream ports are bridges that normally lead to only a
* device 0, but if this is set, we scan all possible devices, not
* just device 0.
*/
PCI_SCAN_ALL_PCIE_DEVS = 0x00000040,
};
#ifdef CONFIG_PCI

7
include/linux/ioport.h
View File

@ -223,5 +223,12 @@ extern int
walk_system_ram_range(unsigned long start_pfn, unsigned long nr_pages,
void *arg, int (*func)(unsigned long, unsigned long, void *));
/* True if any part of r1 overlaps r2 */
static inline bool resource_overlaps(struct resource *r1, struct resource *r2)
{
return (r1->start <= r2->end && r1->end >= r2->start);
}
#endif /* __ASSEMBLY__ */
#endif /* _LINUX_IOPORT_H */

9
include/linux/pci.h
View File

@ -375,11 +375,18 @@ struct pci_host_bridge_window {
};
struct pci_host_bridge {
struct list_head list;
struct device dev;
struct pci_bus *bus; /* root bus */
struct list_head windows; /* pci_host_bridge_windows */
void (*release_fn)(struct pci_host_bridge *);
void *release_data;
};
#define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
void (*release_fn)(struct pci_host_bridge *),
void *release_data);
/*
* The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
* to P2P or CardBus bridge windows) go in a table. Additional ones (for