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drm/amd/powerplay: add hardware manager sub-component

Browse Source 
The hwmgr handles all hardware related calls, including clock/power
gating control, DPM, read and parse PPTable, etc.

v5: squash in fixes
v4: implement acpi's atcs function use cgs interface
v3: fix code style error and add big-endian mode support.
v2: use cgs interface directly in hwmgr sub-module

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Jammy Zhou 2015-07-21 21:18:15 +08:00 committed by Alex Deucher
parent ac885b3a20
commit 3bace35914
16 changed files with 3439 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/drm/amd/powerplay/Makefile
View File

@ -6,7 +6,7 @@ subdir-ccflags-y += -Iinclude/drm \
AMD_PP_PATH = ../powerplay
PP_LIBS = smumgr
PP_LIBS = smumgr hwmgr
AMD_POWERPLAY = $(addsuffix /Makefile,$(addprefix drivers/gpu/drm/amd/powerplay/,$(PP_LIBS)))

55
drivers/gpu/drm/amd/powerplay/amd_powerplay.c
View File

@ -35,12 +35,46 @@ static int pp_early_init(void *handle)
static int pp_sw_init(void *handle)
{
return 0;
struct pp_instance *pp_handle;
struct pp_hwmgr *hwmgr;
int ret = 0;
if (handle == NULL)
return -EINVAL;
pp_handle = (struct pp_instance *)handle;
hwmgr = pp_handle->hwmgr;
if (hwmgr == NULL || hwmgr->pptable_func == NULL ||
hwmgr->hwmgr_func == NULL ||
hwmgr->pptable_func->pptable_init == NULL ||
hwmgr->hwmgr_func->backend_init == NULL)
return -EINVAL;
ret = hwmgr->pptable_func->pptable_init(hwmgr);
if (ret == 0)
ret = hwmgr->hwmgr_func->backend_init(hwmgr);
return ret;
}
static int pp_sw_fini(void *handle)
{
return 0;
struct pp_instance *pp_handle;
struct pp_hwmgr *hwmgr;
int ret = 0;
if (handle == NULL)
return -EINVAL;
pp_handle = (struct pp_instance *)handle;
hwmgr = pp_handle->hwmgr;
if (hwmgr != NULL || hwmgr->hwmgr_func != NULL ||
hwmgr->hwmgr_func->backend_fini != NULL)
ret = hwmgr->hwmgr_func->backend_fini(hwmgr);
return ret;
}
static int pp_hw_init(void *handle)
@ -72,6 +106,8 @@ static int pp_hw_init(void *handle)
smumgr->smumgr_funcs->smu_fini(smumgr);
return ret;
}
hw_init_power_state_table(pp_handle->hwmgr);
return 0;
}
@ -203,6 +239,7 @@ pp_debugfs_print_current_performance_level(void *handle,
{
return;
}
const struct amd_powerplay_funcs pp_dpm_funcs = {
.get_temperature = NULL,
.load_firmware = pp_dpm_load_fw,
@ -230,10 +267,20 @@ static int amd_pp_instance_init(struct amd_pp_init *pp_init,
ret = smum_init(pp_init, handle);
if (ret)
return ret;
goto fail_smum;
ret = hwmgr_init(pp_init, handle);
if (ret)
goto fail_hwmgr;
amd_pp->pp_handle = handle;
return 0;
fail_hwmgr:
smum_fini(handle->smu_mgr);
fail_smum:
kfree(handle);
return ret;
}
static int amd_pp_instance_fini(void *handle)
@ -242,6 +289,8 @@ static int amd_pp_instance_fini(void *handle)
if (instance == NULL)
return -EINVAL;
hwmgr_fini(instance->hwmgr);
smum_fini(instance->smu_mgr);
kfree(handle);

10
drivers/gpu/drm/amd/powerplay/hwmgr/Makefile Normal file
View File

@ -0,0 +1,10 @@
#
# Makefile for the 'hw manager' sub-component of powerplay.
# It provides the hardware management services for the driver.
HARDWARE_MGR = hwmgr.o processpptables.o functiontables.o \
hardwaremanager.o pp_acpi.o
AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR))
AMD_POWERPLAY_FILES += $(AMD_PP_HWMGR)

154
drivers/gpu/drm/amd/powerplay/hwmgr/functiontables.c Normal file
View File

@ -0,0 +1,154 @@
/*
* Copyright 2015 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include "hwmgr.h"
static int phm_run_table(struct pp_hwmgr *hwmgr,
struct phm_runtime_table_header *rt_table,
void *input,
void *output,
void *temp_storage)
{
int result = 0;
phm_table_function *function;
for (function = rt_table->function_list; NULL != *function; function++) {
int tmp = (*function)(hwmgr, input, output, temp_storage, result);
if (tmp == PP_Result_TableImmediateExit)
break;
if (tmp) {
if (0 == result)
result = tmp;
if (rt_table->exit_error)
break;
}
}
return result;
}
int phm_dispatch_table(struct pp_hwmgr *hwmgr,
struct phm_runtime_table_header *rt_table,
void *input, void *output)
{
int result = 0;
void *temp_storage = NULL;
if (hwmgr == NULL || rt_table == NULL || rt_table->function_list == NULL) {
printk(KERN_ERR "[ powerplay ] Invalid Parameter!\n");
return 0; /*temp return ture because some function not implement on some asic */
}
if (0 != rt_table->storage_size) {
temp_storage = kzalloc(rt_table->storage_size, GFP_KERNEL);
if (temp_storage == NULL) {
printk(KERN_ERR "[ powerplay ] Could not allocate table temporary storage\n");
return -1;
}
}
result = phm_run_table(hwmgr, rt_table, input, output, temp_storage);
if (NULL != temp_storage)
kfree(temp_storage);
return result;
}
int phm_construct_table(struct pp_hwmgr *hwmgr,
struct phm_master_table_header *master_table,
struct phm_runtime_table_header *rt_table)
{
uint32_t function_count = 0;
const struct phm_master_table_item *table_item;
uint32_t size;
phm_table_function *run_time_list;
phm_table_function *rtf;
if (hwmgr == NULL || master_table == NULL || rt_table == NULL) {
printk(KERN_ERR "[ powerplay ] Invalid Parameter!\n");
return -1;
}
for (table_item = master_table->master_list;
NULL != table_item->tableFunction; table_item++) {
if ((NULL == table_item->isFunctionNeededInRuntimeTable) ||
(table_item->isFunctionNeededInRuntimeTable(hwmgr)))
function_count++;
}
size = (function_count + 1) * sizeof(phm_table_function);
run_time_list = kzalloc(size, GFP_KERNEL);
if (NULL == run_time_list)
return -1;
rtf = run_time_list;
for (table_item = master_table->master_list;
NULL != table_item->tableFunction; table_item++) {
if ((rtf - run_time_list) > function_count) {
printk(KERN_ERR "[ powerplay ] Check function results have changed\n");
kfree(run_time_list);
return -1;
}
if ((NULL == table_item->isFunctionNeededInRuntimeTable) ||
(table_item->isFunctionNeededInRuntimeTable(hwmgr))) {
*(rtf++) = table_item->tableFunction;
}
}
if ((rtf - run_time_list) > function_count) {
printk(KERN_ERR "[ powerplay ] Check function results have changed\n");
kfree(run_time_list);
return -1;
}
*rtf = NULL;
rt_table->function_list = run_time_list;
rt_table->exit_error = (0 != (master_table->flags & PHM_MasterTableFlag_ExitOnError));
rt_table->storage_size = master_table->storage_size;
return 0;
}
int phm_destroy_table(struct pp_hwmgr *hwmgr,
struct phm_runtime_table_header *rt_table)
{
if (hwmgr == NULL || rt_table == NULL) {
printk(KERN_ERR "[ powerplay ] Invalid Parameter\n");
return -1;
}
if (NULL == rt_table->function_list)
return 0;
kfree(rt_table->function_list);
rt_table->function_list = NULL;
rt_table->storage_size = 0;
rt_table->exit_error = false;
return 0;
}

84
drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c Normal file
View File

@ -0,0 +1,84 @@
/*
* Copyright 2015 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#include <linux/errno.h>
#include "hwmgr.h"
#include "hardwaremanager.h"
#include "pp_acpi.h"
#include "amd_acpi.h"
void phm_init_dynamic_caps(struct pp_hwmgr *hwmgr)
{
phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableVoltageTransition);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableEngineTransition);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMemoryTransition);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMGClockGating);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMGCGTSSM);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableLSClockGating);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_Force3DClockSupport);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableLightSleep);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMCLS);
phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisablePowerGating);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableDPM);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableSMUUVDHandshake);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_ThermalAutoThrottling);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_NoOD5Support);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UserMaxClockForMultiDisplays);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_VpuRecoveryInProgress);
if (acpi_atcs_functions_supported(hwmgr->device, ATCS_FUNCTION_PCIE_PERFORMANCE_REQUEST) &&
acpi_atcs_functions_supported(hwmgr->device, ATCS_FUNCTION_PCIE_DEVICE_READY_NOTIFICATION))
phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest);
}
int phm_setup_asic(struct pp_hwmgr *hwmgr)
{
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_TablelessHardwareInterface)) {
if (NULL != hwmgr->hwmgr_func->asic_setup)
return hwmgr->hwmgr_func->asic_setup(hwmgr);
} else {
return phm_dispatch_table (hwmgr, &(hwmgr->setup_asic),
NULL, NULL);
}
return 0;
}
int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr)
{
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_TablelessHardwareInterface)) {
if (NULL != hwmgr->hwmgr_func->dynamic_state_management_enable)
return hwmgr->hwmgr_func->dynamic_state_management_enable(hwmgr);
} else {
return phm_dispatch_table (hwmgr,
&(hwmgr->enable_dynamic_state_management),
NULL, NULL);
}
return 0;
}

201
drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c Normal file
View File

@ -0,0 +1,201 @@
/*
* Copyright 2015 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#include "linux/delay.h"
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include "cgs_common.h"
#include "power_state.h"
#include "hwmgr.h"
int hwmgr_init(struct amd_pp_init *pp_init, struct pp_instance *handle)
{
struct pp_hwmgr *hwmgr;
if ((handle == NULL) || (pp_init == NULL))
return -EINVAL;
hwmgr = kzalloc(sizeof(struct pp_hwmgr), GFP_KERNEL);
if (hwmgr == NULL)
return -ENOMEM;
handle->hwmgr = hwmgr;
hwmgr->smumgr = handle->smu_mgr;
hwmgr->device = pp_init->device;
hwmgr->chip_family = pp_init->chip_family;
hwmgr->chip_id = pp_init->chip_id;
hwmgr->hw_revision = pp_init->rev_id;
hwmgr->usec_timeout = AMD_MAX_USEC_TIMEOUT;
hwmgr->power_source = PP_PowerSource_AC;
switch (hwmgr->chip_family) {
default:
return -EINVAL;
}
phm_init_dynamic_caps(hwmgr);
return 0;
}
int hwmgr_fini(struct pp_hwmgr *hwmgr)
{
if (hwmgr == NULL || hwmgr->ps == NULL)
return -EINVAL;
kfree(hwmgr->ps);
kfree(hwmgr);
return 0;
}
int hw_init_power_state_table(struct pp_hwmgr *hwmgr)
{
int result;
unsigned int i;
unsigned int table_entries;
struct pp_power_state *state;
int size;
if (hwmgr->hwmgr_func->get_num_of_pp_table_entries == NULL)
return -EINVAL;
if (hwmgr->hwmgr_func->get_power_state_size == NULL)
return -EINVAL;
hwmgr->num_ps = table_entries = hwmgr->hwmgr_func->get_num_of_pp_table_entries(hwmgr);
hwmgr->ps_size = size = hwmgr->hwmgr_func->get_power_state_size(hwmgr) +
sizeof(struct pp_power_state);
hwmgr->ps = kzalloc(size * table_entries, GFP_KERNEL);
state = hwmgr->ps;
for (i = 0; i < table_entries; i++) {
result = hwmgr->hwmgr_func->get_pp_table_entry(hwmgr, i, state);
if (state->classification.flags & PP_StateClassificationFlag_Boot) {
hwmgr->boot_ps = state;
hwmgr->current_ps = hwmgr->request_ps = state;
}
state->id = i + 1; /* assigned unique num for every power state id */
if (state->classification.flags & PP_StateClassificationFlag_Uvd)
hwmgr->uvd_ps = state;
state = (struct pp_power_state *)((uint64_t)state + size);
}
return 0;
}
/**
* Returns once the part of the register indicated by the mask has
* reached the given value.
*/
int phm_wait_on_register(struct pp_hwmgr *hwmgr, uint32_t index,
uint32_t value, uint32_t mask)
{
uint32_t i;
uint32_t cur_value;
if (hwmgr == NULL || hwmgr->device == NULL) {
printk(KERN_ERR "[ powerplay ] Invalid Hardware Manager!");
return -EINVAL;
}
for (i = 0; i < hwmgr->usec_timeout; i++) {
cur_value = cgs_read_register(hwmgr->device, index);
if ((cur_value & mask) == (value & mask))
break;
udelay(1);
}
/* timeout means wrong logic*/
if (i == hwmgr->usec_timeout)
return -1;
return 0;
}
int phm_wait_for_register_unequal(struct pp_hwmgr *hwmgr,
uint32_t index, uint32_t value, uint32_t mask)
{
uint32_t i;
uint32_t cur_value;
if (hwmgr == NULL || hwmgr->device == NULL) {
printk(KERN_ERR "[ powerplay ] Invalid Hardware Manager!");
return -EINVAL;
}
for (i = 0; i < hwmgr->usec_timeout; i++) {
cur_value = cgs_read_register(hwmgr->device, index);
if ((cur_value & mask) != (value & mask))
break;
udelay(1);
}
/* timeout means wrong logic*/
if (i == hwmgr->usec_timeout)
return -1;
return 0;
}
/**
* Returns once the part of the register indicated by the mask has
* reached the given value.The indirect space is described by giving
* the memory-mapped index of the indirect index register.
*/
void phm_wait_on_indirect_register(struct pp_hwmgr *hwmgr,
uint32_t indirect_port,
uint32_t index,
uint32_t value,
uint32_t mask)
{
if (hwmgr == NULL || hwmgr->device == NULL) {
printk(KERN_ERR "[ powerplay ] Invalid Hardware Manager!");
return;
}
cgs_write_register(hwmgr->device, indirect_port, index);
phm_wait_on_register(hwmgr, indirect_port + 1, mask, value);
}
void phm_wait_for_indirect_register_unequal(struct pp_hwmgr *hwmgr,
uint32_t indirect_port,
uint32_t index,
uint32_t value,
uint32_t mask)
{
if (hwmgr == NULL || hwmgr->device == NULL) {
printk(KERN_ERR "[ powerplay ] Invalid Hardware Manager!");
return;
}
cgs_write_register(hwmgr->device, indirect_port, index);
phm_wait_for_register_unequal(hwmgr, indirect_port + 1,
value, mask);
}

76
drivers/gpu/drm/amd/powerplay/hwmgr/pp_acpi.c Normal file
View File

@ -0,0 +1,76 @@
#include <linux/errno.h>
#include "linux/delay.h"
#include "hwmgr.h"
#include "amd_acpi.h"
bool acpi_atcs_functions_supported(void *device, uint32_t index)
{
int32_t result;
struct atcs_verify_interface output_buf = {0};
int32_t temp_buffer = 1;
result = cgs_call_acpi_method(device, CGS_ACPI_METHOD_ATCS,
ATCS_FUNCTION_VERIFY_INTERFACE,
&temp_buffer,
&output_buf,
1,
sizeof(temp_buffer),
sizeof(output_buf));
return result == 0 ? (output_buf.function_bits & (1 << (index - 1))) != 0 : false;
}
int acpi_pcie_perf_request(void *device, uint8_t perf_req, bool advertise)
{
struct atcs_pref_req_input atcs_input;
struct atcs_pref_req_output atcs_output;
u32 retry = 3;
int result;
struct cgs_system_info info = {0};
if (!acpi_atcs_functions_supported(device, ATCS_FUNCTION_PCIE_PERFORMANCE_REQUEST))
return -EINVAL;
info.size = sizeof(struct cgs_system_info);
info.info_id = CGS_SYSTEM_INFO_ADAPTER_BDF_ID;
result = cgs_query_system_info(device, &info);
if (result != 0)
return -EINVAL;
atcs_input.client_id = (uint16_t)info.value;
atcs_input.size = sizeof(struct atcs_pref_req_input);
atcs_input.valid_flags_mask = ATCS_VALID_FLAGS_MASK;
atcs_input.flags = ATCS_WAIT_FOR_COMPLETION;
if (advertise)
atcs_input.flags |= ATCS_ADVERTISE_CAPS;
atcs_input.req_type = ATCS_PCIE_LINK_SPEED;
atcs_input.perf_req = perf_req;
atcs_output.size = sizeof(struct atcs_pref_req_input);
while (retry--) {
result = cgs_call_acpi_method(device,
CGS_ACPI_METHOD_ATCS,
ATCS_FUNCTION_PCIE_PERFORMANCE_REQUEST,
&atcs_input,
&atcs_output,
0,
sizeof(atcs_input),
sizeof(atcs_output));
if (result != 0)
return -EIO;
switch (atcs_output.ret_val) {
case ATCS_REQUEST_REFUSED:
default:
return -EINVAL;
case ATCS_REQUEST_COMPLETE:
return 0;
case ATCS_REQUEST_IN_PROGRESS:
udelay(10);
break;
}
}
return 0;
}

1661
drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c Normal file
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File diff suppressed because it is too large Load Diff

47
drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.h Normal file
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@ -0,0 +1,47 @@
/*
* Copyright 2015 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
* Interface Functions related to the BIOS PowerPlay Tables.
*
*/
#ifndef PROCESSPPTABLES_H
#define PROCESSPPTABLES_H
struct pp_hwmgr;
struct pp_power_state;
struct pp_hw_power_state;
extern const struct pp_table_func pptable_funcs;
typedef int (*pp_tables_hw_clock_info_callback)(struct pp_hwmgr *hwmgr,
struct pp_hw_power_state *hw_ps,
unsigned int index,
const void *clock_info);
int pp_tables_get_num_of_entries(struct pp_hwmgr *hwmgr,
unsigned long *num_of_entries);
int pp_tables_get_entry(struct pp_hwmgr *hwmgr,
unsigned long entry_index,
struct pp_power_state *ps,
pp_tables_hw_clock_info_callback func);
#endif

1
drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
View File

@ -28,7 +28,6 @@
#include "amd_shared.h"
#include "cgs_common.h"
enum amd_pp_event {
AMD_PP_EVENT_INITIALIZE = 0,
AMD_PP_EVENT_UNINITIALIZE,

280
drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h Normal file
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@ -0,0 +1,280 @@
/*
* Copyright 2015 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef _HARDWARE_MANAGER_H_
#define _HARDWARE_MANAGER_H_
struct pp_hwmgr;
/* Automatic Power State Throttling */
enum PHM_AutoThrottleSource
{
PHM_AutoThrottleSource_Thermal,
PHM_AutoThrottleSource_External
};
typedef enum PHM_AutoThrottleSource PHM_AutoThrottleSource;
enum phm_platform_caps {
PHM_PlatformCaps_AtomBiosPpV1 = 0,
PHM_PlatformCaps_PowerPlaySupport,
PHM_PlatformCaps_ACOverdriveSupport,
PHM_PlatformCaps_BacklightSupport,
PHM_PlatformCaps_ThermalController,
PHM_PlatformCaps_BiosPowerSourceControl,
PHM_PlatformCaps_DisableVoltageTransition,
PHM_PlatformCaps_DisableEngineTransition,
PHM_PlatformCaps_DisableMemoryTransition,
PHM_PlatformCaps_DynamicPowerManagement,
PHM_PlatformCaps_EnableASPML0s,
PHM_PlatformCaps_EnableASPML1,
PHM_PlatformCaps_OD5inACSupport,
PHM_PlatformCaps_OD5inDCSupport,
PHM_PlatformCaps_SoftStateOD5,
PHM_PlatformCaps_NoOD5Support,
PHM_PlatformCaps_ContinuousHardwarePerformanceRange,
PHM_PlatformCaps_ActivityReporting,
PHM_PlatformCaps_EnableBackbias,
PHM_PlatformCaps_OverdriveDisabledByPowerBudget,
PHM_PlatformCaps_ShowPowerBudgetWarning,
PHM_PlatformCaps_PowerBudgetWaiverAvailable,
PHM_PlatformCaps_GFXClockGatingSupport,
PHM_PlatformCaps_MMClockGatingSupport,
PHM_PlatformCaps_AutomaticDCTransition,
PHM_PlatformCaps_GeminiPrimary,
PHM_PlatformCaps_MemorySpreadSpectrumSupport,
PHM_PlatformCaps_EngineSpreadSpectrumSupport,
PHM_PlatformCaps_StepVddc,
PHM_PlatformCaps_DynamicPCIEGen2Support,
PHM_PlatformCaps_SMC,
PHM_PlatformCaps_FaultyInternalThermalReading, /* Internal thermal controller reports faulty temperature value when DAC2 is active */
PHM_PlatformCaps_EnableVoltageControl, /* indicates voltage can be controlled */
PHM_PlatformCaps_EnableSideportControl, /* indicates Sideport can be controlled */
PHM_PlatformCaps_VideoPlaybackEEUNotification, /* indicates EEU notification of video start/stop is required */
PHM_PlatformCaps_TurnOffPll_ASPML1, /* PCIE Turn Off PLL in ASPM L1 */
PHM_PlatformCaps_EnableHTLinkControl, /* indicates HT Link can be controlled by ACPI or CLMC overrided/automated mode. */
PHM_PlatformCaps_PerformanceStateOnly, /* indicates only performance power state to be used on current system. */
PHM_PlatformCaps_ExclusiveModeAlwaysHigh, /* In Exclusive (3D) mode always stay in High state. */
PHM_PlatformCaps_DisableMGClockGating, /* to disable Medium Grain Clock Gating or not */
PHM_PlatformCaps_DisableMGCGTSSM, /* TO disable Medium Grain Clock Gating Shader Complex control */
PHM_PlatformCaps_UVDAlwaysHigh, /* In UVD mode always stay in High state */
PHM_PlatformCaps_DisablePowerGating, /* to disable power gating */
PHM_PlatformCaps_CustomThermalPolicy, /* indicates only performance power state to be used on current system. */
PHM_PlatformCaps_StayInBootState, /* Stay in Boot State, do not do clock/voltage or PCIe Lane and Gen switching (RV7xx and up). */
PHM_PlatformCaps_SMCAllowSeparateSWThermalState, /* SMC use separate SW thermal state, instead of the default SMC thermal policy. */
PHM_PlatformCaps_MultiUVDStateSupport, /* Powerplay state table supports multi UVD states. */
PHM_PlatformCaps_EnableSCLKDeepSleepForUVD, /* With HW ECOs, we don't need to disable SCLK Deep Sleep for UVD state. */
PHM_PlatformCaps_EnableMCUHTLinkControl, /* Enable HT link control by MCU */
PHM_PlatformCaps_ABM, /* ABM support.*/
PHM_PlatformCaps_KongThermalPolicy, /* A thermal policy specific for Kong */
PHM_PlatformCaps_SwitchVDDNB, /* if the users want to switch VDDNB */
PHM_PlatformCaps_ULPS, /* support ULPS mode either through ACPI state or ULPS state */
PHM_PlatformCaps_NativeULPS, /* hardware capable of ULPS state (other than through the ACPI state) */
PHM_PlatformCaps_EnableMVDDControl, /* indicates that memory voltage can be controlled */
PHM_PlatformCaps_ControlVDDCI, /* Control VDDCI separately from VDDC. */
PHM_PlatformCaps_DisableDCODT, /* indicates if DC ODT apply or not */
PHM_PlatformCaps_DynamicACTiming, /* if the SMC dynamically re-programs MC SEQ register values */
PHM_PlatformCaps_EnableThermalIntByGPIO, /* enable throttle control through GPIO */
PHM_PlatformCaps_BootStateOnAlert, /* Go to boot state on alerts, e.g. on an AC->DC transition. */
PHM_PlatformCaps_DontWaitForVBlankOnAlert, /* Do NOT wait for VBLANK during an alert (e.g. AC->DC transition). */
PHM_PlatformCaps_Force3DClockSupport, /* indicates if the platform supports force 3D clock. */
PHM_PlatformCaps_MicrocodeFanControl, /* Fan is controlled by the SMC microcode. */
PHM_PlatformCaps_AdjustUVDPriorityForSP,
PHM_PlatformCaps_DisableLightSleep, /* Light sleep for evergreen family. */
PHM_PlatformCaps_DisableMCLS, /* MC Light sleep */
PHM_PlatformCaps_RegulatorHot, /* Enable throttling on 'regulator hot' events. */
PHM_PlatformCaps_BACO, /* Support Bus Alive Chip Off mode */
PHM_PlatformCaps_DisableDPM, /* Disable DPM, supported from Llano */
PHM_PlatformCaps_DynamicM3Arbiter, /* support dynamically change m3 arbitor parameters */
PHM_PlatformCaps_SclkDeepSleep, /* support sclk deep sleep */
PHM_PlatformCaps_DynamicPatchPowerState, /* this ASIC supports to patch power state dynamically */
PHM_PlatformCaps_ThermalAutoThrottling, /* enabling auto thermal throttling, */
PHM_PlatformCaps_SumoThermalPolicy, /* A thermal policy specific for Sumo */
PHM_PlatformCaps_PCIEPerformanceRequest, /* support to change RC voltage */
PHM_PlatformCaps_BLControlledByGPU, /* support varibright */
PHM_PlatformCaps_PowerContainment, /* support DPM2 power containment (AKA TDP clamping) */
PHM_PlatformCaps_SQRamping, /* support DPM2 SQ power throttle */
PHM_PlatformCaps_CAC, /* support Capacitance * Activity power estimation */
PHM_PlatformCaps_NIChipsets, /* Northern Island and beyond chipsets */
PHM_PlatformCaps_TrinityChipsets, /* Trinity chipset */
PHM_PlatformCaps_EvergreenChipsets, /* Evergreen family chipset */
PHM_PlatformCaps_PowerControl, /* Cayman and beyond chipsets */
PHM_PlatformCaps_DisableLSClockGating, /* to disable Light Sleep control for HDP memories */
PHM_PlatformCaps_BoostState, /* this ASIC supports boost state */
PHM_PlatformCaps_UserMaxClockForMultiDisplays, /* indicates if max memory clock is used for all status when multiple displays are connected */
PHM_PlatformCaps_RegWriteDelay, /* indicates if back to back reg write delay is required */
PHM_PlatformCaps_NonABMSupportInPPLib, /* ABM is not supported in PPLIB, (moved from PPLIB to DAL) */
PHM_PlatformCaps_GFXDynamicMGPowerGating, /* Enable Dynamic MG PowerGating on Trinity */
PHM_PlatformCaps_DisableSMUUVDHandshake, /* Disable SMU UVD Handshake */
PHM_PlatformCaps_DTE, /* Support Digital Temperature Estimation */
PHM_PlatformCaps_W5100Specifc_SmuSkipMsgDTE, /* This is for the feature requested by David B., and Tonny W.*/
PHM_PlatformCaps_UVDPowerGating, /* enable UVD power gating, supported from Llano */
PHM_PlatformCaps_UVDDynamicPowerGating, /* enable UVD Dynamic power gating, supported from UVD5 */
PHM_PlatformCaps_VCEPowerGating, /* Enable VCE power gating, supported for TN and later ASICs */
PHM_PlatformCaps_SamuPowerGating, /* Enable SAMU power gating, supported for KV and later ASICs */
PHM_PlatformCaps_UVDDPM, /* UVD clock DPM */
PHM_PlatformCaps_VCEDPM, /* VCE clock DPM */
PHM_PlatformCaps_SamuDPM, /* SAMU clock DPM */
PHM_PlatformCaps_AcpDPM, /* ACP clock DPM */
PHM_PlatformCaps_SclkDeepSleepAboveLow, /* Enable SCLK Deep Sleep on all DPM states */
PHM_PlatformCaps_DynamicUVDState, /* Dynamic UVD State */
PHM_PlatformCaps_WantSAMClkWithDummyBackEnd, /* Set SAM Clk With Dummy Back End */
PHM_PlatformCaps_WantUVDClkWithDummyBackEnd, /* Set UVD Clk With Dummy Back End */
PHM_PlatformCaps_WantVCEClkWithDummyBackEnd, /* Set VCE Clk With Dummy Back End */
PHM_PlatformCaps_WantACPClkWithDummyBackEnd, /* Set SAM Clk With Dummy Back End */
PHM_PlatformCaps_OD6inACSupport, /* indicates that the ASIC/back end supports OD6 */
PHM_PlatformCaps_OD6inDCSupport, /* indicates that the ASIC/back end supports OD6 in DC */
PHM_PlatformCaps_EnablePlatformPowerManagement, /* indicates that Platform Power Management feature is supported */
PHM_PlatformCaps_SurpriseRemoval, /* indicates that surprise removal feature is requested */
PHM_PlatformCaps_NewCACVoltage, /* indicates new CAC voltage table support */
PHM_PlatformCaps_DBRamping, /* for dI/dT feature */
PHM_PlatformCaps_TDRamping, /* for dI/dT feature */
PHM_PlatformCaps_TCPRamping, /* for dI/dT feature */
PHM_PlatformCaps_EnableSMU7ThermalManagement, /* SMC will manage thermal events */
PHM_PlatformCaps_FPS, /* FPS support */
PHM_PlatformCaps_ACP, /* ACP support */
PHM_PlatformCaps_SclkThrottleLowNotification, /* SCLK Throttle Low Notification */
PHM_PlatformCaps_XDMAEnabled, /* XDMA engine is enabled */
PHM_PlatformCaps_UseDummyBackEnd, /* use dummy back end */
PHM_PlatformCaps_EnableDFSBypass, /* Enable DFS bypass */
PHM_PlatformCaps_VddNBDirectRequest,
PHM_PlatformCaps_PauseMMSessions,
PHM_PlatformCaps_UnTabledHardwareInterface, /* Tableless/direct call hardware interface for CI and newer ASICs */
PHM_PlatformCaps_SMU7, /* indicates that vpuRecoveryBegin without SMU shutdown */
PHM_PlatformCaps_RevertGPIO5Polarity, /* indicates revert GPIO5 plarity table support */
PHM_PlatformCaps_Thermal2GPIO17, /* indicates thermal2GPIO17 table support */
PHM_PlatformCaps_ThermalOutGPIO, /* indicates ThermalOutGPIO support, pin number is assigned by VBIOS */
PHM_PlatformCaps_DisableMclkSwitchingForFrameLock, /* Disable memory clock switch during Framelock */
PHM_PlatformCaps_VRHotGPIOConfigurable, /* indicates VR_HOT GPIO configurable */
PHM_PlatformCaps_TempInversion, /* enable Temp Inversion feature */
PHM_PlatformCaps_IOIC3,
PHM_PlatformCaps_ConnectedStandby,
PHM_PlatformCaps_EVV,
PHM_PlatformCaps_EnableLongIdleBACOSupport,
PHM_PlatformCaps_CombinePCCWithThermalSignal,
PHM_PlatformCaps_DisableUsingActualTemperatureForPowerCalc,
PHM_PlatformCaps_StablePState,
PHM_PlatformCaps_OD6PlusinACSupport,
PHM_PlatformCaps_OD6PlusinDCSupport,
PHM_PlatformCaps_ODThermalLimitUnlock,
PHM_PlatformCaps_ReducePowerLimit,
PHM_PlatformCaps_ODFuzzyFanControlSupport,
PHM_PlatformCaps_GeminiRegulatorFanControlSupport,
PHM_PlatformCaps_ControlVDDGFX,
PHM_PlatformCaps_BBBSupported,
PHM_PlatformCaps_DisableVoltageIsland,
PHM_PlatformCaps_FanSpeedInTableIsRPM,
PHM_PlatformCaps_GFXClockGatingManagedInCAIL,
PHM_PlatformCaps_IcelandULPSSWWorkAround,
PHM_PlatformCaps_FPSEnhancement,
PHM_PlatformCaps_LoadPostProductionFirmware,
PHM_PlatformCaps_VpuRecoveryInProgress,
PHM_PlatformCaps_Falcon_QuickTransition,
PHM_PlatformCaps_AVFS,
PHM_PlatformCaps_ClockStretcher,
PHM_PlatformCaps_TablelessHardwareInterface,
PHM_PlatformCaps_EnableDriverEVV,
PHM_PlatformCaps_Max
};
#define PHM_MAX_NUM_CAPS_BITS_PER_FIELD (sizeof(uint32_t)*8)
/* Number of uint32_t entries used by CAPS table */
#define PHM_MAX_NUM_CAPS_ULONG_ENTRIES \
((PHM_PlatformCaps_Max + ((PHM_MAX_NUM_CAPS_BITS_PER_FIELD) - 1)) / (PHM_MAX_NUM_CAPS_BITS_PER_FIELD))
struct pp_hw_descriptor {
uint32_t hw_caps[PHM_MAX_NUM_CAPS_ULONG_ENTRIES];
};
/* Function for setting a platform cap */
static inline void phm_cap_set(uint32_t *caps,
enum phm_platform_caps c)
{
caps[c / PHM_MAX_NUM_CAPS_BITS_PER_FIELD] |= (1UL <<
(c & (PHM_MAX_NUM_CAPS_BITS_PER_FIELD - 1)));
}
static inline void phm_cap_unset(uint32_t *caps,
enum phm_platform_caps c)
{
caps[c / PHM_MAX_NUM_CAPS_BITS_PER_FIELD] &= ~(1UL << (c & (PHM_MAX_NUM_CAPS_BITS_PER_FIELD - 1)));
}
static inline bool phm_cap_enabled(const uint32_t *caps, enum phm_platform_caps c)
{
return (0 != (caps[c / PHM_MAX_NUM_CAPS_BITS_PER_FIELD] &
(1UL << (c & (PHM_MAX_NUM_CAPS_BITS_PER_FIELD - 1)))));
}
enum phm_clock_Type {
PHM_DispClock = 1,
PHM_SClock,
PHM_MemClock
};
#define MAX_NUM_CLOCKS 16
struct PP_Clocks {
uint32_t engineClock;
uint32_t memoryClock;
uint32_t BusBandwidth;
uint32_t engineClockInSR;
};
struct phm_platform_descriptor {
uint32_t platformCaps[PHM_MAX_NUM_CAPS_ULONG_ENTRIES];
uint32_t vbiosInterruptId;
struct PP_Clocks overdriveLimit;
struct PP_Clocks clockStep;
uint32_t hardwareActivityPerformanceLevels;
uint32_t minimumClocksReductionPercentage;
uint32_t minOverdriveVDDC;
uint32_t maxOverdriveVDDC;
uint32_t overdriveVDDCStep;
uint32_t hardwarePerformanceLevels;
uint16_t powerBudget;
uint32_t TDPLimit;
uint32_t nearTDPLimit;
uint32_t nearTDPLimitAdjusted;
uint32_t SQRampingThreshold;
uint32_t CACLeakage;
uint16_t TDPODLimit;
uint32_t TDPAdjustment;
bool TDPAdjustmentPolarity;
uint16_t LoadLineSlope;
uint32_t VidMinLimit;
uint32_t VidMaxLimit;
uint32_t VidStep;
uint32_t VidAdjustment;
bool VidAdjustmentPolarity;
};
struct phm_clocks {
uint32_t num_of_entries;
uint32_t clock[MAX_NUM_CLOCKS];
};
extern int phm_setup_asic(struct pp_hwmgr *hwmgr);
extern int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr);
extern void phm_init_dynamic_caps(struct pp_hwmgr *hwmgr);
#endif /* _HARDWARE_MANAGER_H_ */

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drivers/gpu/drm/amd/powerplay/inc/hwmgr.h Normal file
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@ -0,0 +1,607 @@
/*
* Copyright 2015 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef _HWMGR_H_
#define _HWMGR_H_
#include "amd_powerplay.h"
#include "pp_instance.h"
#include "hardwaremanager.h"
#include "pp_power_source.h"
struct pp_instance;
struct pp_hwmgr;
struct pp_hw_power_state;
struct pp_power_state;
struct PP_VCEState;
enum PP_Result {
PP_Result_TableImmediateExit = 0x13,
};
#define PCIE_PERF_REQ_REMOVE_REGISTRY 0
#define PCIE_PERF_REQ_FORCE_LOWPOWER 1
#define PCIE_PERF_REQ_GEN1 2
#define PCIE_PERF_REQ_GEN2 3
#define PCIE_PERF_REQ_GEN3 4
enum PHM_BackEnd_Magic {
PHM_Dummy_Magic = 0xAA5555AA,
PHM_RV770_Magic = 0xDCBAABCD,
PHM_Kong_Magic = 0x239478DF,
PHM_NIslands_Magic = 0x736C494E,
PHM_Sumo_Magic = 0x8339FA11,
PHM_SIslands_Magic = 0x369431AC,
PHM_Trinity_Magic = 0x96751873,
PHM_CIslands_Magic = 0x38AC78B0,
PHM_Kv_Magic = 0xDCBBABC0,
PHM_VIslands_Magic = 0x20130307,
PHM_Cz_Magic = 0x67DCBA25
};
enum PP_DAL_POWERLEVEL {
PP_DAL_POWERLEVEL_INVALID = 0,
PP_DAL_POWERLEVEL_ULTRALOW,
PP_DAL_POWERLEVEL_LOW,
PP_DAL_POWERLEVEL_NOMINAL,
PP_DAL_POWERLEVEL_PERFORMANCE,
PP_DAL_POWERLEVEL_0 = PP_DAL_POWERLEVEL_ULTRALOW,
PP_DAL_POWERLEVEL_1 = PP_DAL_POWERLEVEL_LOW,
PP_DAL_POWERLEVEL_2 = PP_DAL_POWERLEVEL_NOMINAL,
PP_DAL_POWERLEVEL_3 = PP_DAL_POWERLEVEL_PERFORMANCE,
PP_DAL_POWERLEVEL_4 = PP_DAL_POWERLEVEL_3+1,
PP_DAL_POWERLEVEL_5 = PP_DAL_POWERLEVEL_4+1,
PP_DAL_POWERLEVEL_6 = PP_DAL_POWERLEVEL_5+1,
PP_DAL_POWERLEVEL_7 = PP_DAL_POWERLEVEL_6+1,
};
#define PHM_PCIE_POWERGATING_TARGET_GFX 0
#define PHM_PCIE_POWERGATING_TARGET_DDI 1
#define PHM_PCIE_POWERGATING_TARGET_PLLCASCADE 2
#define PHM_PCIE_POWERGATING_TARGET_PHY 3
typedef int (*phm_table_function)(struct pp_hwmgr *hwmgr, void *input,
void *output, void *storage, int result);
typedef bool (*phm_check_function)(struct pp_hwmgr *hwmgr);
struct phm_acp_arbiter {
uint32_t acpclk;
};
struct phm_uvd_arbiter {
uint32_t vclk;
uint32_t dclk;
uint32_t vclk_ceiling;
uint32_t dclk_ceiling;
};
struct phm_vce_arbiter {
uint32_t evclk;
uint32_t ecclk;
};
struct phm_gfx_arbiter {
uint32_t sclk;
uint32_t mclk;
uint32_t sclk_over_drive;
uint32_t mclk_over_drive;
uint32_t sclk_threshold;
uint32_t num_cus;
};
/* Entries in the master tables */
struct phm_master_table_item {
phm_check_function isFunctionNeededInRuntimeTable;
phm_table_function tableFunction;
};
enum phm_master_table_flag {
PHM_MasterTableFlag_None = 0,
PHM_MasterTableFlag_ExitOnError = 1,
};
/* The header of the master tables */
struct phm_master_table_header {
uint32_t storage_size;
uint32_t flags;
struct phm_master_table_item *master_list;
};
struct phm_runtime_table_header {
uint32_t storage_size;
bool exit_error;
phm_table_function *function_list;
};
struct phm_clock_array {
uint32_t count;
uint32_t values[1];
};
struct phm_clock_voltage_dependency_record {
uint32_t clk;
uint32_t v;
};
struct phm_vceclock_voltage_dependency_record {
uint32_t ecclk;
uint32_t evclk;
uint32_t v;
};
struct phm_uvdclock_voltage_dependency_record {
uint32_t vclk;
uint32_t dclk;
uint32_t v;
};
struct phm_samuclock_voltage_dependency_record {
uint32_t samclk;
uint32_t v;
};
struct phm_acpclock_voltage_dependency_record {
uint32_t acpclk;
uint32_t v;
};
struct phm_clock_voltage_dependency_table {
uint32_t count; /* Number of entries. */
struct phm_clock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
};
struct phm_phase_shedding_limits_record {
uint32_t Voltage;
uint32_t Sclk;
uint32_t Mclk;
};
extern int phm_dispatch_table(struct pp_hwmgr *hwmgr,
struct phm_runtime_table_header *rt_table,
void *input, void *output);
extern int phm_construct_table(struct pp_hwmgr *hwmgr,
struct phm_master_table_header *master_table,
struct phm_runtime_table_header *rt_table);
extern int phm_destroy_table(struct pp_hwmgr *hwmgr,
struct phm_runtime_table_header *rt_table);
struct phm_uvd_clock_voltage_dependency_record {
uint32_t vclk;
uint32_t dclk;
uint32_t v;
};
struct phm_uvd_clock_voltage_dependency_table {
uint8_t count;
struct phm_uvd_clock_voltage_dependency_record entries[1];
};
struct phm_acp_clock_voltage_dependency_record {
uint32_t acpclk;
uint32_t v;
};
struct phm_acp_clock_voltage_dependency_table {
uint32_t count;
struct phm_acp_clock_voltage_dependency_record entries[1];
};
struct phm_vce_clock_voltage_dependency_record {
uint32_t ecclk;
uint32_t evclk;
uint32_t v;
};
struct phm_phase_shedding_limits_table {
uint32_t count;
struct phm_phase_shedding_limits_record entries[1];
};
struct phm_vceclock_voltage_dependency_table {
uint8_t count; /* Number of entries. */
struct phm_vceclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
};
struct phm_uvdclock_voltage_dependency_table {
uint8_t count; /* Number of entries. */
struct phm_uvdclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
};
struct phm_samuclock_voltage_dependency_table {
uint8_t count; /* Number of entries. */
struct phm_samuclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
};
struct phm_acpclock_voltage_dependency_table {
uint32_t count; /* Number of entries. */
struct phm_acpclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
};
struct phm_vce_clock_voltage_dependency_table {
uint8_t count;
struct phm_vce_clock_voltage_dependency_record entries[1];
};
struct pp_hwmgr_func {
int (*backend_init)(struct pp_hwmgr *hw_mgr);
int (*backend_fini)(struct pp_hwmgr *hw_mgr);
int (*asic_setup)(struct pp_hwmgr *hw_mgr);
int (*get_power_state_size)(struct pp_hwmgr *hw_mgr);
int (*force_dpm_level)(struct pp_hwmgr *hw_mgr, enum amd_dpm_forced_level level);
int (*dynamic_state_management_enable)(struct pp_hwmgr *hw_mgr);
int (*patch_boot_state)(struct pp_hwmgr *hwmgr, struct pp_hw_power_state *hw_ps);
int (*get_pp_table_entry)(struct pp_hwmgr *hwmgr, unsigned long, struct pp_power_state *);
int (*get_num_of_pp_table_entries)(struct pp_hwmgr *hwmgr);
};
struct pp_table_func {
int (*pptable_init)(struct pp_hwmgr *hw_mgr);
int (*pptable_fini)(struct pp_hwmgr *hw_mgr);
int (*pptable_get_number_of_vce_state_table_entries)(struct pp_hwmgr *hw_mgr);
int (*pptable_get_vce_state_table_entry)(
struct pp_hwmgr *hwmgr,
unsigned long i,
struct PP_VCEState *vce_state,
void **clock_info,
unsigned long *flag);
};
union phm_cac_leakage_record {
struct {
uint16_t Vddc; /* in CI, we use it for StdVoltageHiSidd */
uint32_t Leakage; /* in CI, we use it for StdVoltageLoSidd */
};
struct {
uint16_t Vddc1;
uint16_t Vddc2;
uint16_t Vddc3;
};
};
struct phm_cac_leakage_table {
uint32_t count;
union phm_cac_leakage_record entries[1];
};
struct phm_samu_clock_voltage_dependency_record {
uint32_t samclk;
uint32_t v;
};
struct phm_samu_clock_voltage_dependency_table {
uint8_t count;
struct phm_samu_clock_voltage_dependency_record entries[1];
};
struct phm_cac_tdp_table {
uint16_t usTDP;
uint16_t usConfigurableTDP;
uint16_t usTDC;
uint16_t usBatteryPowerLimit;
uint16_t usSmallPowerLimit;
uint16_t usLowCACLeakage;
uint16_t usHighCACLeakage;
uint16_t usMaximumPowerDeliveryLimit;
uint16_t usOperatingTempMinLimit;
uint16_t usOperatingTempMaxLimit;
uint16_t usOperatingTempStep;
uint16_t usOperatingTempHyst;
uint16_t usDefaultTargetOperatingTemp;
uint16_t usTargetOperatingTemp;
uint16_t usPowerTuneDataSetID;
uint16_t usSoftwareShutdownTemp;
uint16_t usClockStretchAmount;
uint16_t usTemperatureLimitHotspot;
uint16_t usTemperatureLimitLiquid1;
uint16_t usTemperatureLimitLiquid2;
uint16_t usTemperatureLimitVrVddc;
uint16_t usTemperatureLimitVrMvdd;
uint16_t usTemperatureLimitPlx;
uint8_t ucLiquid1_I2C_address;
uint8_t ucLiquid2_I2C_address;
uint8_t ucLiquid_I2C_Line;
uint8_t ucVr_I2C_address;
uint8_t ucVr_I2C_Line;
uint8_t ucPlx_I2C_address;
uint8_t ucPlx_I2C_Line;
};
struct phm_ppm_table {
uint8_t ppm_design;
uint16_t cpu_core_number;
uint32_t platform_tdp;
uint32_t small_ac_platform_tdp;
uint32_t platform_tdc;
uint32_t small_ac_platform_tdc;
uint32_t apu_tdp;
uint32_t dgpu_tdp;
uint32_t dgpu_ulv_power;
uint32_t tj_max;
};
struct phm_vq_budgeting_record {
uint32_t ulCUs;
uint32_t ulSustainableSOCPowerLimitLow;
uint32_t ulSustainableSOCPowerLimitHigh;
uint32_t ulMinSclkLow;
uint32_t ulMinSclkHigh;
uint8_t ucDispConfig;
uint32_t ulDClk;
uint32_t ulEClk;
uint32_t ulSustainableSclk;
uint32_t ulSustainableCUs;
};
struct phm_vq_budgeting_table {
uint8_t numEntries;
struct phm_vq_budgeting_record entries[1];
};
struct phm_clock_and_voltage_limits {
uint32_t sclk;
uint32_t mclk;
uint16_t vddc;
uint16_t vddci;
uint16_t vddgfx;
};
struct phm_dynamic_state_info {
struct phm_clock_voltage_dependency_table *vddc_dependency_on_sclk;
struct phm_clock_voltage_dependency_table *vddci_dependency_on_mclk;
struct phm_clock_voltage_dependency_table *vddc_dependency_on_mclk;
struct phm_clock_voltage_dependency_table *mvdd_dependency_on_mclk;
struct phm_clock_voltage_dependency_table *vddc_dep_on_dal_pwrl;
struct phm_clock_array *valid_sclk_values;
struct phm_clock_array *valid_mclk_values;
struct phm_clock_and_voltage_limits max_clock_voltage_on_dc;
struct phm_clock_and_voltage_limits max_clock_voltage_on_ac;
uint32_t mclk_sclk_ratio;
uint32_t sclk_mclk_delta;
uint32_t vddc_vddci_delta;
uint32_t min_vddc_for_pcie_gen2;
struct phm_cac_leakage_table *cac_leakage_table;
struct phm_phase_shedding_limits_table *vddc_phase_shed_limits_table;
struct phm_vce_clock_voltage_dependency_table
*vce_clocl_voltage_dependency_table;
struct phm_uvd_clock_voltage_dependency_table
*uvd_clocl_voltage_dependency_table;
struct phm_acp_clock_voltage_dependency_table
*acp_clock_voltage_dependency_table;
struct phm_samu_clock_voltage_dependency_table
*samu_clock_voltage_dependency_table;
struct phm_ppm_table *ppm_parameter_table;
struct phm_cac_tdp_table *cac_dtp_table;
struct phm_clock_voltage_dependency_table *vdd_gfx_dependency_on_sclk;
struct phm_vq_budgeting_table *vq_budgeting_table;
};
struct pp_hwmgr {
uint32_t chip_family;
uint32_t chip_id;
uint32_t hw_revision;
uint32_t sub_sys_id;
uint32_t sub_vendor_id;
void *device;
struct pp_smumgr *smumgr;
const void *soft_pp_table;
enum amd_dpm_forced_level dpm_level;
struct phm_gfx_arbiter gfx_arbiter;
struct phm_acp_arbiter acp_arbiter;
struct phm_uvd_arbiter uvd_arbiter;
struct phm_vce_arbiter vce_arbiter;
uint32_t usec_timeout;
void *pptable;
struct phm_platform_descriptor platform_descriptor;
void *backend;
enum PP_DAL_POWERLEVEL dal_power_level;
struct phm_dynamic_state_info dyn_state;
struct phm_runtime_table_header setup_asic;
struct phm_runtime_table_header disable_dynamic_state_management;
struct phm_runtime_table_header enable_dynamic_state_management;
const struct pp_hwmgr_func *hwmgr_func;
const struct pp_table_func *pptable_func;
struct pp_power_state *ps;
enum pp_power_source power_source;
uint32_t num_ps;
uint32_t ps_size;
struct pp_power_state *current_ps;
struct pp_power_state *request_ps;
struct pp_power_state *boot_ps;
struct pp_power_state *uvd_ps;
};
extern int hwmgr_init(struct amd_pp_init *pp_init,
struct pp_instance *handle);
extern int hwmgr_fini(struct pp_hwmgr *hwmgr);
extern int hw_init_power_state_table(struct pp_hwmgr *hwmgr);
extern int phm_wait_on_register(struct pp_hwmgr *hwmgr, uint32_t index,
uint32_t value, uint32_t mask);
extern int phm_wait_for_register_unequal(struct pp_hwmgr *hwmgr,
uint32_t index, uint32_t value, uint32_t mask);
extern void phm_wait_on_indirect_register(struct pp_hwmgr *hwmgr,
uint32_t indirect_port,
uint32_t index,
uint32_t value,
uint32_t mask);
extern void phm_wait_for_indirect_register_unequal(
struct pp_hwmgr *hwmgr,
uint32_t indirect_port,
uint32_t index,
uint32_t value,
uint32_t mask);
#define PHM_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
#define PHM_FIELD_MASK(reg, field) reg##__##field##_MASK
#define PHM_SET_FIELD(origval, reg, field, fieldval) \
(((origval) & ~PHM_FIELD_MASK(reg, field)) | \
(PHM_FIELD_MASK(reg, field) & ((fieldval) << PHM_FIELD_SHIFT(reg, field))))
#define PHM_GET_FIELD(value, reg, field) \
(((value) & PHM_FIELD_MASK(reg, field)) >> \
PHM_FIELD_SHIFT(reg, field))
#define PHM_WAIT_REGISTER_GIVEN_INDEX(hwmgr, index, value, mask) \
phm_wait_on_register(hwmgr, index, value, mask)
#define PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, index, value, mask) \
phm_wait_for_register_unequal(hwmgr, index, value, mask)
#define PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, index, value, mask) \
phm_wait_on_indirect_register(hwmgr, mm##port##_INDEX, index, value, mask)
#define PHM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, index, value, mask) \
phm_wait_for_indirect_register_unequal(hwmgr, mm##port##_INDEX, index, value, mask)
#define PHM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, index, value, mask) \
phm_wait_on_indirect_register(hwmgr, mm##port##_INDEX_0, index, value, mask)
#define PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, index, value, mask) \
phm_wait_for_indirect_register_unequal(hwmgr, mm##port##_INDEX_0, index, value, mask)
/* Operations on named registers. */
#define PHM_WAIT_REGISTER(hwmgr, reg, value, mask) \
PHM_WAIT_REGISTER_GIVEN_INDEX(hwmgr, mm##reg, value, mask)
#define PHM_WAIT_REGISTER_UNEQUAL(hwmgr, reg, value, mask) \
PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, mm##reg, value, mask)
#define PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, value, mask) \
PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
#define PHM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask) \
PHM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
#define PHM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg, value, mask) \
PHM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
#define PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask) \
PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
/* Operations on named fields. */
#define PHM_READ_FIELD(device, reg, field) \
PHM_GET_FIELD(cgs_read_register(device, mm##reg), reg, field)
#define PHM_READ_INDIRECT_FIELD(device, port, reg, field) \
PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
reg, field)
#define PHM_READ_VFPF_INDIRECT_FIELD(device, port, reg, field) \
PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
reg, field)
#define PHM_WRITE_FIELD(device, reg, field, fieldval) \
cgs_write_register(device, mm##reg, PHM_SET_FIELD( \
cgs_read_register(device, mm##reg), reg, field, fieldval))
#define PHM_WRITE_INDIRECT_FIELD(device, port, reg, field, fieldval) \
cgs_write_ind_register(device, port, ix##reg, \
PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
reg, field, fieldval))
#define PHM_WRITE_VFPF_INDIRECT_FIELD(device, port, reg, field, fieldval) \
cgs_write_ind_register(device, port, ix##reg, \
PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
reg, field, fieldval))
#define PHM_WAIT_FIELD(hwmgr, reg, field, fieldval) \
PHM_WAIT_REGISTER(hwmgr, reg, (fieldval) \
<< PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
#define PHM_WAIT_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval) \
PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, (fieldval) \
<< PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
#define PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval) \
PHM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg, (fieldval) \
<< PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
#define PHM_WAIT_FIELD_UNEQUAL(hwmgr, reg, field, fieldval) \
PHM_WAIT_REGISTER_UNEQUAL(hwmgr, reg, (fieldval) \
<< PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
#define PHM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, port, reg, field, fieldval) \
PHM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, (fieldval) \
<< PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
#define PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, port, reg, field, fieldval) \
PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, (fieldval) \
<< PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
/* Operations on arrays of registers & fields. */
#define PHM_READ_ARRAY_REGISTER(device, reg, offset) \
cgs_read_register(device, mm##reg + (offset))
#define PHM_WRITE_ARRAY_REGISTER(device, reg, offset, value) \
cgs_write_register(device, mm##reg + (offset), value)
#define PHM_WAIT_ARRAY_REGISTER(hwmgr, reg, offset, value, mask) \
PHM_WAIT_REGISTER_GIVEN_INDEX(hwmgr, mm##reg + (offset), value, mask)
#define PHM_WAIT_ARRAY_REGISTER_UNEQUAL(hwmgr, reg, offset, value, mask) \
PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, mm##reg + (offset), value, mask)
#define PHM_READ_ARRAY_FIELD(hwmgr, reg, offset, field) \
PHM_GET_FIELD(PHM_READ_ARRAY_REGISTER(hwmgr->device, reg, offset), reg, field)
#define PHM_WRITE_ARRAY_FIELD(hwmgr, reg, offset, field, fieldvalue) \
PHM_WRITE_ARRAY_REGISTER(hwmgr->device, reg, offset, \
PHM_SET_FIELD(PHM_READ_ARRAY_REGISTER(hwmgr->device, reg, offset), \
reg, field, fieldvalue))
#define PHM_WAIT_ARRAY_FIELD(hwmgr, reg, offset, field, fieldvalue) \
PHM_WAIT_REGISTER_GIVEN_INDEX(hwmgr, mm##reg + (offset), \
(fieldvalue) << PHM_FIELD_SHIFT(reg, field), \
PHM_FIELD_MASK(reg, field))
#define PHM_WAIT_ARRAY_FIELD_UNEQUAL(hwmgr, reg, offset, field, fieldvalue) \
PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, mm##reg + (offset), \
(fieldvalue) << PHM_FIELD_SHIFT(reg, field), \
PHM_FIELD_MASK(reg, field))
#endif /* _HWMGR_H_ */

200
drivers/gpu/drm/amd/powerplay/inc/power_state.h Normal file
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@ -0,0 +1,200 @@
/*
* Copyright 2015 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef PP_POWERSTATE_H
#define PP_POWERSTATE_H
struct pp_hw_power_state {
unsigned int magic;
};
struct pp_power_state;
#define PP_INVALID_POWER_STATE_ID (0)
/*
* An item of a list containing Power States.
*/
struct PP_StateLinkedList {
struct pp_power_state *next;
struct pp_power_state *prev;
};
enum PP_StateUILabel {
PP_StateUILabel_None,
PP_StateUILabel_Battery,
PP_StateUILabel_MiddleLow,
PP_StateUILabel_Balanced,
PP_StateUILabel_MiddleHigh,
PP_StateUILabel_Performance,
PP_StateUILabel_BACO
};
enum PP_StateClassificationFlag {
PP_StateClassificationFlag_Boot = 0x0001,
PP_StateClassificationFlag_Thermal = 0x0002,
PP_StateClassificationFlag_LimitedPowerSource = 0x0004,
PP_StateClassificationFlag_Rest = 0x0008,
PP_StateClassificationFlag_Forced = 0x0010,
PP_StateClassificationFlag_User3DPerformance = 0x0020,
PP_StateClassificationFlag_User2DPerformance = 0x0040,
PP_StateClassificationFlag_3DPerformance = 0x0080,
PP_StateClassificationFlag_ACOverdriveTemplate = 0x0100,
PP_StateClassificationFlag_Uvd = 0x0200,
PP_StateClassificationFlag_3DPerformanceLow = 0x0400,
PP_StateClassificationFlag_ACPI = 0x0800,
PP_StateClassificationFlag_HD2 = 0x1000,
PP_StateClassificationFlag_UvdHD = 0x2000,
PP_StateClassificationFlag_UvdSD = 0x4000,
PP_StateClassificationFlag_UserDCPerformance = 0x8000,
PP_StateClassificationFlag_DCOverdriveTemplate = 0x10000,
PP_StateClassificationFlag_BACO = 0x20000,
PP_StateClassificationFlag_LimitedPowerSource_2 = 0x40000,
PP_StateClassificationFlag_ULV = 0x80000,
PP_StateClassificationFlag_UvdMVC = 0x100000,
};
typedef unsigned int PP_StateClassificationFlags;
struct PP_StateClassificationBlock {
enum PP_StateUILabel ui_label;
enum PP_StateClassificationFlag flags;
int bios_index;
bool temporary_state;
bool to_be_deleted;
};
struct PP_StatePcieBlock {
unsigned int lanes;
};
enum PP_RefreshrateSource {
PP_RefreshrateSource_EDID,
PP_RefreshrateSource_Explicit
};
struct PP_StateDisplayBlock {
bool disableFrameModulation;
bool limitRefreshrate;
enum PP_RefreshrateSource refreshrateSource;
int explicitRefreshrate;
int edidRefreshrateIndex;
bool enableVariBright;
};
struct PP_StateMemroyBlock {
bool dllOff;
uint8_t m3arb;
uint8_t unused[3];
};
struct PP_StateSoftwareAlgorithmBlock {
bool disableLoadBalancing;
bool enableSleepForTimestamps;
};
#define PP_TEMPERATURE_UNITS_PER_CENTIGRADES 1000
/**
* Type to hold a temperature range.
*/
struct PP_TemperatureRange {
uint16_t min;
uint16_t max;
};
struct PP_StateValidationBlock {
bool singleDisplayOnly;
bool disallowOnDC;
uint8_t supportedPowerLevels;
};
struct PP_UVD_CLOCKS {
uint32_t VCLK;
uint32_t DCLK;
};
/**
* Structure to hold a PowerPlay Power State.
*/
struct pp_power_state {
uint32_t id;
struct PP_StateLinkedList orderedList;
struct PP_StateLinkedList allStatesList;
struct PP_StateClassificationBlock classification;
struct PP_StateValidationBlock validation;
struct PP_StatePcieBlock pcie;
struct PP_StateDisplayBlock display;
struct PP_StateMemroyBlock memory;
struct PP_TemperatureRange temperatures;
struct PP_StateSoftwareAlgorithmBlock software;
struct PP_UVD_CLOCKS uvd_clocks;
struct pp_hw_power_state hardware;
};
/*Structure to hold a VCE state entry*/
struct PP_VCEState {
uint32_t evclk;
uint32_t ecclk;
uint32_t sclk;
uint32_t mclk;
};
enum PP_MMProfilingState {
PP_MMProfilingState_NA = 0,
PP_MMProfilingState_Started,
PP_MMProfilingState_Stopped
};
struct PP_Clock_Engine_Request {
unsigned long clientType;
unsigned long ctxid;
uint64_t context_handle;
unsigned long sclk;
unsigned long sclkHardMin;
unsigned long mclk;
unsigned long iclk;
unsigned long evclk;
unsigned long ecclk;
unsigned long ecclkHardMin;
unsigned long vclk;
unsigned long dclk;
unsigned long samclk;
unsigned long acpclk;
unsigned long sclkOverdrive;
unsigned long mclkOverdrive;
unsigned long sclk_threshold;
unsigned long flag;
unsigned long vclk_ceiling;
unsigned long dclk_ceiling;
unsigned long num_cus;
unsigned long pmflag;
enum PP_MMProfilingState MMProfilingState;
};
#endif

28
drivers/gpu/drm/amd/powerplay/inc/pp_acpi.h Normal file
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/*
* Copyright 2015 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
extern bool acpi_atcs_functions_supported(void *device,
uint32_t index);
extern int acpi_pcie_perf_request(void *device,
uint8_t perf_req,
bool advertise);

3
drivers/gpu/drm/amd/powerplay/inc/pp_instance.h
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@ -24,10 +24,11 @@
#define _PP_INSTANCE_H_
#include "smumgr.h"
#include "hwmgr.h"
struct pp_instance {
struct pp_smumgr *smu_mgr;
struct pp_hwmgr *hwmgr;
};
#endif

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drivers/gpu/drm/amd/powerplay/inc/pp_power_source.h Normal file
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/*
* Copyright 2015 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef PP_POWERSOURCE_H
#define PP_POWERSOURCE_H
enum pp_power_source {
PP_PowerSource_AC = 0,
PP_PowerSource_DC,
PP_PowerSource_LimitedPower,
PP_PowerSource_LimitedPower_2,
PP_PowerSource_Max
};
#endif