mirror of
https://github.com/torvalds/linux.git
synced 2024-10-23 05:30:55 +00:00
Samsung DTS ARM64 changes for v6.12
1. Exynos7885: Correct amount of RAM on Samsung Galaxy A8.
2. ExynosAutov9: Add new DPUM clock controller and DPUM IOMMU (SysMMU).
3. ExynosAutov920: Add initial (incomplete) clock controllers: TOP and
PERIC0 controllers.
4. Google GS101: Add reboot and poweroff support.
5. Add binding headers with clock IDs for several devices, used by the
DTS.
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Merge tag 'samsung-dt64-6.12' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt
Samsung DTS ARM64 changes for v6.12
1. Exynos7885: Correct amount of RAM on Samsung Galaxy A8.
2. ExynosAutov9: Add new DPUM clock controller and DPUM IOMMU (SysMMU).
3. ExynosAutov920: Add initial (incomplete) clock controllers: TOP and
PERIC0 controllers.
4. Google GS101: Add reboot and poweroff support.
5. Add binding headers with clock IDs for several devices, used by the
DTS.
* tag 'samsung-dt64-6.12' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
arm64: dts: exynosautov920: add initial CMU clock nodes in ExynosAuto v920
dt-bindings: clock: add ExynosAuto v920 SoC CMU bindings
arm64: dts: exynosautov9: Add dpum SysMMU
arm64: dts: exynosautov9: add dpum clock DT nodes
dt-bindings: clock: exynosautov9: add dpum clock
dt-bindings: clock: exynos7885: Add indices for USB clocks
dt-bindings: clock: exynos7885: Add CMU_TOP PLL MUX indices
dt-bindings: clock: exynos7885: Fix duplicated binding
dt-bindings: clock: exynos850: Add TMU clock
arm64: dts: exynos: gs101: add syscon-poweroff and syscon-reboot nodes
arm64: dts: exynos: exynos7885-jackpotlte: Correct RAM amount to 4GB
Link: https://lore.kernel.org/r/20240827121638.29707-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
3b8b1ff762
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|
@ -35,6 +35,7 @@ properties:
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|||
- samsung,exynosautov9-cmu-top
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- samsung,exynosautov9-cmu-busmc
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- samsung,exynosautov9-cmu-core
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||||
- samsung,exynosautov9-cmu-dpum
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||||
- samsung,exynosautov9-cmu-fsys0
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||||
- samsung,exynosautov9-cmu-fsys1
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- samsung,exynosautov9-cmu-fsys2
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||||
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@ -109,6 +110,24 @@ allOf:
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|||
- const: oscclk
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- const: dout_clkcmu_core_bus
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynosautov9-cmu-dpum
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (26 MHz)
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- description: DPU Main bus clock (from CMU_TOP)
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clock-names:
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items:
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- const: oscclk
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- const: bus
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- if:
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properties:
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compatible:
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|
|
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@ -0,0 +1,162 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/samsung,exynosautov920-clock.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Samsung ExynosAuto v920 SoC clock controller
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maintainers:
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- Sunyeal Hong <sunyeal.hong@samsung.com>
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- Chanwoo Choi <cw00.choi@samsung.com>
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- Krzysztof Kozlowski <krzk@kernel.org>
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- Sylwester Nawrocki <s.nawrocki@samsung.com>
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description: |
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ExynosAuto v920 clock controller is comprised of several CMU units, generating
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clocks for different domains. Those CMU units are modeled as separate device
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tree nodes, and might depend on each other. Root clocks in that clock tree are
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two external clocks:: OSCCLK/XTCXO (38.4 MHz) and RTCCLK/XrtcXTI (32768 Hz).
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The external OSCCLK must be defined as fixed-rate clock in dts.
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CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
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dividers; all other clocks of function blocks (other CMUs) are usually
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derived from CMU_TOP.
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Each clock is assigned an identifier and client nodes can use this identifier
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to specify the clock which they consume. All clocks available for usage
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in clock consumer nodes are defined as preprocessor macros in
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'include/dt-bindings/clock/samsung,exynosautov920.h' header.
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properties:
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compatible:
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enum:
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- samsung,exynosautov920-cmu-top
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- samsung,exynosautov920-cmu-peric0
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- samsung,exynosautov920-cmu-peric1
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- samsung,exynosautov920-cmu-misc
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- samsung,exynosautov920-cmu-hsi0
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- samsung,exynosautov920-cmu-hsi1
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clocks:
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minItems: 1
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maxItems: 4
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clock-names:
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minItems: 1
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maxItems: 4
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"#clock-cells":
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const: 1
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reg:
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maxItems: 1
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allOf:
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynosautov920-cmu-top
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (38.4 MHz)
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clock-names:
|
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items:
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- const: oscclk
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- if:
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properties:
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compatible:
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contains:
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enum:
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- samsung,exynosautov920-cmu-peric0
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- samsung,exynosautov920-cmu-peric1
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (38.4 MHz)
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- description: CMU_PERICn NOC clock (from CMU_TOP)
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- description: CMU_PERICn IP clock (from CMU_TOP)
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clock-names:
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items:
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- const: oscclk
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- const: noc
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- const: ip
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- if:
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properties:
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compatible:
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enum:
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- samsung,exynosautov920-cmu-misc
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- samsung,exynosautov920-cmu-hsi0
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (38.4 MHz)
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- description: CMU_MISC/CMU_HSI0 NOC clock (from CMU_TOP)
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clock-names:
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items:
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- const: oscclk
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- const: noc
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynosautov920-cmu-hsi1
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||||
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||||
then:
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properties:
|
||||
clocks:
|
||||
items:
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||||
- description: External reference clock (38.4 MHz)
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- description: CMU_HSI1 NOC clock (from CMU_TOP)
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||||
- description: CMU_HSI1 USBDRD clock (from CMU_TOP)
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- description: CMU_HSI1 MMC_CARD clock (from CMU_TOP)
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clock-names:
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||||
items:
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- const: oscclk
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- const: noc
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- const: usbdrd
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- const: mmc_card
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required:
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- compatible
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- "#clock-cells"
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- clocks
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- clock-names
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- reg
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additionalProperties: false
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examples:
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# Clock controller node for CMU_PERIC0
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- |
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#include <dt-bindings/clock/samsung,exynosautov920.h>
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cmu_peric0: clock-controller@10800000 {
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compatible = "samsung,exynosautov920-cmu-peric0";
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reg = <0x10800000 0x8000>;
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#clock-cells = <1>;
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clocks = <&xtcxo>,
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<&cmu_top DOUT_CLKCMU_PERIC0_NOC>,
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<&cmu_top DOUT_CLKCMU_PERIC0_IP>;
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clock-names = "oscclk",
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"noc",
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"ip";
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};
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...
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@ -32,7 +32,7 @@
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device_type = "memory";
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reg = <0x0 0x80000000 0x3da00000>,
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<0x0 0xc0000000 0x40000000>,
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<0x8 0x80000000 0x40000000>;
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<0x8 0x80000000 0x80000000>;
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};
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gpio-keys {
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|
|
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@ -251,6 +251,52 @@
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"dout_fsys2_clkcmu_ethernet";
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};
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cmu_dpum: clock-controller@18c00000 {
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compatible = "samsung,exynosautov9-cmu-dpum";
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reg = <0x18c00000 0x8000>;
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#clock-cells = <1>;
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clocks = <&xtcxo>,
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<&cmu_top DOUT_CLKCMU_DPUM_BUS>;
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clock-names = "oscclk", "bus";
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};
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sysmmu_dpum_0: sysmmu@18c80000 {
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compatible = "samsung,exynos-sysmmu";
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reg = <0x18c80000 0x10000>;
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interrupts = <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cmu_dpum CLK_GOUT_DPUM_SYSMMU_D0_CLK>;
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clock-names = "sysmmu";
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#iommu-cells = <0>;
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};
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sysmmu_dpum_1: sysmmu@18c90000 {
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compatible = "samsung,exynos-sysmmu";
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reg = <0x18c90000 0x10000>;
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interrupts = <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cmu_dpum CLK_GOUT_DPUM_SYSMMU_D1_CLK>;
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clock-names = "sysmmu";
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#iommu-cells = <0>;
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};
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sysmmu_dpum_2: sysmmu@18ca0000 {
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compatible = "samsung,exynos-sysmmu";
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reg = <0x18ca0000 0x10000>;
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interrupts = <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cmu_dpum CLK_GOUT_DPUM_SYSMMU_D2_CLK>;
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clock-names = "sysmmu";
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#iommu-cells = <0>;
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};
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sysmmu_dpum_3: sysmmu@18cb0000 {
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compatible = "samsung,exynos-sysmmu";
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reg = <0x18cb0000 0x10000>;
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interrupts = <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cmu_dpum CLK_GOUT_DPUM_SYSMMU_D3_CLK>;
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clock-names = "sysmmu";
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#iommu-cells = <0>;
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};
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cmu_core: clock-controller@1b030000 {
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compatible = "samsung,exynosautov9-cmu-core";
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reg = <0x1b030000 0x8000>;
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|
|
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|||
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@ -6,6 +6,7 @@
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*
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*/
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#include <dt-bindings/clock/samsung,exynosautov920.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/soc/samsung,exynos-usi.h>
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@ -38,17 +39,6 @@
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clock-output-names = "oscclk";
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};
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/*
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* FIXME: Keep the stub clock for serial driver, until proper clock
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* driver is implemented.
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*/
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clock_usi: clock-usi {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <200000000>;
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clock-output-names = "usi";
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};
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cpus: cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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||||
|
|
@ -192,6 +182,19 @@
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|||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
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||||
|
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cmu_peric0: clock-controller@10800000 {
|
||||
compatible = "samsung,exynosautov920-cmu-peric0";
|
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reg = <0x10800000 0x8000>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
clocks = <&xtcxo>,
|
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<&cmu_top DOUT_CLKCMU_PERIC0_NOC>,
|
||||
<&cmu_top DOUT_CLKCMU_PERIC0_IP>;
|
||||
clock-names = "oscclk",
|
||||
"noc",
|
||||
"ip";
|
||||
};
|
||||
|
||||
syscon_peric0: syscon@10820000 {
|
||||
compatible = "samsung,exynosautov920-peric0-sysreg",
|
||||
"syscon";
|
||||
|
|
@ -213,7 +216,8 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
clocks = <&clock_usi>, <&clock_usi>;
|
||||
clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>,
|
||||
<&cmu_peric0 CLK_DOUT_PERIC0_USI00_USI>;
|
||||
clock-names = "pclk", "ipclk";
|
||||
status = "disabled";
|
||||
|
||||
|
|
@ -224,7 +228,8 @@
|
|||
interrupts = <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0_bus>;
|
||||
clocks = <&clock_usi>, <&clock_usi>;
|
||||
clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>,
|
||||
<&cmu_peric0 CLK_DOUT_PERIC0_USI00_USI>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
samsung,uart-fifosize = <256>;
|
||||
status = "disabled";
|
||||
|
|
@ -254,6 +259,15 @@
|
|||
interrupts = <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
cmu_top: clock-controller@11000000 {
|
||||
compatible = "samsung,exynosautov920-cmu-top";
|
||||
reg = <0x11000000 0x8000>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
clocks = <&xtcxo>;
|
||||
clock-names = "oscclk";
|
||||
};
|
||||
|
||||
pinctrl_alive: pinctrl@11850000 {
|
||||
compatible = "samsung,exynosautov920-pinctrl";
|
||||
reg = <0x11850000 0x10000>;
|
||||
|
|
|
|||
|
|
@ -1394,6 +1394,21 @@
|
|||
pmu_system_controller: system-controller@17460000 {
|
||||
compatible = "google,gs101-pmu", "syscon";
|
||||
reg = <0x17460000 0x10000>;
|
||||
|
||||
poweroff: syscon-poweroff {
|
||||
compatible = "syscon-poweroff";
|
||||
regmap = <&pmu_system_controller>;
|
||||
offset = <0x3e9c>; /* PAD_CTRL_PWR_HOLD */
|
||||
mask = <0x100>; /* reset value */
|
||||
};
|
||||
|
||||
reboot: syscon-reboot {
|
||||
compatible = "syscon-reboot";
|
||||
regmap = <&pmu_system_controller>;
|
||||
offset = <0x3a00>; /* SYSTEM_CONFIGURATION */
|
||||
mask = <0x2>; /* SWRESET_SYSTEM */
|
||||
value = <0x2>; /* reset value */
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_gpio_alive: pinctrl@174d0000 {
|
||||
|
|
|
|||
|
|
@ -69,6 +69,8 @@
|
|||
#define CLK_GOUT_FSYS_MMC_EMBD 58
|
||||
#define CLK_GOUT_FSYS_MMC_SDIO 59
|
||||
#define CLK_GOUT_FSYS_USB30DRD 60
|
||||
#define CLK_MOUT_SHARED0_PLL 61
|
||||
#define CLK_MOUT_SHARED1_PLL 62
|
||||
|
||||
/* CMU_CORE */
|
||||
#define CLK_MOUT_CORE_BUS_USER 1
|
||||
|
|
@ -132,16 +134,24 @@
|
|||
#define CLK_GOUT_WDT1_PCLK 43
|
||||
|
||||
/* CMU_FSYS */
|
||||
#define CLK_MOUT_FSYS_BUS_USER 1
|
||||
#define CLK_MOUT_FSYS_MMC_CARD_USER 2
|
||||
#define CLK_MOUT_FSYS_MMC_EMBD_USER 3
|
||||
#define CLK_MOUT_FSYS_MMC_SDIO_USER 4
|
||||
#define CLK_MOUT_FSYS_USB30DRD_USER 4
|
||||
#define CLK_GOUT_MMC_CARD_ACLK 5
|
||||
#define CLK_GOUT_MMC_CARD_SDCLKIN 6
|
||||
#define CLK_GOUT_MMC_EMBD_ACLK 7
|
||||
#define CLK_GOUT_MMC_EMBD_SDCLKIN 8
|
||||
#define CLK_GOUT_MMC_SDIO_ACLK 9
|
||||
#define CLK_GOUT_MMC_SDIO_SDCLKIN 10
|
||||
#define CLK_MOUT_FSYS_BUS_USER 1
|
||||
#define CLK_MOUT_FSYS_MMC_CARD_USER 2
|
||||
#define CLK_MOUT_FSYS_MMC_EMBD_USER 3
|
||||
#define CLK_MOUT_FSYS_MMC_SDIO_USER 4
|
||||
#define CLK_GOUT_MMC_CARD_ACLK 5
|
||||
#define CLK_GOUT_MMC_CARD_SDCLKIN 6
|
||||
#define CLK_GOUT_MMC_EMBD_ACLK 7
|
||||
#define CLK_GOUT_MMC_EMBD_SDCLKIN 8
|
||||
#define CLK_GOUT_MMC_SDIO_ACLK 9
|
||||
#define CLK_GOUT_MMC_SDIO_SDCLKIN 10
|
||||
#define CLK_MOUT_FSYS_USB30DRD_USER 11
|
||||
#define CLK_MOUT_USB_PLL 12
|
||||
#define CLK_FOUT_USB_PLL 13
|
||||
#define CLK_FSYS_USB20PHY_CLKCORE 14
|
||||
#define CLK_FSYS_USB30DRD_ACLK_20PHYCTRL 15
|
||||
#define CLK_FSYS_USB30DRD_ACLK_30PHYCTRL_0 16
|
||||
#define CLK_FSYS_USB30DRD_ACLK_30PHYCTRL_1 17
|
||||
#define CLK_FSYS_USB30DRD_BUS_CLK_EARLY 18
|
||||
#define CLK_FSYS_USB30DRD_REF_CLK 19
|
||||
|
||||
#endif /* _DT_BINDINGS_CLOCK_EXYNOS_7885_H */
|
||||
|
|
|
|||
|
|
@ -358,6 +358,7 @@
|
|||
#define CLK_GOUT_UART_PCLK 32
|
||||
#define CLK_GOUT_WDT0_PCLK 33
|
||||
#define CLK_GOUT_WDT1_PCLK 34
|
||||
#define CLK_GOUT_BUSIF_TMU_PCLK 35
|
||||
|
||||
/* CMU_CORE */
|
||||
#define CLK_MOUT_CORE_BUS_USER 1
|
||||
|
|
|
|||
|
|
@ -179,6 +179,17 @@
|
|||
#define CLK_GOUT_CORE_CCI_PCLK 4
|
||||
#define CLK_GOUT_CORE_CMU_CORE_PCLK 5
|
||||
|
||||
/* CMU_DPUM */
|
||||
#define CLK_MOUT_DPUM_BUS_USER 1
|
||||
#define CLK_DOUT_DPUM_BUSP 2
|
||||
#define CLK_GOUT_DPUM_ACLK_DECON 3
|
||||
#define CLK_GOUT_DPUM_ACLK_DMA 4
|
||||
#define CLK_GOUT_DPUM_ACLK_DPP 5
|
||||
#define CLK_GOUT_DPUM_SYSMMU_D0_CLK 6
|
||||
#define CLK_GOUT_DPUM_SYSMMU_D1_CLK 7
|
||||
#define CLK_GOUT_DPUM_SYSMMU_D2_CLK 8
|
||||
#define CLK_GOUT_DPUM_SYSMMU_D3_CLK 9
|
||||
|
||||
/* CMU_FSYS0 */
|
||||
#define CLK_MOUT_FSYS0_BUS_USER 1
|
||||
#define CLK_MOUT_FSYS0_PCIE_USER 2
|
||||
|
|
|
|||
191
include/dt-bindings/clock/samsung,exynosautov920.h
Normal file
191
include/dt-bindings/clock/samsung,exynosautov920.h
Normal file
|
|
@ -0,0 +1,191 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (c) 2024 Samsung Electronics Co., Ltd.
|
||||
* Author: Sunyeal Hong <sunyeal.hong@samsung.com>
|
||||
*
|
||||
* Device Tree binding constants for ExynosAuto v920 clock controller.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLOCK_EXYNOSAUTOV920_H
|
||||
#define _DT_BINDINGS_CLOCK_EXYNOSAUTOV920_H
|
||||
|
||||
/* CMU_TOP */
|
||||
#define FOUT_SHARED0_PLL 1
|
||||
#define FOUT_SHARED1_PLL 2
|
||||
#define FOUT_SHARED2_PLL 3
|
||||
#define FOUT_SHARED3_PLL 4
|
||||
#define FOUT_SHARED4_PLL 5
|
||||
#define FOUT_SHARED5_PLL 6
|
||||
#define FOUT_MMC_PLL 7
|
||||
|
||||
/* MUX in CMU_TOP */
|
||||
#define MOUT_SHARED0_PLL 8
|
||||
#define MOUT_SHARED1_PLL 9
|
||||
#define MOUT_SHARED2_PLL 10
|
||||
#define MOUT_SHARED3_PLL 11
|
||||
#define MOUT_SHARED4_PLL 12
|
||||
#define MOUT_SHARED5_PLL 13
|
||||
#define MOUT_MMC_PLL 14
|
||||
#define MOUT_CLKCMU_CMU_BOOST 15
|
||||
#define MOUT_CLKCMU_CMU_CMUREF 16
|
||||
#define MOUT_CLKCMU_ACC_NOC 17
|
||||
#define MOUT_CLKCMU_ACC_ORB 18
|
||||
#define MOUT_CLKCMU_APM_NOC 19
|
||||
#define MOUT_CLKCMU_AUD_CPU 20
|
||||
#define MOUT_CLKCMU_AUD_NOC 21
|
||||
#define MOUT_CLKCMU_CPUCL0_SWITCH 22
|
||||
#define MOUT_CLKCMU_CPUCL0_CLUSTER 23
|
||||
#define MOUT_CLKCMU_CPUCL0_DBG 24
|
||||
#define MOUT_CLKCMU_CPUCL1_SWITCH 25
|
||||
#define MOUT_CLKCMU_CPUCL1_CLUSTER 26
|
||||
#define MOUT_CLKCMU_CPUCL2_SWITCH 27
|
||||
#define MOUT_CLKCMU_CPUCL2_CLUSTER 28
|
||||
#define MOUT_CLKCMU_DNC_NOC 29
|
||||
#define MOUT_CLKCMU_DPTX_NOC 30
|
||||
#define MOUT_CLKCMU_DPTX_DPGTC 31
|
||||
#define MOUT_CLKCMU_DPTX_DPOSC 32
|
||||
#define MOUT_CLKCMU_DPUB_NOC 33
|
||||
#define MOUT_CLKCMU_DPUB_DSIM 34
|
||||
#define MOUT_CLKCMU_DPUF0_NOC 35
|
||||
#define MOUT_CLKCMU_DPUF1_NOC 36
|
||||
#define MOUT_CLKCMU_DPUF2_NOC 37
|
||||
#define MOUT_CLKCMU_DSP_NOC 38
|
||||
#define MOUT_CLKCMU_G3D_SWITCH 39
|
||||
#define MOUT_CLKCMU_G3D_NOCP 40
|
||||
#define MOUT_CLKCMU_GNPU_NOC 41
|
||||
#define MOUT_CLKCMU_HSI0_NOC 42
|
||||
#define MOUT_CLKCMU_HSI1_NOC 43
|
||||
#define MOUT_CLKCMU_HSI1_USBDRD 44
|
||||
#define MOUT_CLKCMU_HSI1_MMC_CARD 45
|
||||
#define MOUT_CLKCMU_HSI2_NOC 46
|
||||
#define MOUT_CLKCMU_HSI2_NOC_UFS 47
|
||||
#define MOUT_CLKCMU_HSI2_UFS_EMBD 48
|
||||
#define MOUT_CLKCMU_HSI2_ETHERNET 49
|
||||
#define MOUT_CLKCMU_ISP_NOC 50
|
||||
#define MOUT_CLKCMU_M2M_NOC 51
|
||||
#define MOUT_CLKCMU_M2M_JPEG 52
|
||||
#define MOUT_CLKCMU_MFC_MFC 53
|
||||
#define MOUT_CLKCMU_MFC_WFD 54
|
||||
#define MOUT_CLKCMU_MFD_NOC 55
|
||||
#define MOUT_CLKCMU_MIF_SWITCH 56
|
||||
#define MOUT_CLKCMU_MIF_NOCP 57
|
||||
#define MOUT_CLKCMU_MISC_NOC 58
|
||||
#define MOUT_CLKCMU_NOCL0_NOC 59
|
||||
#define MOUT_CLKCMU_NOCL1_NOC 60
|
||||
#define MOUT_CLKCMU_NOCL2_NOC 61
|
||||
#define MOUT_CLKCMU_PERIC0_NOC 62
|
||||
#define MOUT_CLKCMU_PERIC0_IP 63
|
||||
#define MOUT_CLKCMU_PERIC1_NOC 64
|
||||
#define MOUT_CLKCMU_PERIC1_IP 65
|
||||
#define MOUT_CLKCMU_SDMA_NOC 66
|
||||
#define MOUT_CLKCMU_SNW_NOC 67
|
||||
#define MOUT_CLKCMU_SSP_NOC 68
|
||||
#define MOUT_CLKCMU_TAA_NOC 69
|
||||
|
||||
/* DIV in CMU_TOP */
|
||||
#define DOUT_SHARED0_DIV1 70
|
||||
#define DOUT_SHARED0_DIV2 71
|
||||
#define DOUT_SHARED0_DIV3 72
|
||||
#define DOUT_SHARED0_DIV4 73
|
||||
#define DOUT_SHARED1_DIV1 74
|
||||
#define DOUT_SHARED1_DIV2 75
|
||||
#define DOUT_SHARED1_DIV3 76
|
||||
#define DOUT_SHARED1_DIV4 77
|
||||
#define DOUT_SHARED2_DIV1 78
|
||||
#define DOUT_SHARED2_DIV2 79
|
||||
#define DOUT_SHARED2_DIV3 80
|
||||
#define DOUT_SHARED2_DIV4 81
|
||||
#define DOUT_SHARED3_DIV1 82
|
||||
#define DOUT_SHARED3_DIV2 83
|
||||
#define DOUT_SHARED3_DIV3 84
|
||||
#define DOUT_SHARED3_DIV4 85
|
||||
#define DOUT_SHARED4_DIV1 86
|
||||
#define DOUT_SHARED4_DIV2 87
|
||||
#define DOUT_SHARED4_DIV3 88
|
||||
#define DOUT_SHARED4_DIV4 89
|
||||
#define DOUT_SHARED5_DIV1 90
|
||||
#define DOUT_SHARED5_DIV2 91
|
||||
#define DOUT_SHARED5_DIV3 92
|
||||
#define DOUT_SHARED5_DIV4 93
|
||||
#define DOUT_CLKCMU_CMU_BOOST 94
|
||||
#define DOUT_CLKCMU_ACC_NOC 95
|
||||
#define DOUT_CLKCMU_ACC_ORB 96
|
||||
#define DOUT_CLKCMU_APM_NOC 97
|
||||
#define DOUT_CLKCMU_AUD_CPU 98
|
||||
#define DOUT_CLKCMU_AUD_NOC 99
|
||||
#define DOUT_CLKCMU_CPUCL0_SWITCH 100
|
||||
#define DOUT_CLKCMU_CPUCL0_CLUSTER 101
|
||||
#define DOUT_CLKCMU_CPUCL0_DBG 102
|
||||
#define DOUT_CLKCMU_CPUCL1_SWITCH 103
|
||||
#define DOUT_CLKCMU_CPUCL1_CLUSTER 104
|
||||
#define DOUT_CLKCMU_CPUCL2_SWITCH 105
|
||||
#define DOUT_CLKCMU_CPUCL2_CLUSTER 106
|
||||
#define DOUT_CLKCMU_DNC_NOC 107
|
||||
#define DOUT_CLKCMU_DPTX_NOC 108
|
||||
#define DOUT_CLKCMU_DPTX_DPGTC 109
|
||||
#define DOUT_CLKCMU_DPTX_DPOSC 110
|
||||
#define DOUT_CLKCMU_DPUB_NOC 111
|
||||
#define DOUT_CLKCMU_DPUB_DSIM 112
|
||||
#define DOUT_CLKCMU_DPUF0_NOC 113
|
||||
#define DOUT_CLKCMU_DPUF1_NOC 114
|
||||
#define DOUT_CLKCMU_DPUF2_NOC 115
|
||||
#define DOUT_CLKCMU_DSP_NOC 116
|
||||
#define DOUT_CLKCMU_G3D_SWITCH 117
|
||||
#define DOUT_CLKCMU_G3D_NOCP 118
|
||||
#define DOUT_CLKCMU_GNPU_NOC 119
|
||||
#define DOUT_CLKCMU_HSI0_NOC 120
|
||||
#define DOUT_CLKCMU_HSI1_NOC 121
|
||||
#define DOUT_CLKCMU_HSI1_USBDRD 122
|
||||
#define DOUT_CLKCMU_HSI1_MMC_CARD 123
|
||||
#define DOUT_CLKCMU_HSI2_NOC 124
|
||||
#define DOUT_CLKCMU_HSI2_NOC_UFS 125
|
||||
#define DOUT_CLKCMU_HSI2_UFS_EMBD 126
|
||||
#define DOUT_CLKCMU_HSI2_ETHERNET 127
|
||||
#define DOUT_CLKCMU_ISP_NOC 128
|
||||
#define DOUT_CLKCMU_M2M_NOC 129
|
||||
#define DOUT_CLKCMU_M2M_JPEG 130
|
||||
#define DOUT_CLKCMU_MFC_MFC 131
|
||||
#define DOUT_CLKCMU_MFC_WFD 132
|
||||
#define DOUT_CLKCMU_MFD_NOC 133
|
||||
#define DOUT_CLKCMU_MIF_NOCP 134
|
||||
#define DOUT_CLKCMU_MISC_NOC 135
|
||||
#define DOUT_CLKCMU_NOCL0_NOC 136
|
||||
#define DOUT_CLKCMU_NOCL1_NOC 137
|
||||
#define DOUT_CLKCMU_NOCL2_NOC 138
|
||||
#define DOUT_CLKCMU_PERIC0_NOC 139
|
||||
#define DOUT_CLKCMU_PERIC0_IP 140
|
||||
#define DOUT_CLKCMU_PERIC1_NOC 141
|
||||
#define DOUT_CLKCMU_PERIC1_IP 142
|
||||
#define DOUT_CLKCMU_SDMA_NOC 143
|
||||
#define DOUT_CLKCMU_SNW_NOC 144
|
||||
#define DOUT_CLKCMU_SSP_NOC 145
|
||||
#define DOUT_CLKCMU_TAA_NOC 146
|
||||
|
||||
/* CMU_PERIC0 */
|
||||
#define CLK_MOUT_PERIC0_IP_USER 1
|
||||
#define CLK_MOUT_PERIC0_NOC_USER 2
|
||||
#define CLK_MOUT_PERIC0_USI00_USI 3
|
||||
#define CLK_MOUT_PERIC0_USI01_USI 4
|
||||
#define CLK_MOUT_PERIC0_USI02_USI 5
|
||||
#define CLK_MOUT_PERIC0_USI03_USI 6
|
||||
#define CLK_MOUT_PERIC0_USI04_USI 7
|
||||
#define CLK_MOUT_PERIC0_USI05_USI 8
|
||||
#define CLK_MOUT_PERIC0_USI06_USI 9
|
||||
#define CLK_MOUT_PERIC0_USI07_USI 10
|
||||
#define CLK_MOUT_PERIC0_USI08_USI 11
|
||||
#define CLK_MOUT_PERIC0_USI_I2C 12
|
||||
#define CLK_MOUT_PERIC0_I3C 13
|
||||
|
||||
#define CLK_DOUT_PERIC0_USI00_USI 14
|
||||
#define CLK_DOUT_PERIC0_USI01_USI 15
|
||||
#define CLK_DOUT_PERIC0_USI02_USI 16
|
||||
#define CLK_DOUT_PERIC0_USI03_USI 17
|
||||
#define CLK_DOUT_PERIC0_USI04_USI 18
|
||||
#define CLK_DOUT_PERIC0_USI05_USI 19
|
||||
#define CLK_DOUT_PERIC0_USI06_USI 20
|
||||
#define CLK_DOUT_PERIC0_USI07_USI 21
|
||||
#define CLK_DOUT_PERIC0_USI08_USI 22
|
||||
#define CLK_DOUT_PERIC0_USI_I2C 23
|
||||
#define CLK_DOUT_PERIC0_I3C 24
|
||||
|
||||
#endif /* _DT_BINDINGS_CLOCK_EXYNOSAUTOV920_H */
|
||||
Loading…
Reference in New Issue
Block a user