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Merge remote-tracking branches 'asoc/topic/cs43130', 'asoc/topic/cs53l30', 'asoc/topic/cygnus' and 'asoc/topic/davinci' into asoc-next

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This commit is contained in:
Mark Brown 2017-09-01 12:12:32 +01:00
commit 3b2d0bb5ef
9 changed files with 3376 additions and 196 deletions
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67
Documentation/devicetree/bindings/sound/cs43130.txt Normal file
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@ -0,0 +1,67 @@
CS43130 DAC
Required properties:
- compatible : "cirrus,cs43130", "cirrus,cs4399", "cirrus,cs43131",
"cirrus,cs43198"
- reg : the I2C address of the device for I2C
- VA-supply, VP-supply, VL-supply, VCP-supply, VD-supply:
power supplies for the device, as covered in
Documentation/devicetree/bindings/regulator/regulator.txt.
Optional properties:
- reset-gpios : Active low GPIO used to reset the device
- cirrus,xtal-ibias:
When external MCLK is generated by external crystal
oscillator, CS43130 can be used to provide bias current
for external crystal. Amount of bias current sent is
set as:
1 = 7.5uA
2 = 12.5uA
3 = 15uA
- cirrus,dc-measure:
Boolean, define to enable headphone DC impedance measurement.
- cirrus,ac-measure:
Boolean, define to enable headphone AC impedance measurement.
DC impedance must also be enabled for AC impedance measurement.
- cirrus,dc-threshold:
Define 2 DC impedance thresholds in ohms for HP output control.
Default values are 50 and 120 Ohms.
- cirrus,ac-freq:
Define the frequencies at which to measure HP AC impedance.
Only used if "cirrus,dc-measure" is defined.
Exactly 10 frequencies must be defined.
If this properties is undefined, by default,
following frequencies are used:
<24 43 93 200 431 928 2000 4309 9283 20000>
The above frequencies are logarithmically equally spaced.
Log base is 10.
Example:
cs43130: audio-codec@30 {
compatible = "cirrus,cs43130";
reg = <0x30>;
reset-gpios = <&axi_gpio 54 0>;
VA-supply = <&dummy_vreg>;
VP-supply = <&dummy_vreg>;
VL-supply = <&dummy_vreg>;
VCP-supply = <&dummy_vreg>;
VD-supply = <&dummy_vreg>;
cirrus,xtal-ibias = <2>;
interrupt-parent = <&gpio0>;
interrupts = <55 8>;
cirrus,dc-measure;
cirrus,ac-measure;
cirrus,dc-threshold = /bits/ 16 <20 100>;
cirrus,ac-freq = /bits/ 16 <24 43 93 200 431 928 2000 4309 9283 20000>;
};

235
sound/soc/bcm/cygnus-ssp.c
View File

@ -27,12 +27,6 @@
#define DEFAULT_VCO 1354750204
#define CYGNUS_TDM_RATE \
(SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 | \
SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_22050 | \
SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
SNDRV_PCM_RATE_48000)
#define CAPTURE_FCI_ID_BASE 0x180
#define CYGNUS_SSP_TRISTATE_MASK 0x001fff
#define CYGNUS_PLLCLKSEL_MASK 0xf
@ -234,152 +228,20 @@ static const struct pll_macro_entry pll_predef_mclk[] = {
{98304000, 2},
};
#define CYGNUS_RATE_MIN 8000
#define CYGNUS_RATE_MAX 384000
/* List of valid frame sizes for tdm mode */
static const int ssp_valid_tdm_framesize[] = {32, 64, 128, 256, 512};
/*
* Use this relationship to derive the sampling rate (lrclk)
* lrclk = (mclk) / ((2*mclk_to_sclk_ratio) * (32 * SCLK))).
*
* Use mclk and pll_ch from the table above
*
* Valid SCLK = 0/1/2/4/8/12
*
* mclk_to_sclk_ratio = number of MCLK per SCLK. Division is twice the
* value programmed in this field.
* Valid mclk_to_sclk_ratio = 1 through to 15
*
* eg: To set lrclk = 48khz, set mclk = 12288000, mclk_to_sclk_ratio = 2,
* SCLK = 64
*/
struct _ssp_clk_coeff {
u32 mclk;
u32 sclk_rate;
u32 rate;
u32 mclk_rate;
static const unsigned int cygnus_rates[] = {
8000, 11025, 16000, 22050, 32000, 44100, 48000,
88200, 96000, 176400, 192000, 352800, 384000
};
static const struct _ssp_clk_coeff ssp_clk_coeff[] = {
{ 4096000, 32, 16000, 4},
{ 4096000, 32, 32000, 2},
{ 4096000, 64, 8000, 4},
{ 4096000, 64, 16000, 2},
{ 4096000, 64, 32000, 1},
{ 4096000, 128, 8000, 2},
{ 4096000, 128, 16000, 1},
{ 4096000, 256, 8000, 1},
{ 6144000, 32, 16000, 6},
{ 6144000, 32, 32000, 3},
{ 6144000, 32, 48000, 2},
{ 6144000, 32, 96000, 1},
{ 6144000, 64, 8000, 6},
{ 6144000, 64, 16000, 3},
{ 6144000, 64, 48000, 1},
{ 6144000, 128, 8000, 3},
{ 8192000, 32, 32000, 4},
{ 8192000, 64, 16000, 4},
{ 8192000, 64, 32000, 2},
{ 8192000, 128, 8000, 4},
{ 8192000, 128, 16000, 2},
{ 8192000, 128, 32000, 1},
{ 8192000, 256, 8000, 2},
{ 8192000, 256, 16000, 1},
{ 8192000, 512, 8000, 1},
{12288000, 32, 32000, 6},
{12288000, 32, 48000, 4},
{12288000, 32, 96000, 2},
{12288000, 32, 192000, 1},
{12288000, 64, 16000, 6},
{12288000, 64, 32000, 3},
{12288000, 64, 48000, 2},
{12288000, 64, 96000, 1},
{12288000, 128, 8000, 6},
{12288000, 128, 16000, 3},
{12288000, 128, 48000, 1},
{12288000, 256, 8000, 3},
{16384000, 64, 32000, 4},
{16384000, 128, 16000, 4},
{16384000, 128, 32000, 2},
{16384000, 256, 8000, 4},
{16384000, 256, 16000, 2},
{16384000, 256, 32000, 1},
{16384000, 512, 8000, 2},
{16384000, 512, 16000, 1},
{24576000, 32, 96000, 4},
{24576000, 32, 192000, 2},
{24576000, 64, 32000, 6},
{24576000, 64, 48000, 4},
{24576000, 64, 96000, 2},
{24576000, 64, 192000, 1},
{24576000, 128, 16000, 6},
{24576000, 128, 32000, 3},
{24576000, 128, 48000, 2},
{24576000, 256, 8000, 6},
{24576000, 256, 16000, 3},
{24576000, 256, 48000, 1},
{24576000, 512, 8000, 3},
{49152000, 32, 192000, 4},
{49152000, 64, 96000, 4},
{49152000, 64, 192000, 2},
{49152000, 128, 32000, 6},
{49152000, 128, 48000, 4},
{49152000, 128, 96000, 2},
{49152000, 128, 192000, 1},
{49152000, 256, 16000, 6},
{49152000, 256, 32000, 3},
{49152000, 256, 48000, 2},
{49152000, 256, 96000, 1},
{49152000, 512, 8000, 6},
{49152000, 512, 16000, 3},
{49152000, 512, 48000, 1},
{ 5644800, 32, 22050, 4},
{ 5644800, 32, 44100, 2},
{ 5644800, 32, 88200, 1},
{ 5644800, 64, 11025, 4},
{ 5644800, 64, 22050, 2},
{ 5644800, 64, 44100, 1},
{11289600, 32, 44100, 4},
{11289600, 32, 88200, 2},
{11289600, 32, 176400, 1},
{11289600, 64, 22050, 4},
{11289600, 64, 44100, 2},
{11289600, 64, 88200, 1},
{11289600, 128, 11025, 4},
{11289600, 128, 22050, 2},
{11289600, 128, 44100, 1},
{22579200, 32, 88200, 4},
{22579200, 32, 176400, 2},
{22579200, 64, 44100, 4},
{22579200, 64, 88200, 2},
{22579200, 64, 176400, 1},
{22579200, 128, 22050, 4},
{22579200, 128, 44100, 2},
{22579200, 128, 88200, 1},
{22579200, 256, 11025, 4},
{22579200, 256, 22050, 2},
{22579200, 256, 44100, 1},
{45158400, 32, 176400, 4},
{45158400, 64, 88200, 4},
{45158400, 64, 176400, 2},
{45158400, 128, 44100, 4},
{45158400, 128, 88200, 2},
{45158400, 128, 176400, 1},
{45158400, 256, 22050, 4},
{45158400, 256, 44100, 2},
{45158400, 256, 88200, 1},
{45158400, 512, 11025, 4},
{45158400, 512, 22050, 2},
{45158400, 512, 44100, 1},
static const struct snd_pcm_hw_constraint_list cygnus_rate_constraint = {
.count = ARRAY_SIZE(cygnus_rates),
.list = cygnus_rates,
};
static struct cygnus_aio_port *cygnus_dai_get_portinfo(struct snd_soc_dai *dai)
@ -679,40 +541,55 @@ static int pll_configure_mclk(struct cygnus_audio *cygaud, u32 mclk,
return p_entry->pll_ch_num;
}
static int cygnus_ssp_set_clocks(struct cygnus_aio_port *aio,
struct cygnus_audio *cygaud)
static int cygnus_ssp_set_clocks(struct cygnus_aio_port *aio)
{
u32 value, i = 0;
u32 value;
u32 mask = 0xf;
u32 sclk;
bool found = false;
const struct _ssp_clk_coeff *p_entry = NULL;
u32 mclk_rate;
unsigned int bit_rate;
unsigned int ratio;
for (i = 0; i < ARRAY_SIZE(ssp_clk_coeff); i++) {
p_entry = &ssp_clk_coeff[i];
if ((p_entry->rate == aio->lrclk) &&
(p_entry->sclk_rate == aio->bit_per_frame) &&
(p_entry->mclk == aio->mclk)) {
found = true;
break;
}
}
if (!found) {
bit_rate = aio->bit_per_frame * aio->lrclk;
/*
* Check if the bit clock can be generated from the given MCLK.
* MCLK must be a perfect multiple of bit clock and must be one of the
* following values... (2,4,6,8,10,12,14)
*/
if ((aio->mclk % bit_rate) != 0)
return -EINVAL;
ratio = aio->mclk / bit_rate;
switch (ratio) {
case 2:
case 4:
case 6:
case 8:
case 10:
case 12:
case 14:
mclk_rate = ratio / 2;
break;
default:
dev_err(aio->cygaud->dev,
"No valid match found in ssp_clk_coeff array\n");
"Invalid combination of MCLK and BCLK\n");
dev_err(aio->cygaud->dev, "lrclk = %u, bits/frame = %u, mclk = %u\n",
aio->lrclk, aio->bit_per_frame, aio->mclk);
return -EINVAL;
}
sclk = aio->bit_per_frame;
if (sclk == 512)
sclk = 0;
/* sclks_per_1fs_div = sclk cycles/32 */
sclk /= 32;
/* Set sclk rate */
switch (aio->port_type) {
case PORT_TDM:
sclk = aio->bit_per_frame;
if (sclk == 512)
sclk = 0;
/* sclks_per_1fs_div = sclk cycles/32 */
sclk /= 32;
/* Set number of bitclks per frame */
value = readl(aio->cygaud->audio + aio->regs.i2s_cfg);
value &= ~(mask << I2S_OUT_CFGX_SCLKS_PER_1FS_DIV32);
@ -731,7 +608,7 @@ static int cygnus_ssp_set_clocks(struct cygnus_aio_port *aio,
/* Set MCLK_RATE ssp port (spdif and ssp are the same) */
value = readl(aio->cygaud->audio + aio->regs.i2s_mclk_cfg);
value &= ~(0xf << I2S_OUT_MCLKRATE_SHIFT);
value |= (p_entry->mclk_rate << I2S_OUT_MCLKRATE_SHIFT);
value |= (mclk_rate << I2S_OUT_MCLKRATE_SHIFT);
writel(value, aio->cygaud->audio + aio->regs.i2s_mclk_cfg);
dev_dbg(aio->cygaud->dev, "mclk cfg reg = 0x%x\n", value);
@ -745,7 +622,6 @@ static int cygnus_ssp_hw_params(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct cygnus_aio_port *aio = cygnus_dai_get_portinfo(dai);
struct cygnus_audio *cygaud = snd_soc_dai_get_drvdata(dai);
int rate, bitres;
u32 value;
u32 mask = 0x1f;
@ -841,7 +717,7 @@ static int cygnus_ssp_hw_params(struct snd_pcm_substream *substream,
aio->lrclk = rate;
if (!aio->is_slave)
ret = cygnus_ssp_set_clocks(aio, cygaud);
ret = cygnus_ssp_set_clocks(aio);
return ret;
}
@ -888,6 +764,11 @@ static int cygnus_ssp_startup(struct snd_pcm_substream *substream,
else
aio->clk_trace.cap_en = true;
substream->runtime->hw.rate_min = CYGNUS_RATE_MIN;
substream->runtime->hw.rate_max = CYGNUS_RATE_MAX;
snd_pcm_hw_constraint_list(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_RATE, &cygnus_rate_constraint);
return 0;
}
@ -1261,9 +1142,7 @@ static const struct snd_soc_dai_ops cygnus_ssp_dai_ops = {
.playback = { \
.channels_min = 1, \
.channels_max = 16, \
.rates = CYGNUS_TDM_RATE | SNDRV_PCM_RATE_88200 | \
SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | \
SNDRV_PCM_RATE_192000, \
.rates = SNDRV_PCM_RATE_KNOT, \
.formats = SNDRV_PCM_FMTBIT_S8 | \
SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S32_LE, \
@ -1271,9 +1150,7 @@ static const struct snd_soc_dai_ops cygnus_ssp_dai_ops = {
.capture = { \
.channels_min = 2, \
.channels_max = 16, \
.rates = CYGNUS_TDM_RATE | SNDRV_PCM_RATE_88200 | \
SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | \
SNDRV_PCM_RATE_192000, \
.rates = SNDRV_PCM_RATE_KNOT, \
.formats = SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S32_LE, \
}, \
@ -1293,9 +1170,7 @@ static const struct snd_soc_dai_driver cygnus_spdif_dai_info = {
.playback = {
.channels_min = 2,
.channels_max = 2,
.rates = CYGNUS_TDM_RATE | SNDRV_PCM_RATE_88200 |
SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
SNDRV_PCM_RATE_192000,
.rates = SNDRV_PCM_RATE_KNOT,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S32_LE,
},

6
sound/soc/codecs/Kconfig
View File

@ -60,6 +60,7 @@ config SND_SOC_ALL_CODECS
select SND_SOC_CS4271_I2C if I2C
select SND_SOC_CS4271_SPI if SPI_MASTER
select SND_SOC_CS42XX8_I2C if I2C
select SND_SOC_CS43130 if I2C
select SND_SOC_CS4349 if I2C
select SND_SOC_CS47L24 if MFD_CS47L24
select SND_SOC_CS53L30 if I2C
@ -487,6 +488,11 @@ config SND_SOC_CS42XX8_I2C
select SND_SOC_CS42XX8
select REGMAP_I2C
# Cirrus Logic CS43130 HiFi DAC
config SND_SOC_CS43130
tristate "Cirrus Logic CS43130 CODEC"
depends on I2C
# Cirrus Logic CS4349 HiFi DAC
config SND_SOC_CS4349
tristate "Cirrus Logic CS4349 CODEC"

2
sound/soc/codecs/Makefile
View File

@ -53,6 +53,7 @@ snd-soc-cs4271-i2c-objs := cs4271-i2c.o
snd-soc-cs4271-spi-objs := cs4271-spi.o
snd-soc-cs42xx8-objs := cs42xx8.o
snd-soc-cs42xx8-i2c-objs := cs42xx8-i2c.o
snd-soc-cs43130-objs := cs43130.o
snd-soc-cs4349-objs := cs4349.o
snd-soc-cs47l24-objs := cs47l24.o
snd-soc-cs53l30-objs := cs53l30.o
@ -291,6 +292,7 @@ obj-$(CONFIG_SND_SOC_CS4271_I2C) += snd-soc-cs4271-i2c.o
obj-$(CONFIG_SND_SOC_CS4271_SPI) += snd-soc-cs4271-spi.o
obj-$(CONFIG_SND_SOC_CS42XX8) += snd-soc-cs42xx8.o
obj-$(CONFIG_SND_SOC_CS42XX8_I2C) += snd-soc-cs42xx8-i2c.o
obj-$(CONFIG_SND_SOC_CS43130) += snd-soc-cs43130.o
obj-$(CONFIG_SND_SOC_CS4349) += snd-soc-cs4349.o
obj-$(CONFIG_SND_SOC_CS47L24) += snd-soc-cs47l24.o
obj-$(CONFIG_SND_SOC_CS53L30) += snd-soc-cs53l30.o

2690
sound/soc/codecs/cs43130.c Normal file
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File diff suppressed because it is too large Load Diff

546
sound/soc/codecs/cs43130.h Normal file
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@ -0,0 +1,546 @@
/*
* ALSA SoC CS43130 codec driver
*
* Copyright 2017 Cirrus Logic, Inc.
*
* Author: Li Xu <li.xu@cirrus.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
*/
#ifndef __CS43130_H__
#define __CS43130_H__
/* CS43130 registers addresses */
/* all reg address is shifted by a byte for control byte to be LSB */
#define CS43130_FIRSTREG 0x010000
#define CS43130_LASTREG 0x190000
#define CS43130_CHIP_ID 0x00043130
#define CS4399_CHIP_ID 0x00043990
#define CS43131_CHIP_ID 0x00043131
#define CS43198_CHIP_ID 0x00043198
#define CS43130_DEVID_AB 0x010000 /* Device ID A & B [RO] */
#define CS43130_DEVID_CD 0x010001 /* Device ID C & D [RO] */
#define CS43130_DEVID_E 0x010002 /* Device ID E [RO] */
#define CS43130_FAB_ID 0x010003 /* Fab ID [RO] */
#define CS43130_REV_ID 0x010004 /* Revision ID [RO] */
#define CS43130_SUBREV_ID 0x010005 /* Subrevision ID */
#define CS43130_SYS_CLK_CTL_1 0x010006 /* System Clocking Ctl 1 */
#define CS43130_SP_SRATE 0x01000B /* Serial Port Sample Rate */
#define CS43130_SP_BITSIZE 0x01000C /* Serial Port Bit Size */
#define CS43130_PAD_INT_CFG 0x01000D /* Pad Interface Config */
#define CS43130_DXD1 0x010010 /* DXD1 */
#define CS43130_DXD7 0x010025 /* DXD7 */
#define CS43130_DXD19 0x010026 /* DXD19 */
#define CS43130_DXD17 0x010027 /* DXD17 */
#define CS43130_DXD18 0x010028 /* DXD18 */
#define CS43130_DXD12 0x01002C /* DXD12 */
#define CS43130_DXD8 0x01002E /* DXD8 */
#define CS43130_PWDN_CTL 0x020000 /* Power Down Ctl */
#define CS43130_DXD2 0x020019 /* DXD2 */
#define CS43130_CRYSTAL_SET 0x020052 /* Crystal Setting */
#define CS43130_PLL_SET_1 0x030001 /* PLL Setting 1 */
#define CS43130_PLL_SET_2 0x030002 /* PLL Setting 2 */
#define CS43130_PLL_SET_3 0x030003 /* PLL Setting 3 */
#define CS43130_PLL_SET_4 0x030004 /* PLL Setting 4 */
#define CS43130_PLL_SET_5 0x030005 /* PLL Setting 5 */
#define CS43130_PLL_SET_6 0x030008 /* PLL Setting 6 */
#define CS43130_PLL_SET_7 0x03000A /* PLL Setting 7 */
#define CS43130_PLL_SET_8 0x03001B /* PLL Setting 8 */
#define CS43130_PLL_SET_9 0x040002 /* PLL Setting 9 */
#define CS43130_PLL_SET_10 0x040003 /* PLL Setting 10 */
#define CS43130_CLKOUT_CTL 0x040004 /* CLKOUT Ctl */
#define CS43130_ASP_NUM_1 0x040010 /* ASP Numerator 1 */
#define CS43130_ASP_NUM_2 0x040011 /* ASP Numerator 2 */
#define CS43130_ASP_DEN_1 0x040012 /* ASP Denominator 1 */
#define CS43130_ASP_DEN_2 0x040013 /* ASP Denominator 2 */
#define CS43130_ASP_LRCK_HI_TIME_1 0x040014 /* ASP LRCK High Time 1 */
#define CS43130_ASP_LRCK_HI_TIME_2 0x040015 /* ASP LRCK High Time 2 */
#define CS43130_ASP_LRCK_PERIOD_1 0x040016 /* ASP LRCK Period 1 */
#define CS43130_ASP_LRCK_PERIOD_2 0x040017 /* ASP LRCK Period 2 */
#define CS43130_ASP_CLOCK_CONF 0x040018 /* ASP Clock Config */
#define CS43130_ASP_FRAME_CONF 0x040019 /* ASP Frame Config */
#define CS43130_XSP_NUM_1 0x040020 /* XSP Numerator 1 */
#define CS43130_XSP_NUM_2 0x040021 /* XSP Numerator 2 */
#define CS43130_XSP_DEN_1 0x040022 /* XSP Denominator 1 */
#define CS43130_XSP_DEN_2 0x040023 /* XSP Denominator 2 */
#define CS43130_XSP_LRCK_HI_TIME_1 0x040024 /* XSP LRCK High Time 1 */
#define CS43130_XSP_LRCK_HI_TIME_2 0x040025 /* XSP LRCK High Time 2 */
#define CS43130_XSP_LRCK_PERIOD_1 0x040026 /* XSP LRCK Period 1 */
#define CS43130_XSP_LRCK_PERIOD_2 0x040027 /* XSP LRCK Period 2 */
#define CS43130_XSP_CLOCK_CONF 0x040028 /* XSP Clock Config */
#define CS43130_XSP_FRAME_CONF 0x040029 /* XSP Frame Config */
#define CS43130_ASP_CH_1_LOC 0x050000 /* ASP Chan 1 Location */
#define CS43130_ASP_CH_2_LOC 0x050001 /* ASP Chan 2 Location */
#define CS43130_ASP_CH_1_SZ_EN 0x05000A /* ASP Chan 1 Size, Enable */
#define CS43130_ASP_CH_2_SZ_EN 0x05000B /* ASP Chan 2 Size, Enable */
#define CS43130_XSP_CH_1_LOC 0x060000 /* XSP Chan 1 Location */
#define CS43130_XSP_CH_2_LOC 0x060001 /* XSP Chan 2 Location */
#define CS43130_XSP_CH_1_SZ_EN 0x06000A /* XSP Chan 1 Size, Enable */
#define CS43130_XSP_CH_2_SZ_EN 0x06000B /* XSP Chan 2 Size, Enable */
#define CS43130_DSD_VOL_B 0x070000 /* DSD Volume B */
#define CS43130_DSD_VOL_A 0x070001 /* DSD Volume A */
#define CS43130_DSD_PATH_CTL_1 0x070002 /* DSD Proc Path Sig Ctl 1 */
#define CS43130_DSD_INT_CFG 0x070003 /* DSD Interface Config */
#define CS43130_DSD_PATH_CTL_2 0x070004 /* DSD Proc Path Sig Ctl 2 */
#define CS43130_DSD_PCM_MIX_CTL 0x070005 /* DSD and PCM Mixing Ctl */
#define CS43130_DSD_PATH_CTL_3 0x070006 /* DSD Proc Path Sig Ctl 3 */
#define CS43130_HP_OUT_CTL_1 0x080000 /* HP Output Ctl 1 */
#define CS43130_DXD16 0x080024 /* DXD16 */
#define CS43130_DXD13 0x080032 /* DXD13 */
#define CS43130_PCM_FILT_OPT 0x090000 /* PCM Filter Option */
#define CS43130_PCM_VOL_B 0x090001 /* PCM Volume B */
#define CS43130_PCM_VOL_A 0x090002 /* PCM Volume A */
#define CS43130_PCM_PATH_CTL_1 0x090003 /* PCM Path Signal Ctl 1 */
#define CS43130_PCM_PATH_CTL_2 0x090004 /* PCM Path Signal Ctl 2 */
#define CS43130_DXD6 0x090097 /* DXD6 */
#define CS43130_CLASS_H_CTL 0x0B0000 /* Class H Ctl */
#define CS43130_DXD15 0x0B0005 /* DXD15 */
#define CS43130_DXD14 0x0B0006 /* DXD14 */
#define CS43130_DXD3 0x0C0002 /* DXD3 */
#define CS43130_DXD10 0x0C0003 /* DXD10 */
#define CS43130_DXD11 0x0C0005 /* DXD11 */
#define CS43130_DXD9 0x0C0006 /* DXD9 */
#define CS43130_DXD4 0x0C0009 /* DXD4 */
#define CS43130_DXD5 0x0C000E /* DXD5 */
#define CS43130_HP_DETECT 0x0D0000 /* HP Detect */
#define CS43130_HP_STATUS 0x0D0001 /* HP Status [RO] */
#define CS43130_HP_LOAD_1 0x0E0000 /* HP Load 1 */
#define CS43130_HP_MEAS_LOAD_1 0x0E0003 /* HP Load Measurement 1 */
#define CS43130_HP_MEAS_LOAD_2 0x0E0004 /* HP Load Measurement 2 */
#define CS43130_HP_DC_STAT_1 0x0E000D /* HP DC Load Status 0 [RO] */
#define CS43130_HP_DC_STAT_2 0x0E000E /* HP DC Load Status 1 [RO] */
#define CS43130_HP_AC_STAT_1 0x0E0010 /* HP AC Load Status 0 [RO] */
#define CS43130_HP_AC_STAT_2 0x0E0011 /* HP AC Load Status 1 [RO] */
#define CS43130_HP_LOAD_STAT 0x0E001A /* HP Load Status [RO] */
#define CS43130_INT_STATUS_1 0x0F0000 /* Interrupt Status 1 */
#define CS43130_INT_STATUS_2 0x0F0001 /* Interrupt Status 2 */
#define CS43130_INT_STATUS_3 0x0F0002 /* Interrupt Status 3 */
#define CS43130_INT_STATUS_4 0x0F0003 /* Interrupt Status 4 */
#define CS43130_INT_STATUS_5 0x0F0004 /* Interrupt Status 5 */
#define CS43130_INT_MASK_1 0x0F0010 /* Interrupt Mask 1 */
#define CS43130_INT_MASK_2 0x0F0011 /* Interrupt Mask 2 */
#define CS43130_INT_MASK_3 0x0F0012 /* Interrupt Mask 3 */
#define CS43130_INT_MASK_4 0x0F0013 /* Interrupt Mask 4 */
#define CS43130_INT_MASK_5 0x0F0014 /* Interrupt Mask 5 */
#define CS43130_MCLK_SRC_SEL_MASK 0x03
#define CS43130_MCLK_SRC_SEL_SHIFT 0
#define CS43130_MCLK_INT_MASK 0x04
#define CS43130_MCLK_INT_SHIFT 2
#define CS43130_CH_BITSIZE_MASK 0x03
#define CS43130_CH_EN_MASK 0x04
#define CS43130_CH_EN_SHIFT 2
#define CS43130_ASP_BITSIZE_MASK 0x03
#define CS43130_XSP_BITSIZE_MASK 0x0C
#define CS43130_XSP_BITSIZE_SHIFT 2
#define CS43130_SP_BITSIZE_ASP_SHIFT 0
#define CS43130_HP_DETECT_CTRL_SHIFT 6
#define CS43130_HP_DETECT_CTRL_MASK (0x03 << CS43130_HP_DETECT_CTRL_SHIFT)
#define CS43130_HP_DETECT_INV_SHIFT 5
#define CS43130_HP_DETECT_INV_MASK (1 << CS43130_HP_DETECT_INV_SHIFT)
/* CS43130_INT_MASK_1 */
#define CS43130_HP_PLUG_INT_SHIFT 6
#define CS43130_HP_PLUG_INT (1 << CS43130_HP_PLUG_INT_SHIFT)
#define CS43130_HP_UNPLUG_INT_SHIFT 5
#define CS43130_HP_UNPLUG_INT (1 << CS43130_HP_UNPLUG_INT_SHIFT)
#define CS43130_XTAL_RDY_INT_SHIFT 4
#define CS43130_XTAL_RDY_INT_MASK 0x10
#define CS43130_XTAL_RDY_INT (1 << CS43130_XTAL_RDY_INT_SHIFT)
#define CS43130_XTAL_ERR_INT_SHIFT 3
#define CS43130_XTAL_ERR_INT (1 << CS43130_XTAL_ERR_INT_SHIFT)
#define CS43130_PLL_RDY_INT_MASK 0x04
#define CS43130_PLL_RDY_INT_SHIFT 2
#define CS43130_PLL_RDY_INT (1 << CS43130_PLL_RDY_INT_SHIFT)
/* CS43130_INT_MASK_4 */
#define CS43130_INT_MASK_ALL 0xFF
#define CS43130_HPLOAD_NO_DC_INT_SHIFT 7
#define CS43130_HPLOAD_NO_DC_INT (1 << CS43130_HPLOAD_NO_DC_INT_SHIFT)
#define CS43130_HPLOAD_UNPLUG_INT_SHIFT 6
#define CS43130_HPLOAD_UNPLUG_INT (1 << CS43130_HPLOAD_UNPLUG_INT_SHIFT)
#define CS43130_HPLOAD_OOR_INT_SHIFT 4
#define CS43130_HPLOAD_OOR_INT (1 << CS43130_HPLOAD_OOR_INT_SHIFT)
#define CS43130_HPLOAD_AC_INT_SHIFT 3
#define CS43130_HPLOAD_AC_INT (1 << CS43130_HPLOAD_AC_INT_SHIFT)
#define CS43130_HPLOAD_DC_INT_SHIFT 2
#define CS43130_HPLOAD_DC_INT (1 << CS43130_HPLOAD_DC_INT_SHIFT)
#define CS43130_HPLOAD_OFF_INT_SHIFT 1
#define CS43130_HPLOAD_OFF_INT (1 << CS43130_HPLOAD_OFF_INT_SHIFT)
#define CS43130_HPLOAD_ON_INT 1
/* CS43130_HP_LOAD_1 */
#define CS43130_HPLOAD_EN_SHIFT 7
#define CS43130_HPLOAD_EN (1 << CS43130_HPLOAD_EN_SHIFT)
#define CS43130_HPLOAD_CHN_SEL_SHIFT 4
#define CS43130_HPLOAD_CHN_SEL (1 << CS43130_HPLOAD_CHN_SEL_SHIFT)
#define CS43130_HPLOAD_AC_START_SHIFT 1
#define CS43130_HPLOAD_AC_START (1 << CS43130_HPLOAD_AC_START_SHIFT)
#define CS43130_HPLOAD_DC_START 1
/* Reg CS43130_SP_BITSIZE */
#define CS43130_SP_BIT_SIZE_8 0x03
#define CS43130_SP_BIT_SIZE_16 0x02
#define CS43130_SP_BIT_SIZE_24 0x01
#define CS43130_SP_BIT_SIZE_32 0x00
/* Reg CS43130_SP_CH_SZ_EN */
#define CS43130_CH_BIT_SIZE_8 0x00
#define CS43130_CH_BIT_SIZE_16 0x01
#define CS43130_CH_BIT_SIZE_24 0x02
#define CS43130_CH_BIT_SIZE_32 0x03
/* PLL */
#define CS43130_PLL_START_MASK 0x01
#define CS43130_PLL_MODE_MASK 0x02
#define CS43130_PLL_MODE_SHIFT 1
#define CS43130_PLL_REF_PREDIV_MASK 0x3
#define CS43130_SP_STP_MASK 0x10
#define CS43130_SP_STP_SHIFT 4
#define CS43130_SP_5050_MASK 0x08
#define CS43130_SP_5050_SHIFT 3
#define CS43130_SP_FSD_MASK 0x07
#define CS43130_SP_MODE_MASK 0x10
#define CS43130_SP_MODE_SHIFT 4
#define CS43130_SP_SCPOL_OUT_MASK 0x08
#define CS43130_SP_SCPOL_OUT_SHIFT 3
#define CS43130_SP_SCPOL_IN_MASK 0x04
#define CS43130_SP_SCPOL_IN_SHIFT 2
#define CS43130_SP_LCPOL_OUT_MASK 0x02
#define CS43130_SP_LCPOL_OUT_SHIFT 1
#define CS43130_SP_LCPOL_IN_MASK 0x01
#define CS43130_SP_LCPOL_IN_SHIFT 0
/* Reg CS43130_PWDN_CTL */
#define CS43130_PDN_XSP_MASK 0x80
#define CS43130_PDN_XSP_SHIFT 7
#define CS43130_PDN_ASP_MASK 0x40
#define CS43130_PDN_ASP_SHIFT 6
#define CS43130_PDN_DSPIF_MASK 0x20
#define CS43130_PDN_DSDIF_SHIFT 5
#define CS43130_PDN_HP_MASK 0x10
#define CS43130_PDN_HP_SHIFT 4
#define CS43130_PDN_XTAL_MASK 0x08
#define CS43130_PDN_XTAL_SHIFT 3
#define CS43130_PDN_PLL_MASK 0x04
#define CS43130_PDN_PLL_SHIFT 2
#define CS43130_PDN_CLKOUT_MASK 0x02
#define CS43130_PDN_CLKOUT_SHIFT 1
/* Reg CS43130_HP_OUT_CTL_1 */
#define CS43130_HP_IN_EN_SHIFT 3
#define CS43130_HP_IN_EN_MASK 0x08
/* Reg CS43130_PAD_INT_CFG */
#define CS43130_ASP_3ST_MASK 0x01
#define CS43130_XSP_3ST_MASK 0x02
/* Reg CS43130_PLL_SET_2 */
#define CS43130_PLL_DIV_DATA_MASK 0x000000FF
#define CS43130_PLL_DIV_FRAC_0_DATA_SHIFT 0
/* Reg CS43130_PLL_SET_3 */
#define CS43130_PLL_DIV_FRAC_1_DATA_SHIFT 8
/* Reg CS43130_PLL_SET_4 */
#define CS43130_PLL_DIV_FRAC_2_DATA_SHIFT 16
/* Reg CS43130_SP_DEN_1 */
#define CS43130_SP_M_LSB_DATA_MASK 0x00FF
#define CS43130_SP_M_LSB_DATA_SHIFT 0
/* Reg CS43130_SP_DEN_2 */
#define CS43130_SP_M_MSB_DATA_MASK 0xFF00
#define CS43130_SP_M_MSB_DATA_SHIFT 8
/* Reg CS43130_SP_NUM_1 */
#define CS43130_SP_N_LSB_DATA_MASK 0x00FF
#define CS43130_SP_N_LSB_DATA_SHIFT 0
/* Reg CS43130_SP_NUM_2 */
#define CS43130_SP_N_MSB_DATA_MASK 0xFF00
#define CS43130_SP_N_MSB_DATA_SHIFT 8
/* Reg CS43130_SP_LRCK_HI_TIME_1 */
#define CS43130_SP_LCHI_DATA_MASK 0x00FF
#define CS43130_SP_LCHI_LSB_DATA_SHIFT 0
/* Reg CS43130_SP_LRCK_HI_TIME_2 */
#define CS43130_SP_LCHI_MSB_DATA_SHIFT 8
/* Reg CS43130_SP_LRCK_PERIOD_1 */
#define CS43130_SP_LCPR_DATA_MASK 0x00FF
#define CS43130_SP_LCPR_LSB_DATA_SHIFT 0
/* Reg CS43130_SP_LRCK_PERIOD_2 */
#define CS43130_SP_LCPR_MSB_DATA_SHIFT 8
#define CS43130_PCM_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S24_LE | \
SNDRV_PCM_FMTBIT_S32_LE)
#define CS43130_DOP_FORMATS (SNDRV_PCM_FMTBIT_DSD_U16_LE | \
SNDRV_PCM_FMTBIT_DSD_U16_BE | \
SNDRV_PCM_FMTBIT_S24_LE)
/* Reg CS43130_CRYSTAL_SET */
#define CS43130_XTAL_IBIAS_MASK 0x07
/* Reg CS43130_PATH_CTL_1 */
#define CS43130_MUTE_MASK 0x03
#define CS43130_MUTE_EN 0x03
/* Reg CS43130_DSD_INT_CFG */
#define CS43130_DSD_MASTER 0x04
/* Reg CS43130_DSD_PATH_CTL_2 */
#define CS43130_DSD_SRC_MASK 0x60
#define CS43130_DSD_SRC_SHIFT 5
#define CS43130_DSD_EN_SHIFT 4
#define CS43130_DSD_SPEED_MASK 0x04
#define CS43130_DSD_SPEED_SHIFT 2
/* Reg CS43130_DSD_PCM_MIX_CTL */
#define CS43130_MIX_PCM_PREP_SHIFT 1
#define CS43130_MIX_PCM_PREP_MASK 0x02
#define CS43130_MIX_PCM_DSD_SHIFT 0
#define CS43130_MIX_PCM_DSD_MASK 0x01
/* Reg CS43130_HP_MEAS_LOAD */
#define CS43130_HP_MEAS_LOAD_MASK 0x000000FF
#define CS43130_HP_MEAS_LOAD_1_SHIFT 0
#define CS43130_HP_MEAS_LOAD_2_SHIFT 8
#define CS43130_MCLK_22M 22579200
#define CS43130_MCLK_24M 24576000
#define CS43130_LINEOUT_LOAD 5000
#define CS43130_JACK_LINEOUT (SND_JACK_MECHANICAL | SND_JACK_LINEOUT)
#define CS43130_JACK_HEADPHONE (SND_JACK_MECHANICAL | \
SND_JACK_HEADPHONE)
#define CS43130_JACK_MASK (SND_JACK_MECHANICAL | \
SND_JACK_LINEOUT | \
SND_JACK_HEADPHONE)
enum cs43130_dsd_src {
CS43130_DSD_SRC_DSD = 0,
CS43130_DSD_SRC_ASP = 2,
CS43130_DSD_SRC_XSP = 3,
};
enum cs43130_asp_rate {
CS43130_ASP_SPRATE_32K = 0,
CS43130_ASP_SPRATE_44_1K,
CS43130_ASP_SPRATE_48K,
CS43130_ASP_SPRATE_88_2K,
CS43130_ASP_SPRATE_96K,
CS43130_ASP_SPRATE_176_4K,
CS43130_ASP_SPRATE_192K,
CS43130_ASP_SPRATE_352_8K,
CS43130_ASP_SPRATE_384K,
};
enum cs43130_mclk_src_sel {
CS43130_MCLK_SRC_EXT = 0,
CS43130_MCLK_SRC_PLL,
CS43130_MCLK_SRC_RCO
};
enum cs43130_mclk_int_freq {
CS43130_MCLK_24P5 = 0,
CS43130_MCLK_22P5,
};
enum cs43130_xtal_ibias {
CS43130_XTAL_UNUSED = -1,
CS43130_XTAL_IBIAS_15UA = 2,
CS43130_XTAL_IBIAS_12_5UA = 4,
CS43130_XTAL_IBIAS_7_5UA = 6,
};
enum cs43130_dai_id {
CS43130_ASP_PCM_DAI = 0,
CS43130_ASP_DOP_DAI,
CS43130_XSP_DOP_DAI,
CS43130_XSP_DSD_DAI,
CS43130_DAI_ID_MAX,
};
struct cs43130_clk_gen {
unsigned int mclk_int;
int fs;
u16 den;
u16 num;
};
/* frm_size = 16 */
static const struct cs43130_clk_gen cs43130_16_clk_gen[] = {
{22579200, 32000, 441, 10,},
{22579200, 44100, 32, 1,},
{22579200, 48000, 147, 5,},
{22579200, 88200, 16, 1,},
{22579200, 96000, 147, 10,},
{22579200, 176400, 8, 1,},
{22579200, 192000, 147, 20,},
{22579200, 352800, 4, 1,},
{22579200, 384000, 147, 40,},
{24576000, 32000, 48, 1,},
{24576000, 44100, 5120, 147,},
{24576000, 48000, 32, 1,},
{24576000, 88200, 2560, 147,},
{24576000, 96000, 16, 1,},
{24576000, 176400, 1280, 147,},
{24576000, 192000, 8, 1,},
{24576000, 352800, 640, 147,},
{24576000, 384000, 4, 1,},
};
/* frm_size = 32 */
static const struct cs43130_clk_gen cs43130_32_clk_gen[] = {
{22579200, 32000, 441, 20,},
{22579200, 44100, 16, 1,},
{22579200, 48000, 147, 10,},
{22579200, 88200, 8, 1,},
{22579200, 96000, 147, 20,},
{22579200, 176400, 4, 1,},
{22579200, 192000, 147, 40,},
{22579200, 352800, 2, 1,},
{22579200, 384000, 147, 80,},
{24576000, 32000, 24, 1,},
{24576000, 44100, 2560, 147,},
{24576000, 48000, 16, 1,},
{24576000, 88200, 1280, 147,},
{24576000, 96000, 8, 1,},
{24576000, 176400, 640, 147,},
{24576000, 192000, 4, 1,},
{24576000, 352800, 320, 147,},
{24576000, 384000, 2, 1,},
};
/* frm_size = 48 */
static const struct cs43130_clk_gen cs43130_48_clk_gen[] = {
{22579200, 32000, 147, 100,},
{22579200, 44100, 32, 3,},
{22579200, 48000, 49, 5,},
{22579200, 88200, 16, 3,},
{22579200, 96000, 49, 10,},
{22579200, 176400, 8, 3,},
{22579200, 192000, 49, 20,},
{22579200, 352800, 4, 3,},
{22579200, 384000, 49, 40,},
{24576000, 32000, 16, 1,},
{24576000, 44100, 5120, 441,},
{24576000, 48000, 32, 3,},
{24576000, 88200, 2560, 441,},
{24576000, 96000, 16, 3,},
{24576000, 176400, 1280, 441,},
{24576000, 192000, 8, 3,},
{24576000, 352800, 640, 441,},
{24576000, 384000, 4, 3,},
};
/* frm_size = 64 */
static const struct cs43130_clk_gen cs43130_64_clk_gen[] = {
{22579200, 32000, 441, 40,},
{22579200, 44100, 8, 1,},
{22579200, 48000, 147, 20,},
{22579200, 88200, 4, 1,},
{22579200, 96000, 147, 40,},
{22579200, 176400, 2, 1,},
{22579200, 192000, 147, 80,},
{22579200, 352800, 1, 1,},
{24576000, 32000, 12, 1,},
{24576000, 44100, 1280, 147,},
{24576000, 48000, 8, 1,},
{24576000, 88200, 640, 147,},
{24576000, 96000, 4, 1,},
{24576000, 176400, 320, 147,},
{24576000, 192000, 2, 1,},
{24576000, 352800, 160, 147,},
{24576000, 384000, 1, 1,},
};
struct cs43130_bitwidth_map {
unsigned int bitwidth;
u8 sp_bit;
u8 ch_bit;
};
struct cs43130_rate_map {
int fs;
int val;
};
#define HP_LEFT 0
#define HP_RIGHT 1
#define CS43130_AC_FREQ 10
#define CS43130_DC_THRESHOLD 2
#define CS43130_NUM_SUPPLIES 5
static const char *const cs43130_supply_names[CS43130_NUM_SUPPLIES] = {
"VA",
"VP",
"VCP",
"VD",
"VL",
};
#define CS43130_NUM_INT 5 /* number of interrupt status reg */
struct cs43130_dai {
unsigned int sclk;
unsigned int dai_format;
unsigned int dai_mode;
};
struct cs43130_private {
struct snd_soc_codec *codec;
struct regmap *regmap;
struct regulator_bulk_data supplies[CS43130_NUM_SUPPLIES];
struct gpio_desc *reset_gpio;
unsigned int dev_id; /* codec device ID */
int xtal_ibias;
/* shared by both DAIs */
struct mutex clk_mutex;
int clk_req;
bool pll_bypass;
struct completion xtal_rdy;
struct completion pll_rdy;
unsigned int mclk;
unsigned int mclk_int;
int mclk_int_src;
/* DAI specific */
struct cs43130_dai dais[CS43130_DAI_ID_MAX];
/* HP load specific */
bool dc_meas;
bool ac_meas;
bool hpload_done;
struct completion hpload_evt;
unsigned int hpload_stat;
u16 hpload_dc[2];
u16 dc_threshold[CS43130_DC_THRESHOLD];
u16 ac_freq[CS43130_AC_FREQ];
u16 hpload_ac[CS43130_AC_FREQ][2];
struct workqueue_struct *wq;
struct work_struct work;
struct snd_soc_jack jack;
};
#endif /* __CS43130_H__ */

15
sound/soc/codecs/cs53l30.c
View File

@ -842,8 +842,7 @@ static int cs53l30_mute_stream(struct snd_soc_dai *dai, int mute, int stream)
{
struct cs53l30_private *priv = snd_soc_codec_get_drvdata(dai->codec);
if (priv->mute_gpio)
gpiod_set_value_cansleep(priv->mute_gpio, mute);
gpiod_set_value_cansleep(priv->mute_gpio, mute);
return 0;
}
@ -960,8 +959,7 @@ static int cs53l30_i2c_probe(struct i2c_client *client,
goto error;
}
if (cs53l30->reset_gpio)
gpiod_set_value_cansleep(cs53l30->reset_gpio, 1);
gpiod_set_value_cansleep(cs53l30->reset_gpio, 1);
i2c_set_clientdata(client, cs53l30);
@ -1056,8 +1054,7 @@ static int cs53l30_i2c_remove(struct i2c_client *client)
snd_soc_unregister_codec(&client->dev);
/* Hold down reset */
if (cs53l30->reset_gpio)
gpiod_set_value_cansleep(cs53l30->reset_gpio, 0);
gpiod_set_value_cansleep(cs53l30->reset_gpio, 0);
regulator_bulk_disable(ARRAY_SIZE(cs53l30->supplies),
cs53l30->supplies);
@ -1073,8 +1070,7 @@ static int cs53l30_runtime_suspend(struct device *dev)
regcache_cache_only(cs53l30->regmap, true);
/* Hold down reset */
if (cs53l30->reset_gpio)
gpiod_set_value_cansleep(cs53l30->reset_gpio, 0);
gpiod_set_value_cansleep(cs53l30->reset_gpio, 0);
regulator_bulk_disable(ARRAY_SIZE(cs53l30->supplies),
cs53l30->supplies);
@ -1094,8 +1090,7 @@ static int cs53l30_runtime_resume(struct device *dev)
return ret;
}
if (cs53l30->reset_gpio)
gpiod_set_value_cansleep(cs53l30->reset_gpio, 1);
gpiod_set_value_cansleep(cs53l30->reset_gpio, 1);
regcache_cache_only(cs53l30->regmap, false);
ret = regcache_sync(cs53l30->regmap);

6
sound/soc/davinci/davinci-mcasp.c
View File

@ -1602,8 +1602,6 @@ static struct davinci_mcasp_pdata *davinci_mcasp_set_pdata_from_of(
pdata = devm_kmemdup(&pdev->dev, match->data, sizeof(*pdata),
GFP_KERNEL);
if (!pdata) {
dev_err(&pdev->dev,
"Failed to allocate memory for pdata\n");
ret = -ENOMEM;
return pdata;
}
@ -1853,6 +1851,10 @@ static int davinci_mcasp_probe(struct platform_device *pdev)
mcasp->context.xrsr_regs = devm_kzalloc(&pdev->dev,
sizeof(u32) * mcasp->num_serializer,
GFP_KERNEL);
if (!mcasp->context.xrsr_regs) {
ret = -ENOMEM;
goto err;
}
#endif
mcasp->serial_dir = pdata->serial_dir;
mcasp->version = pdata->version;

5
sound/soc/davinci/davinci-vcif.c
View File

@ -210,11 +210,8 @@ static int davinci_vcif_probe(struct platform_device *pdev)
davinci_vcif_dev = devm_kzalloc(&pdev->dev,
sizeof(struct davinci_vcif_dev),
GFP_KERNEL);
if (!davinci_vcif_dev) {
dev_dbg(&pdev->dev,
"could not allocate memory for private data\n");
if (!davinci_vcif_dev)
return -ENOMEM;
}
/* DMA tx params */
davinci_vcif_dev->davinci_vc = davinci_vc;