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Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus

Browse Source 
Pull MIPS updates from Ralf Baechle:
 - Some minor work bringing the Cobalt MIPS platforms in line with other
   MIPS platforms
 - Make vmlinux.32 and vmlinux.64 build messages less verbose
 - Always register the R4k clocksource when selected, the clock source's
   rating will decide if this or another clock source is actually going
   to be used
 - Drop support for the Cisco (formerly Scientific Atlanta) PowerTV
   platform.  There appears to be nobody left who cares and the USB
   driver went stale while waiting for years to be merged
 - Some cleanup of Loongson 2 related #ifdefery
 - Various minor cleanups
 - Major rework on all things related to tracing / ptrace on MIPS,
   including switching the MIPS ELF core dumper to regsets, enabling the
   entries for SIGSYS in struct siginfo for MIPS, enabling ftrace
   syscall trace points
 - Some more work to bring DECstation support code in line with other
   more modern code
 - Report the name of the detected CPU, not just its CP0 PrID value
 - Some more BCM 47xx and atheros ath79xx work
 - Support for compressed kernels using the XZ compression scheme

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (53 commits)
  MIPS: remove duplicate define
  MIPS: Random whitespace clean-ups
  MIPS: traps: Reformat notify_die invocations to 80 columns.
  MIPS: Print correct PC in trace dump after NMI exception
  MIPS: kernel: cpu-probe: Report CPU id during probe
  MIPS: Remove unused defines in piix4.h
  MIPS: Get rid of hard-coded values for Malta PIIX4 fixups
  MIPS: Always register R4K clock when selected
  MIPS: Loongson: Get rid of Loongson 2 #ifdefery all over arch/mips.
  MIPS: cacheops.h: Increase indentation by one tab.
  MIPS: Remove bogus BUG_ON()
  MIPS: PowerTV: Remove support code.
  MIPS: ftrace: Add support for syscall tracepoints.
  MIPS: ptrace: Switch syscall reporting to tracehook_report_syscall_entry().
  MIPS: Move audit_arch() helper function to __syscall_get_arch().
  MIPS: Enable HAVE_ARCH_TRACEHOOK.
  MIPS: Switch ELF core dumper to use regsets.
  MIPS: Implement task_user_regset_view.
  MIPS: ptrace: Use tracehook helpers.
  MIPS: O32 / 32-bit: Always copy 4 stack arguments.
  ...
This commit is contained in:
Linus Torvalds 2013-11-08 08:32:58 +09:00
commit 3ae423fe47
133 changed files with 1979 additions and 7085 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
arch/mips/Kbuild.platforms
View File

@ -20,7 +20,6 @@ platforms += mti-sead3
platforms += netlogic
platforms += pmcs-msp71xx
platforms += pnx833x
platforms += powertv
platforms += ralink
platforms += rb532
platforms += sgi-ip22

27
arch/mips/Kconfig
View File

@ -8,6 +8,7 @@ config MIPS
select HAVE_PERF_EVENTS
select PERF_USE_VMALLOC
select HAVE_ARCH_KGDB
select HAVE_ARCH_TRACEHOOK
select ARCH_HAVE_CUSTOM_GPIO_H
select HAVE_FUNCTION_TRACER
select HAVE_FUNCTION_TRACE_MCOUNT_TEST
@ -18,6 +19,7 @@ config MIPS
select HAVE_KPROBES
select HAVE_KRETPROBES
select HAVE_DEBUG_KMEMLEAK
select HAVE_SYSCALL_TRACEPOINTS
select ARCH_BINFMT_ELF_RANDOMIZE_PIE
select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES && 64BIT
select RTC_LIB if !MACH_LOONGSON
@ -146,6 +148,7 @@ config MIPS_COBALT
select CSRC_R4K
select CEVT_GT641XX
select DMA_NONCOHERENT
select EARLY_PRINTK_8250 if EARLY_PRINTK
select HW_HAS_PCI
select I8253
select I8259
@ -412,23 +415,6 @@ config PMC_MSP
of integrated peripherals, interfaces and DSPs in addition to
a variety of MIPS cores.
config POWERTV
bool "Cisco PowerTV"
select BOOT_ELF32
select CEVT_R4K
select CPU_MIPSR2_IRQ_VI
select CPU_MIPSR2_IRQ_EI
select CSRC_POWERTV
select DMA_NONCOHERENT
select HW_HAS_PCI
select SYS_HAS_CPU_MIPS32_R2
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_HIGHMEM
select USB_OHCI_LITTLE_ENDIAN
help
This enables support for the Cisco PowerTV Platform.
config RALINK
bool "Ralink based machines"
select CEVT_R4K
@ -811,7 +797,6 @@ source "arch/mips/jz4740/Kconfig"
source "arch/mips/lantiq/Kconfig"
source "arch/mips/lasat/Kconfig"
source "arch/mips/pmcs-msp71xx/Kconfig"
source "arch/mips/powertv/Kconfig"
source "arch/mips/ralink/Kconfig"
source "arch/mips/sgi-ip27/Kconfig"
source "arch/mips/sibyte/Kconfig"
@ -890,9 +875,6 @@ config CSRC_BCM1480
config CSRC_IOASIC
bool
config CSRC_POWERTV
bool
config CSRC_R4K
bool
@ -1489,8 +1471,10 @@ config SYS_SUPPORTS_ZBOOT
bool
select HAVE_KERNEL_GZIP
select HAVE_KERNEL_BZIP2
select HAVE_KERNEL_LZ4
select HAVE_KERNEL_LZMA
select HAVE_KERNEL_LZO
select HAVE_KERNEL_XZ
config SYS_SUPPORTS_ZBOOT_UART16550
bool
@ -1977,6 +1961,7 @@ config MIPS_VPE_APSP_API
config MIPS_CMP
bool "MIPS CMP framework support"
depends on SYS_SUPPORTS_MIPS_CMP
select SMP
select SYNC_R4K
select SYS_SUPPORTS_SMP
select SYS_SUPPORTS_SCHED_SMT if SMP

8
arch/mips/Kconfig.debug
View File

@ -20,6 +20,14 @@ config EARLY_PRINTK
doesn't cooperate with an X server. You should normally say N here,
unless you want to debug such a crash.
config EARLY_PRINTK_8250
bool "8250/16550 and compatible serial early printk driver"
depends on EARLY_PRINTK
default n
help
If you say Y here, it will be possible to use a 8250/16550 serial
port as the boot console.
config CMDLINE_BOOL
bool "Built-in kernel command line"
default n

14
arch/mips/Makefile
View File

@ -285,15 +285,19 @@ endif
# Other need ECOFF, so we build a 32-bit ELF binary for them which we then
# convert to ECOFF using elf2ecoff.
#
quiet_cmd_32 = OBJCOPY $@
cmd_32 = $(OBJCOPY) -O $(32bit-bfd) $(OBJCOPYFLAGS) $< $@
vmlinux.32: vmlinux
$(OBJCOPY) -O $(32bit-bfd) $(OBJCOPYFLAGS) $< $@
$(call cmd,32)
#
# The 64-bit ELF tools are pretty broken so at this time we generate 64-bit
# ELF files from 32-bit files by conversion.
#
quiet_cmd_64 = OBJCOPY $@
cmd_64 = $(OBJCOPY) -O $(64bit-bfd) $(OBJCOPYFLAGS) $< $@
vmlinux.64: vmlinux
$(OBJCOPY) -O $(64bit-bfd) $(OBJCOPYFLAGS) $< $@
$(call cmd,64)
all: $(all-y)
@ -302,10 +306,16 @@ $(boot-y): $(vmlinux-32) FORCE
$(Q)$(MAKE) $(build)=arch/mips/boot VMLINUX=$(vmlinux-32) \
$(bootvars-y) arch/mips/boot/$@
ifdef CONFIG_SYS_SUPPORTS_ZBOOT
# boot/compressed
$(bootz-y): $(vmlinux-32) FORCE
$(Q)$(MAKE) $(build)=arch/mips/boot/compressed \
$(bootvars-y) 32bit-bfd=$(32bit-bfd) $@
else
vmlinuz: FORCE
@echo ' CONFIG_SYS_SUPPORTS_ZBOOT is not enabled'
/bin/false
endif
CLEAN_FILES += vmlinux.32 vmlinux.64

2
arch/mips/alchemy/devboards/db1235.c
View File

@ -59,7 +59,7 @@ void __init board_setup(void)
ret = -ENODEV;
}
if (ret)
panic("cannot initialize board support\n");
panic("cannot initialize board support");
}
int __init db1235_arch_init(void)

6
arch/mips/ath79/dev-common.c
View File

@ -20,7 +20,6 @@
#include <asm/mach-ath79/ath79.h>
#include <asm/mach-ath79/ar71xx_regs.h>
#include <asm/mach-ath79/ar933x_uart_platform.h>
#include "common.h"
#include "dev-common.h"
@ -68,15 +67,11 @@ static struct resource ar933x_uart_resources[] = {
},
};
static struct ar933x_uart_platform_data ar933x_uart_data;
static struct platform_device ar933x_uart_device = {
.name = "ar933x-uart",
.id = -1,
.resource = ar933x_uart_resources,
.num_resources = ARRAY_SIZE(ar933x_uart_resources),
.dev = {
.platform_data = &ar933x_uart_data,
},
};
void __init ath79_register_uart(void)
@ -93,7 +88,6 @@ void __init ath79_register_uart(void)
ath79_uart_data[0].uartclk = uart_clk_rate;
platform_device_register(&ath79_uart_device);
} else if (soc_is_ar933x()) {
ar933x_uart_data.uartclk = uart_clk_rate;
platform_device_register(&ar933x_uart_device);
} else {
BUG();

1
arch/mips/bcm47xx/Makefile
View File

@ -4,4 +4,5 @@
#
obj-y += irq.o nvram.o prom.o serial.o setup.o time.o sprom.o
obj-y += board.o
obj-$(CONFIG_BCM47XX_SSB) += wgt634u.o

309
arch/mips/bcm47xx/board.c Normal file
View File

@ -0,0 +1,309 @@
#include <linux/export.h>
#include <linux/string.h>
#include <bcm47xx_board.h>
#include <bcm47xx_nvram.h>
struct bcm47xx_board_type {
const enum bcm47xx_board board;
const char *name;
};
struct bcm47xx_board_type_list1 {
struct bcm47xx_board_type board;
const char *value1;
};
struct bcm47xx_board_type_list2 {
struct bcm47xx_board_type board;
const char *value1;
const char *value2;
};
struct bcm47xx_board_type_list3 {
struct bcm47xx_board_type board;
const char *value1;
const char *value2;
const char *value3;
};
struct bcm47xx_board_store {
enum bcm47xx_board board;
char name[BCM47XX_BOARD_MAX_NAME];
};
/* model_name */
static const
struct bcm47xx_board_type_list1 bcm47xx_board_list_model_name[] __initconst = {
{{BCM47XX_BOARD_DLINK_DIR130, "D-Link DIR-130"}, "DIR-130"},
{{BCM47XX_BOARD_DLINK_DIR330, "D-Link DIR-330"}, "DIR-330"},
{ {0}, 0},
};
/* model_no */
static const
struct bcm47xx_board_type_list1 bcm47xx_board_list_model_no[] __initconst = {
{{BCM47XX_BOARD_ASUS_WL700GE, "Asus WL700"}, "WL700"},
{ {0}, 0},
};
/* machine_name */
static const
struct bcm47xx_board_type_list1 bcm47xx_board_list_machine_name[] __initconst = {
{{BCM47XX_BOARD_LINKSYS_WRTSL54GS, "Linksys WRTSL54GS"}, "WRTSL54GS"},
{ {0}, 0},
};
/* hardware_version */
static const
struct bcm47xx_board_type_list1 bcm47xx_board_list_hardware_version[] __initconst = {
{{BCM47XX_BOARD_ASUS_RTN16, "Asus RT-N16"}, "RT-N16-"},
{{BCM47XX_BOARD_ASUS_WL320GE, "Asus WL320GE"}, "WL320G-"},
{{BCM47XX_BOARD_ASUS_WL330GE, "Asus WL330GE"}, "WL330GE-"},
{{BCM47XX_BOARD_ASUS_WL500GD, "Asus WL500GD"}, "WL500gd-"},
{{BCM47XX_BOARD_ASUS_WL500GPV1, "Asus WL500GP V1"}, "WL500gp-"},
{{BCM47XX_BOARD_ASUS_WL500GPV2, "Asus WL500GP V2"}, "WL500GPV2-"},
{{BCM47XX_BOARD_ASUS_WL500W, "Asus WL500W"}, "WL500gW-"},
{{BCM47XX_BOARD_ASUS_WL520GC, "Asus WL520GC"}, "WL520GC-"},
{{BCM47XX_BOARD_ASUS_WL520GU, "Asus WL520GU"}, "WL520GU-"},
{{BCM47XX_BOARD_BELKIN_F7D4301, "Belkin F7D4301"}, "F7D4301"},
{ {0}, 0},
};
/* productid */
static const
struct bcm47xx_board_type_list1 bcm47xx_board_list_productid[] __initconst = {
{{BCM47XX_BOARD_ASUS_RTAC66U, "Asus RT-AC66U"}, "RT-AC66U"},
{{BCM47XX_BOARD_ASUS_RTN10, "Asus RT-N10"}, "RT-N10"},
{{BCM47XX_BOARD_ASUS_RTN10D, "Asus RT-N10D"}, "RT-N10D"},
{{BCM47XX_BOARD_ASUS_RTN10U, "Asus RT-N10U"}, "RT-N10U"},
{{BCM47XX_BOARD_ASUS_RTN12, "Asus RT-N12"}, "RT-N12"},
{{BCM47XX_BOARD_ASUS_RTN12B1, "Asus RT-N12B1"}, "RT-N12B1"},
{{BCM47XX_BOARD_ASUS_RTN12C1, "Asus RT-N12C1"}, "RT-N12C1"},
{{BCM47XX_BOARD_ASUS_RTN12D1, "Asus RT-N12D1"}, "RT-N12D1"},
{{BCM47XX_BOARD_ASUS_RTN12HP, "Asus RT-N12HP"}, "RT-N12HP"},
{{BCM47XX_BOARD_ASUS_RTN15U, "Asus RT-N15U"}, "RT-N15U"},
{{BCM47XX_BOARD_ASUS_RTN16, "Asus RT-N16"}, "RT-N16"},
{{BCM47XX_BOARD_ASUS_RTN53, "Asus RT-N53"}, "RT-N53"},
{{BCM47XX_BOARD_ASUS_RTN66U, "Asus RT-N66U"}, "RT-N66U"},
{{BCM47XX_BOARD_ASUS_WL300G, "Asus WL300G"}, "WL300g"},
{{BCM47XX_BOARD_ASUS_WLHDD, "Asus WLHDD"}, "WLHDD"},
{ {0}, 0},
};
/* ModelId */
static const
struct bcm47xx_board_type_list1 bcm47xx_board_list_ModelId[] __initconst = {
{{BCM47XX_BOARD_DELL_TM2300, "Dell WX-5565"}, "WX-5565"},
{{BCM47XX_BOARD_MOTOROLA_WE800G, "Motorola WE800G"}, "WE800G"},
{{BCM47XX_BOARD_MOTOROLA_WR850GP, "Motorola WR850GP"}, "WR850GP"},
{{BCM47XX_BOARD_MOTOROLA_WR850GV2V3, "Motorola WR850G"}, "WR850G"},
{ {0}, 0},
};
/* melco_id or buf1falo_id */
static const
struct bcm47xx_board_type_list1 bcm47xx_board_list_melco_id[] __initconst = {
{{BCM47XX_BOARD_BUFFALO_WBR2_G54, "Buffalo WBR2-G54"}, "29bb0332"},
{{BCM47XX_BOARD_BUFFALO_WHR2_A54G54, "Buffalo WHR2-A54G54"}, "290441dd"},
{{BCM47XX_BOARD_BUFFALO_WHR_G125, "Buffalo WHR-G125"}, "32093"},
{{BCM47XX_BOARD_BUFFALO_WHR_G54S, "Buffalo WHR-G54S"}, "30182"},
{{BCM47XX_BOARD_BUFFALO_WHR_HP_G54, "Buffalo WHR-HP-G54"}, "30189"},
{{BCM47XX_BOARD_BUFFALO_WLA2_G54L, "Buffalo WLA2-G54L"}, "29129"},
{{BCM47XX_BOARD_BUFFALO_WZR_G300N, "Buffalo WZR-G300N"}, "31120"},
{{BCM47XX_BOARD_BUFFALO_WZR_RS_G54, "Buffalo WZR-RS-G54"}, "30083"},
{{BCM47XX_BOARD_BUFFALO_WZR_RS_G54HP, "Buffalo WZR-RS-G54HP"}, "30103"},
{ {0}, 0},
};
/* boot_hw_model, boot_hw_ver */
static const
struct bcm47xx_board_type_list2 bcm47xx_board_list_boot_hw[] __initconst = {
/* like WRT160N v3.0 */
{{BCM47XX_BOARD_CISCO_M10V1, "Cisco M10"}, "M10", "1.0"},
/* like WRT310N v2.0 */
{{BCM47XX_BOARD_CISCO_M20V1, "Cisco M20"}, "M20", "1.0"},
{{BCM47XX_BOARD_LINKSYS_E900V1, "Linksys E900 V1"}, "E900", "1.0"},
/* like WRT160N v3.0 */
{{BCM47XX_BOARD_LINKSYS_E1000V1, "Linksys E1000 V1"}, "E100", "1.0"},
{{BCM47XX_BOARD_LINKSYS_E1000V2, "Linksys E1000 V2"}, "E1000", "2.0"},
{{BCM47XX_BOARD_LINKSYS_E1000V21, "Linksys E1000 V2.1"}, "E1000", "2.1"},
{{BCM47XX_BOARD_LINKSYS_E1200V2, "Linksys E1200 V2"}, "E1200", "2.0"},
{{BCM47XX_BOARD_LINKSYS_E2000V1, "Linksys E2000 V1"}, "Linksys E2000", "1.0"},
/* like WRT610N v2.0 */
{{BCM47XX_BOARD_LINKSYS_E3000V1, "Linksys E3000 V1"}, "E300", "1.0"},
{{BCM47XX_BOARD_LINKSYS_E3200V1, "Linksys E3200 V1"}, "E3200", "1.0"},
{{BCM47XX_BOARD_LINKSYS_E4200V1, "Linksys E4200 V1"}, "E4200", "1.0"},
{{BCM47XX_BOARD_LINKSYS_WRT150NV11, "Linksys WRT150N V1.1"}, "WRT150N", "1.1"},
{{BCM47XX_BOARD_LINKSYS_WRT150NV1, "Linksys WRT150N V1"}, "WRT150N", "1"},
{{BCM47XX_BOARD_LINKSYS_WRT160NV1, "Linksys WRT160N V1"}, "WRT160N", "1.0"},
{{BCM47XX_BOARD_LINKSYS_WRT160NV3, "Linksys WRT160N V3"}, "WRT160N", "3.0"},
{{BCM47XX_BOARD_LINKSYS_WRT300NV11, "Linksys WRT300N V1.1"}, "WRT300N", "1.1"},
{{BCM47XX_BOARD_LINKSYS_WRT310NV1, "Linksys WRT310N V1"}, "WRT310N", "1.0"},
{{BCM47XX_BOARD_LINKSYS_WRT310NV2, "Linksys WRT310N V2"}, "WRT310N", "2.0"},
{{BCM47XX_BOARD_LINKSYS_WRT54G3GV2, "Linksys WRT54G3GV2-VF"}, "WRT54G3GV2-VF", "1.0"},
{{BCM47XX_BOARD_LINKSYS_WRT610NV1, "Linksys WRT610N V1"}, "WRT610N", "1.0"},
{{BCM47XX_BOARD_LINKSYS_WRT610NV2, "Linksys WRT610N V2"}, "WRT610N", "2.0"},
{ {0}, 0},
};
/* board_id */
static const
struct bcm47xx_board_type_list1 bcm47xx_board_list_board_id[] __initconst = {
{{BCM47XX_BOARD_NETGEAR_WGR614V8, "Netgear WGR614 V8"}, "U12H072T00_NETGEAR"},
{{BCM47XX_BOARD_NETGEAR_WGR614V9, "Netgear WGR614 V9"}, "U12H094T00_NETGEAR"},
{{BCM47XX_BOARD_NETGEAR_WNDR3300, "Netgear WNDR3300"}, "U12H093T00_NETGEAR"},
{{BCM47XX_BOARD_NETGEAR_WNDR3400V1, "Netgear WNDR3400 V1"}, "U12H155T00_NETGEAR"},
{{BCM47XX_BOARD_NETGEAR_WNDR3400V2, "Netgear WNDR3400 V2"}, "U12H187T00_NETGEAR"},
{{BCM47XX_BOARD_NETGEAR_WNDR3400VCNA, "Netgear WNDR3400 Vcna"}, "U12H155T01_NETGEAR"},
{{BCM47XX_BOARD_NETGEAR_WNDR3700V3, "Netgear WNDR3700 V3"}, "U12H194T00_NETGEAR"},
{{BCM47XX_BOARD_NETGEAR_WNDR4000, "Netgear WNDR4000"}, "U12H181T00_NETGEAR"},
{{BCM47XX_BOARD_NETGEAR_WNDR4500V1, "Netgear WNDR4500 V1"}, "U12H189T00_NETGEAR"},
{{BCM47XX_BOARD_NETGEAR_WNDR4500V2, "Netgear WNDR4500 V2"}, "U12H224T00_NETGEAR"},
{{BCM47XX_BOARD_NETGEAR_WNR2000, "Netgear WNR2000"}, "U12H114T00_NETGEAR"},
{{BCM47XX_BOARD_NETGEAR_WNR3500L, "Netgear WNR3500L"}, "U12H136T99_NETGEAR"},
{{BCM47XX_BOARD_NETGEAR_WNR3500U, "Netgear WNR3500U"}, "U12H136T00_NETGEAR"},
{{BCM47XX_BOARD_NETGEAR_WNR3500V2, "Netgear WNR3500 V2"}, "U12H127T00_NETGEAR"},
{{BCM47XX_BOARD_NETGEAR_WNR3500V2VC, "Netgear WNR3500 V2vc"}, "U12H127T70_NETGEAR"},
{{BCM47XX_BOARD_NETGEAR_WNR834BV2, "Netgear WNR834B V2"}, "U12H081T00_NETGEAR"},
{ {0}, 0},
};
/* boardtype, boardnum, boardrev */
static const
struct bcm47xx_board_type_list3 bcm47xx_board_list_board[] __initconst = {
{{BCM47XX_BOARD_HUAWEI_E970, "Huawei E970"}, "0x048e", "0x5347", "0x11"},
{{BCM47XX_BOARD_PHICOMM_M1, "Phicomm M1"}, "0x0590", "80", "0x1104"},
{{BCM47XX_BOARD_ZTE_H218N, "ZTE H218N"}, "0x053d", "1234", "0x1305"},
{ {0}, 0},
};
static const
struct bcm47xx_board_type bcm47xx_board_unknown[] __initconst = {
{BCM47XX_BOARD_UNKNOWN, "Unknown Board"},
};
static struct bcm47xx_board_store bcm47xx_board = {BCM47XX_BOARD_NO, "Unknown Board"};
static __init const struct bcm47xx_board_type *bcm47xx_board_get_nvram(void)
{
char buf1[30];
char buf2[30];
char buf3[30];
const struct bcm47xx_board_type_list1 *e1;
const struct bcm47xx_board_type_list2 *e2;
const struct bcm47xx_board_type_list3 *e3;
if (bcm47xx_nvram_getenv("model_name", buf1, sizeof(buf1)) >= 0) {
for (e1 = bcm47xx_board_list_model_name; e1->value1; e1++) {
if (!strcmp(buf1, e1->value1))
return &e1->board;
}
}
if (bcm47xx_nvram_getenv("model_no", buf1, sizeof(buf1)) >= 0) {
for (e1 = bcm47xx_board_list_model_no; e1->value1; e1++) {
if (strstarts(buf1, e1->value1))
return &e1->board;
}
}
if (bcm47xx_nvram_getenv("machine_name", buf1, sizeof(buf1)) >= 0) {
for (e1 = bcm47xx_board_list_machine_name; e1->value1; e1++) {
if (strstarts(buf1, e1->value1))
return &e1->board;
}
}
if (bcm47xx_nvram_getenv("hardware_version", buf1, sizeof(buf1)) >= 0) {
for (e1 = bcm47xx_board_list_hardware_version; e1->value1; e1++) {
if (strstarts(buf1, e1->value1))
return &e1->board;
}
}
if (bcm47xx_nvram_getenv("productid", buf1, sizeof(buf1)) >= 0) {
for (e1 = bcm47xx_board_list_productid; e1->value1; e1++) {
if (!strcmp(buf1, e1->value1))
return &e1->board;
}
}
if (bcm47xx_nvram_getenv("ModelId", buf1, sizeof(buf1)) >= 0) {
for (e1 = bcm47xx_board_list_ModelId; e1->value1; e1++) {
if (!strcmp(buf1, e1->value1))
return &e1->board;
}
}
if (bcm47xx_nvram_getenv("melco_id", buf1, sizeof(buf1)) >= 0 ||
bcm47xx_nvram_getenv("buf1falo_id", buf1, sizeof(buf1)) >= 0) {
/* buffalo hardware, check id for specific hardware matches */
for (e1 = bcm47xx_board_list_melco_id; e1->value1; e1++) {
if (!strcmp(buf1, e1->value1))
return &e1->board;
}
}
if (bcm47xx_nvram_getenv("boot_hw_model", buf1, sizeof(buf1)) >= 0 &&
bcm47xx_nvram_getenv("boot_hw_ver", buf2, sizeof(buf2)) >= 0) {
for (e2 = bcm47xx_board_list_boot_hw; e2->value1; e2++) {
if (!strcmp(buf1, e2->value1) &&
!strcmp(buf2, e2->value2))
return &e2->board;
}
}
if (bcm47xx_nvram_getenv("board_id", buf1, sizeof(buf1)) >= 0) {
for (e1 = bcm47xx_board_list_board_id; e1->value1; e1++) {
if (!strcmp(buf1, e1->value1))
return &e1->board;
}
}
if (bcm47xx_nvram_getenv("boardtype", buf1, sizeof(buf1)) >= 0 &&
bcm47xx_nvram_getenv("boardnum", buf2, sizeof(buf2)) >= 0 &&
bcm47xx_nvram_getenv("boardrev", buf3, sizeof(buf3)) >= 0) {
for (e3 = bcm47xx_board_list_board; e3->value1; e3++) {
if (!strcmp(buf1, e3->value1) &&
!strcmp(buf2, e3->value2) &&
!strcmp(buf3, e3->value3))
return &e3->board;
}
}
return bcm47xx_board_unknown;
}
void __init bcm47xx_board_detect(void)
{
int err;
char buf[10];
const struct bcm47xx_board_type *board_detected;
if (bcm47xx_board.board != BCM47XX_BOARD_NO)
return;
/* check if the nvram is available */
err = bcm47xx_nvram_getenv("boardtype", buf, sizeof(buf));
/* init of nvram failed, probably too early now */
if (err == -ENXIO) {
return;
}
board_detected = bcm47xx_board_get_nvram();
bcm47xx_board.board = board_detected->board;
strlcpy(bcm47xx_board.name, board_detected->name,
BCM47XX_BOARD_MAX_NAME);
}
enum bcm47xx_board bcm47xx_board_get(void)
{
return bcm47xx_board.board;
}
EXPORT_SYMBOL(bcm47xx_board_get);
const char *bcm47xx_board_get_name(void)
{
return bcm47xx_board.name;
}
EXPORT_SYMBOL(bcm47xx_board_get_name);

20
arch/mips/bcm47xx/nvram.c
View File

@ -190,3 +190,23 @@ int bcm47xx_nvram_getenv(char *name, char *val, size_t val_len)
return -ENOENT;
}
EXPORT_SYMBOL(bcm47xx_nvram_getenv);
int bcm47xx_nvram_gpio_pin(const char *name)
{
int i, err;
char nvram_var[10];
char buf[30];
for (i = 0; i < 16; i++) {
err = snprintf(nvram_var, sizeof(nvram_var), "gpio%i", i);
if (err <= 0)
continue;
err = bcm47xx_nvram_getenv(nvram_var, buf, sizeof(buf));
if (err <= 0)
continue;
if (!strcmp(name, buf))
return i;
}
return -ENOENT;
}
EXPORT_SYMBOL(bcm47xx_nvram_gpio_pin);

27
arch/mips/bcm47xx/prom.c
View File

@ -32,12 +32,37 @@
#include <asm/bootinfo.h>
#include <asm/fw/cfe/cfe_api.h>
#include <asm/fw/cfe/cfe_error.h>
#include <bcm47xx.h>
#include <bcm47xx_board.h>
static int cfe_cons_handle;
static u16 get_chip_id(void)
{
switch (bcm47xx_bus_type) {
#ifdef CONFIG_BCM47XX_SSB
case BCM47XX_BUS_TYPE_SSB:
return bcm47xx_bus.ssb.chip_id;
#endif
#ifdef CONFIG_BCM47XX_BCMA
case BCM47XX_BUS_TYPE_BCMA:
return bcm47xx_bus.bcma.bus.chipinfo.id;
#endif
}
return 0;
}
const char *get_system_type(void)
{
return "Broadcom BCM47XX";
static char buf[50];
u16 chip_id = get_chip_id();
snprintf(buf, sizeof(buf),
(chip_id > 0x9999) ? "Broadcom BCM%d (%s)" :
"Broadcom BCM%04X (%s)",
chip_id, bcm47xx_board_get_name());
return buf;
}
void prom_putchar(char c)

2
arch/mips/bcm47xx/setup.c
View File

@ -36,6 +36,7 @@
#include <asm/time.h>
#include <bcm47xx.h>
#include <bcm47xx_nvram.h>
#include <bcm47xx_board.h>
union bcm47xx_bus bcm47xx_bus;
EXPORT_SYMBOL(bcm47xx_bus);
@ -221,6 +222,7 @@ void __init plat_mem_setup(void)
_machine_restart = bcm47xx_machine_restart;
_machine_halt = bcm47xx_machine_halt;
pm_power_off = bcm47xx_machine_halt;
bcm47xx_board_detect();
}
static int __init bcm47xx_register_bus_complete(void)

23
arch/mips/bcm47xx/time.c
View File

@ -27,10 +27,16 @@
#include <linux/ssb/ssb.h>
#include <asm/time.h>
#include <bcm47xx.h>
#include <bcm47xx_nvram.h>
#include <bcm47xx_board.h>
void __init plat_time_init(void)
{
unsigned long hz = 0;
u16 chip_id = 0;
char buf[10];
int len;
enum bcm47xx_board board = bcm47xx_board_get();
/*
* Use deterministic values for initial counter interrupt
@ -43,15 +49,32 @@ void __init plat_time_init(void)
#ifdef CONFIG_BCM47XX_SSB
case BCM47XX_BUS_TYPE_SSB:
hz = ssb_cpu_clock(&bcm47xx_bus.ssb.mipscore) / 2;
chip_id = bcm47xx_bus.ssb.chip_id;
break;
#endif
#ifdef CONFIG_BCM47XX_BCMA
case BCM47XX_BUS_TYPE_BCMA:
hz = bcma_cpu_clock(&bcm47xx_bus.bcma.bus.drv_mips) / 2;
chip_id = bcm47xx_bus.bcma.bus.chipinfo.id;
break;
#endif
}
if (chip_id == 0x5354) {
len = bcm47xx_nvram_getenv("clkfreq", buf, sizeof(buf));
if (len >= 0 && !strncmp(buf, "200", 4))
hz = 100000000;
}
switch (board) {
case BCM47XX_BOARD_ASUS_WL520GC:
case BCM47XX_BOARD_ASUS_WL520GU:
hz = 100000000;
break;
default:
break;
}
if (!hz)
hz = 100000000;

6
arch/mips/boot/compressed/Makefile
View File

@ -37,6 +37,10 @@ vmlinuzobjs-$(CONFIG_SYS_SUPPORTS_ZBOOT_UART16550) += $(obj)/uart-16550.o
vmlinuzobjs-$(CONFIG_MIPS_ALCHEMY) += $(obj)/uart-alchemy.o
endif
ifdef CONFIG_KERNEL_XZ
vmlinuzobjs-y += $(obj)/../../lib/ashldi3.o
endif
targets += vmlinux.bin
OBJCOPYFLAGS_vmlinux.bin := $(OBJCOPYFLAGS) -O binary -R .comment -S
$(obj)/vmlinux.bin: $(KBUILD_IMAGE) FORCE
@ -44,8 +48,10 @@ $(obj)/vmlinux.bin: $(KBUILD_IMAGE) FORCE
tool_$(CONFIG_KERNEL_GZIP) = gzip
tool_$(CONFIG_KERNEL_BZIP2) = bzip2
tool_$(CONFIG_KERNEL_LZ4) = lz4
tool_$(CONFIG_KERNEL_LZMA) = lzma
tool_$(CONFIG_KERNEL_LZO) = lzo
tool_$(CONFIG_KERNEL_XZ) = xzkern
targets += vmlinux.bin.z
$(obj)/vmlinux.bin.z: $(obj)/vmlinux.bin FORCE

13
arch/mips/boot/compressed/decompress.c
View File

@ -43,7 +43,8 @@ void error(char *x)
/* activate the code for pre-boot environment */
#define STATIC static
#ifdef CONFIG_KERNEL_GZIP
#if defined(CONFIG_KERNEL_GZIP) || defined(CONFIG_KERNEL_XZ) || \
defined(CONFIG_KERNEL_LZ4)
void *memcpy(void *dest, const void *src, size_t n)
{
int i;
@ -54,6 +55,8 @@ void *memcpy(void *dest, const void *src, size_t n)
d[i] = s[i];
return dest;
}
#endif
#ifdef CONFIG_KERNEL_GZIP
#include "../../../../lib/decompress_inflate.c"
#endif
@ -70,6 +73,10 @@ void *memset(void *s, int c, size_t n)
#include "../../../../lib/decompress_bunzip2.c"
#endif
#ifdef CONFIG_KERNEL_LZ4
#include "../../../../lib/decompress_unlz4.c"
#endif
#ifdef CONFIG_KERNEL_LZMA
#include "../../../../lib/decompress_unlzma.c"
#endif
@ -78,6 +85,10 @@ void *memset(void *s, int c, size_t n)
#include "../../../../lib/decompress_unlzo.c"
#endif
#ifdef CONFIG_KERNEL_XZ
#include "../../../../lib/decompress_unxz.c"
#endif
void decompress_kernel(unsigned long boot_heap_start)
{
unsigned long zimage_start, zimage_size;

5
arch/mips/boot/compressed/ld.script
View File

@ -8,6 +8,9 @@
OUTPUT_ARCH(mips)
ENTRY(start)
PHDRS {
text PT_LOAD FLAGS(7); /* RWX */
}
SECTIONS
{
/* Text and read-only data */
@ -15,7 +18,7 @@ SECTIONS
.text : {
*(.text)
*(.rodata)
}
}: text
/* End of text section */
/* Writable data */

1
arch/mips/boot/ecoff.h
View File

@ -12,7 +12,6 @@ typedef struct filehdr {
} FILHDR;
#define FILHSZ sizeof(FILHDR)
#define OMAGIC 0407
#define MIPSEBMAGIC 0x160
#define MIPSELMAGIC 0x162

4
arch/mips/cavium-octeon/setup.c
View File

@ -999,7 +999,7 @@ void __init plat_mem_setup(void)
if (total == 0)
panic("Unable to allocate memory from "
"cvmx_bootmem_phy_alloc\n");
"cvmx_bootmem_phy_alloc");
}
/*
@ -1081,7 +1081,7 @@ void __init device_tree_init(void)
/* Copy the default tree from init memory. */
initial_boot_params = early_init_dt_alloc_memory_arch(dt_size, 8);
if (initial_boot_params == NULL)
panic("Could not allocate initial_boot_params\n");
panic("Could not allocate initial_boot_params");
memcpy(initial_boot_params, fdt, dt_size);
if (do_prune) {

1
arch/mips/cobalt/Makefile
View File

@ -5,5 +5,4 @@
obj-y := buttons.o irq.o lcd.o led.o reset.o rtc.o serial.o setup.o time.o
obj-$(CONFIG_PCI) += pci.o
obj-$(CONFIG_EARLY_PRINTK) += console.o
obj-$(CONFIG_MTD_PHYSMAP) += mtd.o

20
arch/mips/cobalt/console.c
View File

@ -1,20 +0,0 @@
/*
* (C) P. Horton 2006
*/
#include <linux/io.h>
#include <linux/serial_reg.h>
#include <cobalt.h>
#define UART_BASE ((void __iomem *)CKSEG1ADDR(0x1c800000))
void prom_putchar(char c)
{
if (cobalt_board_id <= COBALT_BRD_ID_QUBE1)
return;
while (!(readb(UART_BASE + UART_LSR) & UART_LSR_THRE))
;
writeb(c, UART_BASE + UART_TX);
}

3
arch/mips/cobalt/setup.c
View File

@ -17,6 +17,7 @@
#include <asm/bootinfo.h>
#include <asm/reboot.h>
#include <asm/setup.h>
#include <asm/gt64120.h>
#include <cobalt.h>
@ -112,6 +113,8 @@ void __init prom_init(void)
}
add_memory_region(0x0, memsz, BOOT_MEM_RAM);
setup_8250_early_printk_port(CKSEG1ADDR(0x1c800000), 0, 0);
}
void __init prom_free_prom_memory(void)

136
arch/mips/configs/powertv_defconfig
View File

@ -1,136 +0,0 @@
CONFIG_POWERTV=y
CONFIG_BOOTLOADER_FAMILY="R2"
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_HZ_1000=y
CONFIG_PREEMPT=y
# CONFIG_SECCOMP is not set
CONFIG_EXPERIMENTAL=y
CONFIG_CROSS_COMPILE=""
# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
CONFIG_LOG_BUF_SHIFT=16
CONFIG_RELAY=y
CONFIG_BLK_DEV_INITRD=y
# CONFIG_RD_GZIP is not set
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_EXPERT=y
# CONFIG_SYSCTL_SYSCALL is not set
CONFIG_KALLSYMS_ALL=y
# CONFIG_PCSPKR_PLATFORM is not set
# CONFIG_EPOLL is not set
# CONFIG_SIGNALFD is not set
# CONFIG_EVENTFD is not set
# CONFIG_VM_EVENT_COUNTERS is not set
# CONFIG_SLUB_DEBUG is not set
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODVERSIONS=y
CONFIG_MODULE_SRCVERSION_ALL=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_PCI=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_ADVANCED_ROUTER=y
CONFIG_IP_PNP=y
CONFIG_SYN_COOKIES=y
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_LRO is not set
# CONFIG_INET_DIAG is not set
CONFIG_IPV6=y
CONFIG_IPV6_PRIVACY=y
CONFIG_INET6_AH=y
CONFIG_INET6_ESP=y
CONFIG_INET6_IPCOMP=y
# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
# CONFIG_INET6_XFRM_MODE_BEET is not set
# CONFIG_IPV6_SIT is not set
CONFIG_IPV6_TUNNEL=y
CONFIG_NETFILTER=y
# CONFIG_BRIDGE_NETFILTER is not set
CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
CONFIG_IP_NF_IPTABLES=y
CONFIG_IP_NF_FILTER=y
CONFIG_IP_NF_ARPTABLES=y
CONFIG_IP_NF_ARPFILTER=y
CONFIG_IP6_NF_IPTABLES=y
CONFIG_IP6_NF_FILTER=y
CONFIG_BRIDGE=y
CONFIG_NET_SCHED=y
CONFIG_NET_SCH_TBF=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_MTD=y
CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_NAND=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=32768
# CONFIG_MISC_DEVICES is not set
# CONFIG_SCSI_PROC_FS is not set
CONFIG_BLK_DEV_SD=y
# CONFIG_SCSI_LOWLEVEL is not set
CONFIG_ATA=y
CONFIG_NETDEVICES=y
CONFIG_NET_ETHERNET=y
# CONFIG_WLAN is not set
CONFIG_USB_RTL8150=y
# CONFIG_INPUT_MOUSEDEV is not set
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
# CONFIG_VT is not set
# CONFIG_DEVKMEM is not set
# CONFIG_LEGACY_PTYS is not set
# CONFIG_HW_RANDOM is not set
# CONFIG_HWMON is not set
# CONFIG_MFD_SUPPORT is not set
# CONFIG_VGA_ARB is not set
CONFIG_USB_HIDDEV=y
CONFIG_USB=y
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
CONFIG_USB_DEVICEFS=y
# CONFIG_USB_DEVICE_CLASS is not set
CONFIG_USB_EHCI_HCD=y
# CONFIG_USB_EHCI_TT_NEWSCHED is not set
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_SERIAL=y
CONFIG_USB_SERIAL_CONSOLE=y
CONFIG_USB_SERIAL_CP210X=y
CONFIG_EXT2_FS=y
CONFIG_EXT3_FS=y
# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
# CONFIG_EXT3_FS_XATTR is not set
# CONFIG_DNOTIFY is not set
CONFIG_FUSE_FS=y
CONFIG_PROC_KCORE=y
CONFIG_TMPFS=y
CONFIG_JFFS2_FS=y
CONFIG_CRAMFS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
CONFIG_ROOT_NFS=y
CONFIG_PRINTK_TIME=y
CONFIG_DEBUG_FS=y
CONFIG_DEBUG_KERNEL=y
CONFIG_DETECT_HUNG_TASK=y
# CONFIG_SCHED_DEBUG is not set
# CONFIG_DEBUG_PREEMPT is not set
CONFIG_DEBUG_INFO=y
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
# CONFIG_EARLY_PRINTK is not set
CONFIG_CMDLINE_BOOL=y
# CONFIG_CRYPTO_ANSI_CPRNG is not set
# CONFIG_CRYPTO_HW is not set

8
arch/mips/dec/int-handler.S
View File

@ -118,7 +118,7 @@
* 7 FPU/R4k timer
*
* We handle the IRQ according to _our_ priority (see setup.c),
* then we just return. If multiple IRQs are pending then we will
* then we just return. If multiple IRQs are pending then we will
* just take another exception, big deal.
*/
.align 5
@ -146,7 +146,7 @@
/*
* Find irq with highest priority
*/
PTR_LA t1,cpu_mask_nr_tbl
PTR_LA t1,cpu_mask_nr_tbl
1: lw t2,(t1)
nop
and t2,t0
@ -195,7 +195,7 @@
/*
* Find irq with highest priority
*/
PTR_LA t1,asic_mask_nr_tbl
PTR_LA t1,asic_mask_nr_tbl
2: lw t2,(t1)
nop
and t2,t0
@ -221,7 +221,7 @@
FEXPORT(cpu_all_int) # HALT, timers, software junk
li a0,DEC_CPU_IRQ_BASE
srl t0,CAUSEB_IP
li t1,CAUSEF_IP>>CAUSEB_IP # mask
li t1,CAUSEF_IP>>CAUSEB_IP # mask
b 1f
li t2,4 # nr of bits / 2

43
arch/mips/dec/ioasic-irq.c
View File

@ -1,7 +1,7 @@
/*
* DEC I/O ASIC interrupts.
*
* Copyright (c) 2002, 2003 Maciej W. Rozycki
* Copyright (c) 2002, 2003, 2013 Maciej W. Rozycki
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
@ -51,22 +51,51 @@ static struct irq_chip ioasic_irq_type = {
.irq_unmask = unmask_ioasic_irq,
};
void clear_ioasic_dma_irq(unsigned int irq)
static void clear_ioasic_dma_irq(struct irq_data *d)
{
u32 sir;
sir = ~(1 << (irq - ioasic_irq_base));
sir = ~(1 << (d->irq - ioasic_irq_base));
ioasic_write(IO_REG_SIR, sir);
fast_iob();
}
static struct irq_chip ioasic_dma_irq_type = {
.name = "IO-ASIC-DMA",
.irq_ack = ack_ioasic_irq,
.irq_ack = clear_ioasic_dma_irq,
.irq_mask = mask_ioasic_irq,
.irq_mask_ack = ack_ioasic_irq,
.irq_unmask = unmask_ioasic_irq,
.irq_eoi = clear_ioasic_dma_irq,
};
/*
* I/O ASIC implements two kinds of DMA interrupts, informational and
* error interrupts.
*
* The formers do not stop DMA and should be cleared as soon as possible
* so that if they retrigger before the handler has completed, usually as
* a side effect of actions taken by the handler, then they are reissued.
* These use the `handle_edge_irq' handler that clears the request right
* away.
*
* The latters stop DMA and do not resume it until the interrupt has been
* cleared. This cannot be done until after a corrective action has been
* taken and this also means they will not retrigger. Therefore they use
* the `handle_fasteoi_irq' handler that only clears the request on the
* way out. Because MIPS processor interrupt inputs, one of which the I/O
* ASIC is cascaded to, are level-triggered it is recommended that error
* DMA interrupt action handlers are registered with the IRQF_ONESHOT flag
* set so that they are run with the interrupt line masked.
*
* This mask has `1' bits in the positions of informational interrupts.
*/
#define IO_IRQ_DMA_INFO \
(IO_IRQ_MASK(IO_INR_SCC0A_RXDMA) | \
IO_IRQ_MASK(IO_INR_SCC1A_RXDMA) | \
IO_IRQ_MASK(IO_INR_ISDN_TXDMA) | \
IO_IRQ_MASK(IO_INR_ISDN_RXDMA) | \
IO_IRQ_MASK(IO_INR_ASC_DMA))
void __init init_ioasic_irqs(int base)
{
int i;
@ -79,7 +108,9 @@ void __init init_ioasic_irqs(int base)
irq_set_chip_and_handler(i, &ioasic_irq_type,
handle_level_irq);
for (; i < base + IO_IRQ_LINES; i++)
irq_set_chip(i, &ioasic_dma_irq_type);
irq_set_chip_and_handler(i, &ioasic_dma_irq_type,
1 << (i - base) & IO_IRQ_DMA_INFO ?
handle_edge_irq : handle_fasteoi_irq);
ioasic_irq_base = base;
}

2
arch/mips/dec/prom/call_o32.S
View File

@ -14,7 +14,7 @@
/* Maximum number of arguments supported. Must be even! */
#define O32_ARGC 32
/* Number of static registers we save. */
/* Number of static registers we save. */
#define O32_STATC 11
/* Frame size for both of the above. */
#define O32_FRAMESZ (4 * O32_ARGC + SZREG * O32_STATC)

2
arch/mips/dec/prom/init.c
View File

@ -104,7 +104,7 @@ void __init prom_init(void)
if (prom_is_rex(magic))
rex_clear_cache();
/* Register the early console. */
/* Register the early console. */
register_prom_console();
/* Were we compiled with the right CPU option? */

2
arch/mips/dec/prom/memory.c
View File

@ -22,7 +22,7 @@ volatile unsigned long mem_err; /* So we know an error occurred */
/*
* Probe memory in 4MB chunks, waiting for an error to tell us we've fallen
* off the end of real memory. Only suitable for the 2100/3100's (PMAX).
* off the end of real memory. Only suitable for the 2100/3100's (PMAX).
*/
#define CHUNK_SIZE 0x400000

4
arch/mips/dec/setup.c
View File

@ -65,7 +65,7 @@ EXPORT_SYMBOL(ioasic_base);
/*
* IRQ routing and priority tables. Priorites are set as follows:
*
* KN01 KN230 KN02 KN02-BA KN02-CA KN03
* KN01 KN230 KN02 KN02-BA KN02-CA KN03
*
* MEMORY CPU CPU CPU ASIC CPU CPU
* RTC CPU CPU CPU ASIC CPU CPU
@ -413,7 +413,7 @@ static void __init dec_init_kn02(void)
/*
* Machine-specific initialisation for KN02-BA, aka DS5000/1xx
* (xx = 20, 25, 33), aka 3min. Also applies to KN04(-BA), aka
* (xx = 20, 25, 33), aka 3min. Also applies to KN04(-BA), aka
* DS5000/150, aka 4min.
*/
static int kn02ba_interrupt[DEC_NR_INTS] __initdata = {

4
arch/mips/include/asm/addrspace.h
View File

@ -58,7 +58,7 @@
/*
* Memory segments (64bit kernel mode addresses)
* The compatibility segments use the full 64-bit sign extended value. Note
* The compatibility segments use the full 64-bit sign extended value. Note
* the R8000 doesn't have them so don't reference these in generic MIPS code.
*/
#define XKUSEG _CONST64_(0x0000000000000000)
@ -131,7 +131,7 @@
/*
* The ultimate limited of the 64-bit MIPS architecture: 2 bits for selecting
* the region, 3 bits for the CCA mode. This leaves 59 bits of which the
* the region, 3 bits for the CCA mode. This leaves 59 bits of which the
* R8000 implements most with its 48-bit physical address space.
*/
#define TO_PHYS_MASK _CONST64_(0x07ffffffffffffff) /* 2^^59 - 1 */

2
arch/mips/include/asm/atomic.h
View File

@ -1,5 +1,5 @@
/*
* Atomic operations that C can't guarantee us. Useful for
* Atomic operations that C can't guarantee us. Useful for
* resource counting etc..
*
* But use these as seldom as possible since they are much more slower

6
arch/mips/include/asm/barrier.h
View File

@ -18,7 +18,7 @@
* over this barrier. All reads preceding this primitive are guaranteed
* to access memory (but not necessarily other CPUs' caches) before any
* reads following this primitive that depend on the data return by
* any of the preceding reads. This primitive is much lighter weight than
* any of the preceding reads. This primitive is much lighter weight than
* rmb() on most CPUs, and is never heavier weight than is
* rmb().
*
@ -43,7 +43,7 @@
* </programlisting>
*
* because the read of "*q" depends on the read of "p" and these
* two reads are separated by a read_barrier_depends(). However,
* two reads are separated by a read_barrier_depends(). However,
* the following code, with the same initial values for "a" and "b":
*
* <programlisting>
@ -57,7 +57,7 @@
* </programlisting>
*
* does not enforce ordering, since there is no data dependency between
* the read of "a" and the read of "b". Therefore, on some CPUs, such
* the read of "a" and the read of "b". Therefore, on some CPUs, such
* as Alpha, "y" could be set to 3 and "x" to 0. Use rmb()
* in cases like this where there are no data dependencies.
*/

93
arch/mips/include/asm/cacheops.h
View File

@ -14,56 +14,52 @@
/*
* Cache Operations available on all MIPS processors with R4000-style caches
*/
#define Index_Invalidate_I 0x00
#define Index_Writeback_Inv_D 0x01
#define Index_Load_Tag_I 0x04
#define Index_Load_Tag_D 0x05
#define Index_Store_Tag_I 0x08
#define Index_Store_Tag_D 0x09
#if defined(CONFIG_CPU_LOONGSON2)
#define Hit_Invalidate_I 0x00
#else
#define Hit_Invalidate_I 0x10
#endif
#define Hit_Invalidate_D 0x11
#define Hit_Writeback_Inv_D 0x15
#define Index_Invalidate_I 0x00
#define Index_Writeback_Inv_D 0x01
#define Index_Load_Tag_I 0x04
#define Index_Load_Tag_D 0x05
#define Index_Store_Tag_I 0x08
#define Index_Store_Tag_D 0x09
#define Hit_Invalidate_I 0x10
#define Hit_Invalidate_D 0x11
#define Hit_Writeback_Inv_D 0x15
/*
* R4000-specific cacheops
*/
#define Create_Dirty_Excl_D 0x0d
#define Fill 0x14
#define Hit_Writeback_I 0x18
#define Hit_Writeback_D 0x19
#define Create_Dirty_Excl_D 0x0d
#define Fill 0x14
#define Hit_Writeback_I 0x18
#define Hit_Writeback_D 0x19
/*
* R4000SC and R4400SC-specific cacheops
*/
#define Index_Invalidate_SI 0x02
#define Index_Writeback_Inv_SD 0x03
#define Index_Load_Tag_SI 0x06
#define Index_Load_Tag_SD 0x07
#define Index_Store_Tag_SI 0x0A
#define Index_Store_Tag_SD 0x0B
#define Create_Dirty_Excl_SD 0x0f
#define Hit_Invalidate_SI 0x12
#define Hit_Invalidate_SD 0x13
#define Hit_Writeback_Inv_SD 0x17
#define Hit_Writeback_SD 0x1b
#define Hit_Set_Virtual_SI 0x1e
#define Hit_Set_Virtual_SD 0x1f
#define Index_Invalidate_SI 0x02
#define Index_Writeback_Inv_SD 0x03
#define Index_Load_Tag_SI 0x06
#define Index_Load_Tag_SD 0x07
#define Index_Store_Tag_SI 0x0A
#define Index_Store_Tag_SD 0x0B
#define Create_Dirty_Excl_SD 0x0f
#define Hit_Invalidate_SI 0x12
#define Hit_Invalidate_SD 0x13
#define Hit_Writeback_Inv_SD 0x17
#define Hit_Writeback_SD 0x1b
#define Hit_Set_Virtual_SI 0x1e
#define Hit_Set_Virtual_SD 0x1f
/*
* R5000-specific cacheops
*/
#define R5K_Page_Invalidate_S 0x17
#define R5K_Page_Invalidate_S 0x17
/*
* RM7000-specific cacheops
*/
#define Page_Invalidate_T 0x16
#define Index_Store_Tag_T 0x0a
#define Index_Load_Tag_T 0x06
#define Page_Invalidate_T 0x16
#define Index_Store_Tag_T 0x0a
#define Index_Load_Tag_T 0x06
/*
* R10000-specific cacheops
@ -71,17 +67,22 @@
* Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused.
* Most of the _S cacheops are identical to the R4000SC _SD cacheops.
*/
#define Index_Writeback_Inv_S 0x03
#define Index_Load_Tag_S 0x07
#define Index_Store_Tag_S 0x0B
#define Hit_Invalidate_S 0x13
#define Cache_Barrier 0x14
#define Hit_Writeback_Inv_S 0x17
#define Index_Load_Data_I 0x18
#define Index_Load_Data_D 0x19
#define Index_Load_Data_S 0x1b
#define Index_Store_Data_I 0x1c
#define Index_Store_Data_D 0x1d
#define Index_Store_Data_S 0x1f
#define Index_Writeback_Inv_S 0x03
#define Index_Load_Tag_S 0x07
#define Index_Store_Tag_S 0x0B
#define Hit_Invalidate_S 0x13
#define Cache_Barrier 0x14
#define Hit_Writeback_Inv_S 0x17
#define Index_Load_Data_I 0x18
#define Index_Load_Data_D 0x19
#define Index_Load_Data_S 0x1b
#define Index_Store_Data_I 0x1c
#define Index_Store_Data_D 0x1d
#define Index_Store_Data_S 0x1f
/*
* Loongson2-specific cacheops
*/
#define Hit_Invalidate_I_Loongson23 0x00
#endif /* __ASM_CACHEOPS_H */

2
arch/mips/include/asm/dec/ioasic.h
View File

@ -31,8 +31,6 @@ static inline u32 ioasic_read(unsigned int reg)
return ioasic_base[reg / 4];
}
extern void clear_ioasic_dma_irq(unsigned int irq);
extern void init_ioasic_irqs(int base);
extern int dec_ioasic_clocksource_init(void);

2
arch/mips/include/asm/dec/ioasic_addrs.h
View File

@ -40,7 +40,7 @@
#define IOASIC_FLOPPY (11*IOASIC_SLOT_SIZE) /* FDC (maxine) */
#define IOASIC_SCSI (12*IOASIC_SLOT_SIZE) /* ASC SCSI */
#define IOASIC_FDC_DMA (13*IOASIC_SLOT_SIZE) /* FDC DMA (maxine) */
#define IOASIC_SCSI_DMA (14*IOASIC_SLOT_SIZE) /* ??? */
#define IOASIC_SCSI_DMA (14*IOASIC_SLOT_SIZE) /* ??? */
#define IOASIC_RES_15 (15*IOASIC_SLOT_SIZE) /* unused? */

12
arch/mips/include/asm/dec/kn01.h
View File

@ -57,12 +57,12 @@
/*
* System Control & Status Register bits.
*/
#define KN01_CSR_MNFMOD (1<<15) /* MNFMOD manufacturing jumper */
#define KN01_CSR_STATUS (1<<14) /* self-test result status output */
#define KN01_CSR_PARDIS (1<<13) /* parity error disable */
#define KN01_CSR_CRSRTST (1<<12) /* PCC test output */
#define KN01_CSR_MONO (1<<11) /* mono/color fb SIMM installed */
#define KN01_CSR_MEMERR (1<<10) /* write timeout error status & ack*/
#define KN01_CSR_MNFMOD (1<<15) /* MNFMOD manufacturing jumper */
#define KN01_CSR_STATUS (1<<14) /* self-test result status output */
#define KN01_CSR_PARDIS (1<<13) /* parity error disable */
#define KN01_CSR_CRSRTST (1<<12) /* PCC test output */
#define KN01_CSR_MONO (1<<11) /* mono/color fb SIMM installed */
#define KN01_CSR_MEMERR (1<<10) /* write timeout error status & ack*/
#define KN01_CSR_VINT (1<<9) /* PCC area detect #2 status & ack */
#define KN01_CSR_TXDIS (1<<8) /* DZ11 transmit disable */
#define KN01_CSR_VBGTRG (1<<2) /* blue DAC voltage over green (r/o) */

2
arch/mips/include/asm/dec/kn02ca.h
View File

@ -68,7 +68,7 @@
#define KN03CA_IO_SSR_ISDN_RST (1<<12) /* ~ISDN (Am79C30A) reset */
#define KN03CA_IO_SSR_FLOPPY_RST (1<<7) /* ~FDC (82077) reset */
#define KN03CA_IO_SSR_VIDEO_RST (1<<6) /* ~framebuffer reset */
#define KN03CA_IO_SSR_VIDEO_RST (1<<6) /* ~framebuffer reset */
#define KN03CA_IO_SSR_AB_RST (1<<5) /* ACCESS.bus reset */
#define KN03CA_IO_SSR_RES_4 (1<<4) /* unused */
#define KN03CA_IO_SSR_RES_3 (1<<4) /* unused */

2
arch/mips/include/asm/dec/prom.h
View File

@ -49,7 +49,7 @@
#ifdef CONFIG_64BIT
#define prom_is_rex(magic) 1 /* KN04 and KN05 are REX PROMs. */
#define prom_is_rex(magic) 1 /* KN04 and KN05 are REX PROMs. */
#else /* !CONFIG_64BIT */

1
arch/mips/include/asm/elf.h
View File

@ -331,6 +331,7 @@ extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *);
#define ELF_CORE_COPY_FPREGS(tsk, elf_fpregs) \
dump_task_fpu(tsk, elf_fpregs)
#define CORE_DUMP_USE_REGSET
#define ELF_EXEC_PAGESIZE PAGE_SIZE
/* This yields a mask that user programs can use to figure out what

18
arch/mips/include/asm/mach-ath79/ar933x_uart_platform.h
View File

@ -1,18 +0,0 @@
/*
* Platform data definition for Atheros AR933X UART
*
* Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#ifndef _AR933X_UART_PLATFORM_H
#define _AR933X_UART_PLATFORM_H
struct ar933x_uart_platform_data {
unsigned uartclk;
};
#endif /* _AR933X_UART_PLATFORM_H */

110
arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h Normal file
View File

@ -0,0 +1,110 @@
#ifndef __BCM47XX_BOARD_H
#define __BCM47XX_BOARD_H
enum bcm47xx_board {
BCM47XX_BOARD_ASUS_RTAC66U,
BCM47XX_BOARD_ASUS_RTN10,
BCM47XX_BOARD_ASUS_RTN10D,
BCM47XX_BOARD_ASUS_RTN10U,
BCM47XX_BOARD_ASUS_RTN12,
BCM47XX_BOARD_ASUS_RTN12B1,
BCM47XX_BOARD_ASUS_RTN12C1,
BCM47XX_BOARD_ASUS_RTN12D1,
BCM47XX_BOARD_ASUS_RTN12HP,
BCM47XX_BOARD_ASUS_RTN15U,
BCM47XX_BOARD_ASUS_RTN16,
BCM47XX_BOARD_ASUS_RTN53,
BCM47XX_BOARD_ASUS_RTN66U,
BCM47XX_BOARD_ASUS_WL300G,
BCM47XX_BOARD_ASUS_WL320GE,
BCM47XX_BOARD_ASUS_WL330GE,
BCM47XX_BOARD_ASUS_WL500GD,
BCM47XX_BOARD_ASUS_WL500GPV1,
BCM47XX_BOARD_ASUS_WL500GPV2,
BCM47XX_BOARD_ASUS_WL500W,
BCM47XX_BOARD_ASUS_WL520GC,
BCM47XX_BOARD_ASUS_WL520GU,
BCM47XX_BOARD_ASUS_WL700GE,
BCM47XX_BOARD_ASUS_WLHDD,
BCM47XX_BOARD_BELKIN_F7D4301,
BCM47XX_BOARD_BUFFALO_WBR2_G54,
BCM47XX_BOARD_BUFFALO_WHR2_A54G54,
BCM47XX_BOARD_BUFFALO_WHR_G125,
BCM47XX_BOARD_BUFFALO_WHR_G54S,
BCM47XX_BOARD_BUFFALO_WHR_HP_G54,
BCM47XX_BOARD_BUFFALO_WLA2_G54L,
BCM47XX_BOARD_BUFFALO_WZR_G300N,
BCM47XX_BOARD_BUFFALO_WZR_RS_G54,
BCM47XX_BOARD_BUFFALO_WZR_RS_G54HP,
BCM47XX_BOARD_CISCO_M10V1,
BCM47XX_BOARD_CISCO_M20V1,
BCM47XX_BOARD_DELL_TM2300,
BCM47XX_BOARD_DLINK_DIR130,
BCM47XX_BOARD_DLINK_DIR330,
BCM47XX_BOARD_HUAWEI_E970,
BCM47XX_BOARD_LINKSYS_E900V1,
BCM47XX_BOARD_LINKSYS_E1000V1,
BCM47XX_BOARD_LINKSYS_E1000V2,
BCM47XX_BOARD_LINKSYS_E1000V21,
BCM47XX_BOARD_LINKSYS_E1200V2,
BCM47XX_BOARD_LINKSYS_E2000V1,
BCM47XX_BOARD_LINKSYS_E3000V1,
BCM47XX_BOARD_LINKSYS_E3200V1,
BCM47XX_BOARD_LINKSYS_E4200V1,
BCM47XX_BOARD_LINKSYS_WRT150NV1,
BCM47XX_BOARD_LINKSYS_WRT150NV11,
BCM47XX_BOARD_LINKSYS_WRT160NV1,
BCM47XX_BOARD_LINKSYS_WRT160NV3,
BCM47XX_BOARD_LINKSYS_WRT300NV11,
BCM47XX_BOARD_LINKSYS_WRT310NV1,
BCM47XX_BOARD_LINKSYS_WRT310NV2,
BCM47XX_BOARD_LINKSYS_WRT54G3GV2,
BCM47XX_BOARD_LINKSYS_WRT610NV1,
BCM47XX_BOARD_LINKSYS_WRT610NV2,
BCM47XX_BOARD_LINKSYS_WRTSL54GS,
BCM47XX_BOARD_MOTOROLA_WE800G,
BCM47XX_BOARD_MOTOROLA_WR850GP,
BCM47XX_BOARD_MOTOROLA_WR850GV2V3,
BCM47XX_BOARD_NETGEAR_WGR614V8,
BCM47XX_BOARD_NETGEAR_WGR614V9,
BCM47XX_BOARD_NETGEAR_WNDR3300,
BCM47XX_BOARD_NETGEAR_WNDR3400V1,
BCM47XX_BOARD_NETGEAR_WNDR3400V2,
BCM47XX_BOARD_NETGEAR_WNDR3400VCNA,
BCM47XX_BOARD_NETGEAR_WNDR3700V3,
BCM47XX_BOARD_NETGEAR_WNDR4000,
BCM47XX_BOARD_NETGEAR_WNDR4500V1,
BCM47XX_BOARD_NETGEAR_WNDR4500V2,
BCM47XX_BOARD_NETGEAR_WNR2000,
BCM47XX_BOARD_NETGEAR_WNR3500L,
BCM47XX_BOARD_NETGEAR_WNR3500U,
BCM47XX_BOARD_NETGEAR_WNR3500V2,
BCM47XX_BOARD_NETGEAR_WNR3500V2VC,
BCM47XX_BOARD_NETGEAR_WNR834BV2,
BCM47XX_BOARD_PHICOMM_M1,
BCM47XX_BOARD_SIMPLETECH_SIMPLESHARE,
BCM47XX_BOARD_ZTE_H218N,
BCM47XX_BOARD_UNKNOWN,
BCM47XX_BOARD_NO,
};
#define BCM47XX_BOARD_MAX_NAME 30
void bcm47xx_board_detect(void);
enum bcm47xx_board bcm47xx_board_get(void);
const char *bcm47xx_board_get_name(void);
#endif /* __BCM47XX_BOARD_H */

2
arch/mips/include/asm/mach-bcm47xx/bcm47xx_nvram.h
View File

@ -48,4 +48,6 @@ static inline void bcm47xx_nvram_parse_macaddr(char *buf, u8 macaddr[6])
printk(KERN_WARNING "Can not parse mac address: %s\n", buf);
}
int bcm47xx_nvram_gpio_pin(const char *name);
#endif /* __BCM47XX_NVRAM_H */

12
arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
View File

@ -52,23 +52,11 @@ static inline int plat_dma_supported(struct device *dev, u64 mask)
return 0;
}
static inline void plat_extra_sync_for_device(struct device *dev)
{
BUG();
}
static inline int plat_device_is_coherent(struct device *dev)
{
return 1;
}
static inline int plat_dma_mapping_error(struct device *dev,
dma_addr_t dma_addr)
{
BUG();
return 0;
}
dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr);
phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr);

87
arch/mips/include/asm/mach-dec/cpu-feature-overrides.h Normal file
View File

@ -0,0 +1,87 @@
/*
* CPU feature overrides for DECstation systems. Two variations
* are generally applicable.
*
* Copyright (C) 2013 Maciej W. Rozycki
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#ifndef __ASM_MACH_DEC_CPU_FEATURE_OVERRIDES_H
#define __ASM_MACH_DEC_CPU_FEATURE_OVERRIDES_H
/* Generic ones first. */
#define cpu_has_tlb 1
#define cpu_has_tx39_cache 0
#define cpu_has_fpu 1
#define cpu_has_divec 0
#define cpu_has_prefetch 0
#define cpu_has_mcheck 0
#define cpu_has_ejtag 0
#define cpu_has_mips16 0
#define cpu_has_mdmx 0
#define cpu_has_mips3d 0
#define cpu_has_smartmips 0
#define cpu_has_rixi 0
#define cpu_has_vtag_icache 0
#define cpu_has_ic_fills_f_dc 0
#define cpu_has_pindexed_dcache 0
#define cpu_has_local_ebase 0
#define cpu_icache_snoops_remote_store 1
#define cpu_has_mips_4 0
#define cpu_has_mips_5 0
#define cpu_has_mips32r1 0
#define cpu_has_mips32r2 0
#define cpu_has_mips64r1 0
#define cpu_has_mips64r2 0
#define cpu_has_dsp 0
#define cpu_has_mipsmt 0
#define cpu_has_userlocal 0
/* R3k-specific ones. */
#ifdef CONFIG_CPU_R3000
#define cpu_has_4kex 0
#define cpu_has_3k_cache 1
#define cpu_has_4k_cache 0
#define cpu_has_32fpr 0
#define cpu_has_counter 0
#define cpu_has_watch 0
#define cpu_has_vce 0
#define cpu_has_cache_cdex_p 0
#define cpu_has_cache_cdex_s 0
#define cpu_has_llsc 0
#define cpu_has_dc_aliases 0
#define cpu_has_mips_2 0
#define cpu_has_mips_3 0
#define cpu_has_nofpuex 1
#define cpu_has_inclusive_pcaches 0
#define cpu_dcache_line_size() 4
#define cpu_icache_line_size() 4
#define cpu_scache_line_size() 0
#endif /* CONFIG_CPU_R3000 */
/* R4k-specific ones. */
#ifdef CONFIG_CPU_R4X00
#define cpu_has_4kex 1
#define cpu_has_3k_cache 0
#define cpu_has_4k_cache 1
#define cpu_has_32fpr 1
#define cpu_has_counter 1
#define cpu_has_watch 1
#define cpu_has_vce 1
#define cpu_has_cache_cdex_p 1
#define cpu_has_cache_cdex_s 1
#define cpu_has_llsc 1
#define cpu_has_dc_aliases (PAGE_SIZE < 0x4000)
#define cpu_has_mips_2 1
#define cpu_has_mips_3 1
#define cpu_has_nofpuex 0
#define cpu_has_inclusive_pcaches 1
#define cpu_dcache_line_size() 16
#define cpu_icache_line_size() 16
#define cpu_scache_line_size() 32
#endif /* CONFIG_CPU_R4X00 */
#endif /* __ASM_MACH_DEC_CPU_FEATURE_OVERRIDES_H */

10
arch/mips/include/asm/mach-generic/dma-coherence.h
View File

@ -47,16 +47,6 @@ static inline int plat_dma_supported(struct device *dev, u64 mask)
return 1;
}
static inline void plat_extra_sync_for_device(struct device *dev)
{
}
static inline int plat_dma_mapping_error(struct device *dev,
dma_addr_t dma_addr)
{
return 0;
}
static inline int plat_device_is_coherent(struct device *dev)
{
#ifdef CONFIG_DMA_COHERENT

10
arch/mips/include/asm/mach-ip27/dma-coherence.h
View File

@ -58,16 +58,6 @@ static inline int plat_dma_supported(struct device *dev, u64 mask)
return 1;
}
static inline void plat_extra_sync_for_device(struct device *dev)
{
}
static inline int plat_dma_mapping_error(struct device *dev,
dma_addr_t dma_addr)
{
return 0;
}
static inline int plat_device_is_coherent(struct device *dev)
{
return 1; /* IP27 non-cohernet mode is unsupported */

11
arch/mips/include/asm/mach-ip32/dma-coherence.h
View File

@ -80,17 +80,6 @@ static inline int plat_dma_supported(struct device *dev, u64 mask)
return 1;
}
static inline void plat_extra_sync_for_device(struct device *dev)
{
return;
}
static inline int plat_dma_mapping_error(struct device *dev,
dma_addr_t dma_addr)
{
return 0;
}
static inline int plat_device_is_coherent(struct device *dev)
{
return 0; /* IP32 is non-cohernet */

10
arch/mips/include/asm/mach-jazz/dma-coherence.h
View File

@ -48,16 +48,6 @@ static inline int plat_dma_supported(struct device *dev, u64 mask)
return 1;
}
static inline void plat_extra_sync_for_device(struct device *dev)
{
}
static inline int plat_dma_mapping_error(struct device *dev,
dma_addr_t dma_addr)
{
return 0;
}
static inline int plat_device_is_coherent(struct device *dev)
{
return 0;

10
arch/mips/include/asm/mach-loongson/dma-coherence.h
View File

@ -53,16 +53,6 @@ static inline int plat_dma_supported(struct device *dev, u64 mask)
return 1;
}
static inline void plat_extra_sync_for_device(struct device *dev)
{
}
static inline int plat_dma_mapping_error(struct device *dev,
dma_addr_t dma_addr)
{
return 0;
}
static inline int plat_device_is_coherent(struct device *dev)
{
return 0;

120
arch/mips/include/asm/mach-powertv/asic.h
View File

@ -1,120 +0,0 @@
/*
* Copyright (C) 2009 Cisco Systems, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef _ASM_MACH_POWERTV_ASIC_H
#define _ASM_MACH_POWERTV_ASIC_H
#include <linux/ioport.h>
#include <linux/platform_device.h>
#include <asm/mach-powertv/asic_regs.h>
#define DVR_CAPABLE (1<<0)
#define PCIE_CAPABLE (1<<1)
#define FFS_CAPABLE (1<<2)
#define DISPLAY_CAPABLE (1<<3)
/* Platform Family types
* For compitability, the new value must be added in the end */
enum family_type {
FAMILY_8500,
FAMILY_8500RNG,
FAMILY_4500,
FAMILY_1500,
FAMILY_8600,
FAMILY_4600,
FAMILY_4600VZA,
FAMILY_8600VZB,
FAMILY_1500VZE,
FAMILY_1500VZF,
FAMILY_8700,
FAMILIES
};
/* Register maps for each ASIC */
extern const struct register_map calliope_register_map;
extern const struct register_map cronus_register_map;
extern const struct register_map gaia_register_map;
extern const struct register_map zeus_register_map;
extern struct resource dvr_cronus_resources[];
extern struct resource dvr_gaia_resources[];
extern struct resource dvr_zeus_resources[];
extern struct resource non_dvr_calliope_resources[];
extern struct resource non_dvr_cronus_resources[];
extern struct resource non_dvr_cronuslite_resources[];
extern struct resource non_dvr_gaia_resources[];
extern struct resource non_dvr_vz_calliope_resources[];
extern struct resource non_dvr_vze_calliope_resources[];
extern struct resource non_dvr_vzf_calliope_resources[];
extern struct resource non_dvr_zeus_resources[];
extern void powertv_platform_init(void);
extern void platform_alloc_bootmem(void);
extern enum asic_type platform_get_asic(void);
extern enum family_type platform_get_family(void);
extern int platform_supports_dvr(void);
extern int platform_supports_ffs(void);
extern int platform_supports_pcie(void);
extern int platform_supports_display(void);
extern void configure_platform(void);
/* Platform Resources */
#define ASIC_RESOURCE_GET_EXISTS 1
extern struct resource *asic_resource_get(const char *name);
extern void platform_release_memory(void *baddr, int size);
/* USB configuration */
struct usb_hcd; /* Forward reference */
extern void platform_configure_usb_ehci(void);
extern void platform_unconfigure_usb_ehci(void);
extern void platform_configure_usb_ohci(void);
extern void platform_unconfigure_usb_ohci(void);
/* Resource for ASIC registers */
extern struct resource asic_resource;
extern int platform_usb_devices_init(struct platform_device **echi_dev,
struct platform_device **ohci_dev);
/* Reboot Cause */
extern void set_reboot_cause(char code, unsigned int data, unsigned int data2);
extern void set_locked_reboot_cause(char code, unsigned int data,
unsigned int data2);
enum sys_reboot_type {
sys_unknown_reboot = 0x00, /* Unknown reboot cause */
sys_davic_change = 0x01, /* Reboot due to change in DAVIC
* mode */
sys_user_reboot = 0x02, /* Reboot initiated by user */
sys_system_reboot = 0x03, /* Reboot initiated by OS */
sys_trap_reboot = 0x04, /* Reboot due to a CPU trap */
sys_silent_reboot = 0x05, /* Silent reboot */
sys_boot_ldr_reboot = 0x06, /* Bootloader reboot */
sys_power_up_reboot = 0x07, /* Power on bootup. Older
* drivers may report as
* userReboot. */
sys_code_change = 0x08, /* Reboot to take code change.
* Older drivers may report as
* userReboot. */
sys_hardware_reset = 0x09, /* HW watchdog or front-panel
* reset button reset. Older
* drivers may report as
* userReboot. */
sys_watchdogInterrupt = 0x0A /* Pre-watchdog interrupt */
};
#endif /* _ASM_MACH_POWERTV_ASIC_H */

90
arch/mips/include/asm/mach-powertv/asic_reg_map.h
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@ -1,90 +0,0 @@
/*
* asic_reg_map.h
*
* A macro-enclosed list of the elements for the register_map structure for
* use in defining and manipulating the structure.
*
* Copyright (C) 2009 Cisco Systems, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
REGISTER_MAP_ELEMENT(eic_slow0_strt_add)
REGISTER_MAP_ELEMENT(eic_cfg_bits)
REGISTER_MAP_ELEMENT(eic_ready_status)
REGISTER_MAP_ELEMENT(chipver3)
REGISTER_MAP_ELEMENT(chipver2)
REGISTER_MAP_ELEMENT(chipver1)
REGISTER_MAP_ELEMENT(chipver0)
REGISTER_MAP_ELEMENT(uart1_intstat)
REGISTER_MAP_ELEMENT(uart1_inten)
REGISTER_MAP_ELEMENT(uart1_config1)
REGISTER_MAP_ELEMENT(uart1_config2)
REGISTER_MAP_ELEMENT(uart1_divisorhi)
REGISTER_MAP_ELEMENT(uart1_divisorlo)
REGISTER_MAP_ELEMENT(uart1_data)
REGISTER_MAP_ELEMENT(uart1_status)
REGISTER_MAP_ELEMENT(int_stat_3)
REGISTER_MAP_ELEMENT(int_stat_2)
REGISTER_MAP_ELEMENT(int_stat_1)
REGISTER_MAP_ELEMENT(int_stat_0)
REGISTER_MAP_ELEMENT(int_config)
REGISTER_MAP_ELEMENT(int_int_scan)
REGISTER_MAP_ELEMENT(ien_int_3)
REGISTER_MAP_ELEMENT(ien_int_2)
REGISTER_MAP_ELEMENT(ien_int_1)
REGISTER_MAP_ELEMENT(ien_int_0)
REGISTER_MAP_ELEMENT(int_level_3_3)
REGISTER_MAP_ELEMENT(int_level_3_2)
REGISTER_MAP_ELEMENT(int_level_3_1)
REGISTER_MAP_ELEMENT(int_level_3_0)
REGISTER_MAP_ELEMENT(int_level_2_3)
REGISTER_MAP_ELEMENT(int_level_2_2)
REGISTER_MAP_ELEMENT(int_level_2_1)
REGISTER_MAP_ELEMENT(int_level_2_0)
REGISTER_MAP_ELEMENT(int_level_1_3)
REGISTER_MAP_ELEMENT(int_level_1_2)
REGISTER_MAP_ELEMENT(int_level_1_1)
REGISTER_MAP_ELEMENT(int_level_1_0)
REGISTER_MAP_ELEMENT(int_level_0_3)
REGISTER_MAP_ELEMENT(int_level_0_2)
REGISTER_MAP_ELEMENT(int_level_0_1)
REGISTER_MAP_ELEMENT(int_level_0_0)
REGISTER_MAP_ELEMENT(int_docsis_en)
REGISTER_MAP_ELEMENT(mips_pll_setup)
REGISTER_MAP_ELEMENT(fs432x4b4_usb_ctl)
REGISTER_MAP_ELEMENT(test_bus)
REGISTER_MAP_ELEMENT(crt_spare)
REGISTER_MAP_ELEMENT(usb2_ohci_int_mask)
REGISTER_MAP_ELEMENT(usb2_strap)
REGISTER_MAP_ELEMENT(ehci_hcapbase)
REGISTER_MAP_ELEMENT(ohci_hc_revision)
REGISTER_MAP_ELEMENT(bcm1_bs_lmi_steer)
REGISTER_MAP_ELEMENT(usb2_control)
REGISTER_MAP_ELEMENT(usb2_stbus_obc)
REGISTER_MAP_ELEMENT(usb2_stbus_mess_size)
REGISTER_MAP_ELEMENT(usb2_stbus_chunk_size)
REGISTER_MAP_ELEMENT(pcie_regs)
REGISTER_MAP_ELEMENT(tim_ch)
REGISTER_MAP_ELEMENT(tim_cl)
REGISTER_MAP_ELEMENT(gpio_dout)
REGISTER_MAP_ELEMENT(gpio_din)
REGISTER_MAP_ELEMENT(gpio_dir)
REGISTER_MAP_ELEMENT(watchdog)
REGISTER_MAP_ELEMENT(front_panel)
REGISTER_MAP_ELEMENT(misc_clk_ctl1)
REGISTER_MAP_ELEMENT(misc_clk_ctl2)
REGISTER_MAP_ELEMENT(crt_ext_ctl)
REGISTER_MAP_ELEMENT(register_maps)

125
arch/mips/include/asm/mach-powertv/asic_regs.h
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@ -1,125 +0,0 @@
/*
* Copyright (C) 2009 Cisco Systems, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef __ASM_MACH_POWERTV_ASIC_H_
#define __ASM_MACH_POWERTV_ASIC_H_
#include <linux/io.h>
/* ASIC types */
enum asic_type {
ASIC_UNKNOWN,
ASIC_ZEUS,
ASIC_CALLIOPE,
ASIC_CRONUS,
ASIC_CRONUSLITE,
ASIC_GAIA,
ASICS /* Number of supported ASICs */
};
/* hardcoded values read from Chip Version registers */
#define CRONUS_10 0x0B4C1C20
#define CRONUS_11 0x0B4C1C21
#define CRONUSLITE_10 0x0B4C1C40
#define NAND_FLASH_BASE 0x03000000
#define CALLIOPE_IO_BASE 0x08000000
#define GAIA_IO_BASE 0x09000000
#define CRONUS_IO_BASE 0x09000000
#define ZEUS_IO_BASE 0x09000000
#define ASIC_IO_SIZE 0x01000000
/* Definitions for backward compatibility */
#define UART1_INTSTAT uart1_intstat
#define UART1_INTEN uart1_inten
#define UART1_CONFIG1 uart1_config1
#define UART1_CONFIG2 uart1_config2
#define UART1_DIVISORHI uart1_divisorhi
#define UART1_DIVISORLO uart1_divisorlo
#define UART1_DATA uart1_data
#define UART1_STATUS uart1_status
/* ASIC register enumeration */
union register_map_entry {
unsigned long phys;
u32 *virt;
};
#define REGISTER_MAP_ELEMENT(x) union register_map_entry x;
struct register_map {
#include <asm/mach-powertv/asic_reg_map.h>
};
#undef REGISTER_MAP_ELEMENT
/**
* register_map_offset_phys - add an offset to the physical address
* @map: Pointer to the &struct register_map
* @offset: Value to add
*
* Only adds the base to non-zero physical addresses
*/
static inline void register_map_offset_phys(struct register_map *map,
unsigned long offset)
{
#define REGISTER_MAP_ELEMENT(x) do { \
if (map->x.phys != 0) \
map->x.phys += offset; \
} while (false);
#include <asm/mach-powertv/asic_reg_map.h>
#undef REGISTER_MAP_ELEMENT
}
/**
* register_map_virtualize - Convert &register_map to virtual addresses
* @map: Pointer to &register_map to virtualize
*/
static inline void register_map_virtualize(struct register_map *map)
{
#define REGISTER_MAP_ELEMENT(x) do { \
map->x.virt = (!map->x.phys) ? NULL : \
UNCAC_ADDR(phys_to_virt(map->x.phys)); \
} while (false);
#include <asm/mach-powertv/asic_reg_map.h>
#undef REGISTER_MAP_ELEMENT
}
extern struct register_map _asic_register_map;
extern unsigned long asic_phy_base;
/*
* Macros to interface to registers through their ioremapped address
* asic_reg_phys_addr Returns the physical address of the given register
* asic_reg_addr Returns the iomapped virtual address of the given
* register.
*/
#define asic_reg_addr(x) (_asic_register_map.x.virt)
#define asic_reg_phys_addr(x) (virt_to_phys((void *) CAC_ADDR( \
(unsigned long) asic_reg_addr(x))))
/*
* The asic_reg macro is gone. It should be replaced by either asic_read or
* asic_write, as appropriate.
*/
#define asic_read(x) readl(asic_reg_addr(x))
#define asic_write(v, x) writel(v, asic_reg_addr(x))
extern void asic_irq_init(void);
#endif

60
arch/mips/include/asm/mach-powertv/cpu-feature-overrides.h
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@ -1,60 +0,0 @@
/*
* Copyright (C) 2010 Cisco Systems, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef _ASM_MACH_POWERTV_CPU_FEATURE_OVERRIDES_H_
#define _ASM_MACH_POWERTV_CPU_FEATURE_OVERRIDES_H_
#define cpu_has_tlb 1
#define cpu_has_4kex 1
#define cpu_has_3k_cache 0
#define cpu_has_4k_cache 1
#define cpu_has_tx39_cache 0
#define cpu_has_fpu 0
#define cpu_has_counter 1
#define cpu_has_watch 1
#define cpu_has_divec 1
#define cpu_has_vce 0
#define cpu_has_cache_cdex_p 0
#define cpu_has_cache_cdex_s 0
#define cpu_has_mcheck 1
#define cpu_has_ejtag 1
#define cpu_has_llsc 1
#define cpu_has_mips16 0
#define cpu_has_mdmx 0
#define cpu_has_mips3d 0
#define cpu_has_smartmips 0
#define cpu_has_vtag_icache 0
#define cpu_has_dc_aliases 0
#define cpu_has_ic_fills_f_dc 0
#define cpu_has_mips32r1 0
#define cpu_has_mips32r2 1
#define cpu_has_mips64r1 0
#define cpu_has_mips64r2 0
#define cpu_has_dsp 0
#define cpu_has_dsp2 0
#define cpu_has_mipsmt 0
#define cpu_has_userlocal 0
#define cpu_has_nofpuex 0
#define cpu_has_64bits 0
#define cpu_has_64bit_zero_reg 0
#define cpu_has_vint 1
#define cpu_has_veic 1
#define cpu_has_inclusive_pcaches 0
#define cpu_dcache_line_size() 32
#define cpu_icache_line_size() 32
#endif

117
arch/mips/include/asm/mach-powertv/dma-coherence.h
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Version from mach-generic modified to support PowerTV port
* Portions Copyright (C) 2009 Cisco Systems, Inc.
* Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
*
*/
#ifndef __ASM_MACH_POWERTV_DMA_COHERENCE_H
#define __ASM_MACH_POWERTV_DMA_COHERENCE_H
#include <linux/sched.h>
#include <linux/device.h>
#include <asm/mach-powertv/asic.h>
static inline bool is_kseg2(void *addr)
{
return (unsigned long)addr >= KSEG2;
}
static inline unsigned long virt_to_phys_from_pte(void *addr)
{
pgd_t *pgd;
pud_t *pud;
pmd_t *pmd;
pte_t *ptep, pte;
unsigned long virt_addr = (unsigned long)addr;
unsigned long phys_addr = 0UL;
/* get the page global directory. */
pgd = pgd_offset_k(virt_addr);
if (!pgd_none(*pgd)) {
/* get the page upper directory */
pud = pud_offset(pgd, virt_addr);
if (!pud_none(*pud)) {
/* get the page middle directory */
pmd = pmd_offset(pud, virt_addr);
if (!pmd_none(*pmd)) {
/* get a pointer to the page table entry */
ptep = pte_offset(pmd, virt_addr);
pte = *ptep;
/* check for a valid page */
if (pte_present(pte)) {
/* get the physical address the page is
* referring to */
phys_addr = (unsigned long)
page_to_phys(pte_page(pte));
/* add the offset within the page */
phys_addr |= (virt_addr & ~PAGE_MASK);
}
}
}
}
return phys_addr;
}
static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr,
size_t size)
{
if (is_kseg2(addr))
return phys_to_dma(virt_to_phys_from_pte(addr));
else
return phys_to_dma(virt_to_phys(addr));
}
static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
struct page *page)
{
return phys_to_dma(page_to_phys(page));
}
static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
dma_addr_t dma_addr)
{
return dma_to_phys(dma_addr);
}
static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
size_t size, enum dma_data_direction direction)
{
}
static inline int plat_dma_supported(struct device *dev, u64 mask)
{
/*
* we fall back to GFP_DMA when the mask isn't all 1s,
* so we can't guarantee allocations that must be
* within a tighter range than GFP_DMA..
*/
if (mask < DMA_BIT_MASK(24))
return 0;
return 1;
}
static inline void plat_extra_sync_for_device(struct device *dev)
{
}
static inline int plat_dma_mapping_error(struct device *dev,
dma_addr_t dma_addr)
{
return 0;
}
static inline int plat_device_is_coherent(struct device *dev)
{
return 0;
}
#endif /* __ASM_MACH_POWERTV_DMA_COHERENCE_H */

253
arch/mips/include/asm/mach-powertv/interrupts.h
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/*
* Copyright (C) 2009 Cisco Systems, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef _ASM_MACH_POWERTV_INTERRUPTS_H_
#define _ASM_MACH_POWERTV_INTERRUPTS_H_
/*
* Defines for all of the interrupt lines
*/
/* Definitions for backward compatibility */
#define kIrq_Uart1 irq_uart1
#define ibase 0
/*------------- Register: int_stat_3 */
/* 126 unused (bit 31) */
#define irq_asc2video (ibase+126) /* ASC 2 Video Interrupt */
#define irq_asc1video (ibase+125) /* ASC 1 Video Interrupt */
#define irq_comms_block_wd (ibase+124) /* ASC 1 Video Interrupt */
#define irq_fdma_mailbox (ibase+123) /* FDMA Mailbox Output */
#define irq_fdma_gp (ibase+122) /* FDMA GP Output */
#define irq_mips_pic (ibase+121) /* MIPS Performance Counter
* Interrupt */
#define irq_mips_timer (ibase+120) /* MIPS Timer Interrupt */
#define irq_memory_protect (ibase+119) /* Memory Protection Interrupt
* -- Ored by glue logic inside
* SPARC ILC (see
* INT_MEM_PROT_STAT, below,
* for individual interrupts)
*/
/* 118 unused (bit 22) */
#define irq_sbag (ibase+117) /* SBAG Interrupt -- Ored by
* glue logic inside SPARC ILC
* (see INT_SBAG_STAT, below,
* for individual interrupts) */
#define irq_qam_b_fec (ibase+116) /* QAM B FEC Interrupt */
#define irq_qam_a_fec (ibase+115) /* QAM A FEC Interrupt */
/* 114 unused (bit 18) */
#define irq_mailbox (ibase+113) /* Mailbox Debug Interrupt --
* Ored by glue logic inside
* SPARC ILC (see
* INT_MAILBOX_STAT, below, for
* individual interrupts) */
#define irq_fuse_stat1 (ibase+112) /* Fuse Status 1 */
#define irq_fuse_stat2 (ibase+111) /* Fuse Status 2 */
#define irq_fuse_stat3 (ibase+110) /* Blitter Interrupt / Fuse
* Status 3 */
#define irq_blitter (ibase+110) /* Blitter Interrupt / Fuse
* Status 3 */
#define irq_avc1_pp0 (ibase+109) /* AVC Decoder #1 PP0
* Interrupt */
#define irq_avc1_pp1 (ibase+108) /* AVC Decoder #1 PP1
* Interrupt */
#define irq_avc1_mbe (ibase+107) /* AVC Decoder #1 MBE
* Interrupt */
#define irq_avc2_pp0 (ibase+106) /* AVC Decoder #2 PP0
* Interrupt */
#define irq_avc2_pp1 (ibase+105) /* AVC Decoder #2 PP1
* Interrupt */
#define irq_avc2_mbe (ibase+104) /* AVC Decoder #2 MBE
* Interrupt */
#define irq_zbug_spi (ibase+103) /* Zbug SPI Slave Interrupt */
#define irq_qam_mod2 (ibase+102) /* QAM Modulator 2 DMA
* Interrupt */
#define irq_ir_rx (ibase+101) /* IR RX 2 Interrupt */
#define irq_aud_dsp2 (ibase+100) /* Audio DSP #2 Interrupt */
#define irq_aud_dsp1 (ibase+99) /* Audio DSP #1 Interrupt */
#define irq_docsis (ibase+98) /* DOCSIS Debug Interrupt */
#define irq_sd_dvp1 (ibase+97) /* SD DVP #1 Interrupt */
#define irq_sd_dvp2 (ibase+96) /* SD DVP #2 Interrupt */
/*------------- Register: int_stat_2 */
#define irq_hd_dvp (ibase+95) /* HD DVP Interrupt */
#define kIrq_Prewatchdog (ibase+94) /* watchdog Pre-Interrupt */
#define irq_timer2 (ibase+93) /* Programmable Timer
* Interrupt 2 */
#define irq_1394 (ibase+92) /* 1394 Firewire Interrupt */
#define irq_usbohci (ibase+91) /* USB 2.0 OHCI Interrupt */
#define irq_usbehci (ibase+90) /* USB 2.0 EHCI Interrupt */
#define irq_pciexp (ibase+89) /* PCI Express 0 Interrupt */
#define irq_pciexp0 (ibase+89) /* PCI Express 0 Interrupt */
#define irq_afe1 (ibase+88) /* AFE 1 Interrupt */
#define irq_sata (ibase+87) /* SATA 1 Interrupt */
#define irq_sata1 (ibase+87) /* SATA 1 Interrupt */
#define irq_dtcp (ibase+86) /* DTCP Interrupt */
#define irq_pciexp1 (ibase+85) /* PCI Express 1 Interrupt */
/* 84 unused (bit 20) */
/* 83 unused (bit 19) */
/* 82 unused (bit 18) */
#define irq_sata2 (ibase+81) /* SATA2 Interrupt */
#define irq_uart2 (ibase+80) /* UART2 Interrupt */
#define irq_legacy_usb (ibase+79) /* Legacy USB Host ISR (1.1
* Host module) */
#define irq_pod (ibase+78) /* POD Interrupt */
#define irq_slave_usb (ibase+77) /* Slave USB */
#define irq_denc1 (ibase+76) /* DENC #1 VTG Interrupt */
#define irq_vbi_vtg (ibase+75) /* VBI VTG Interrupt */
#define irq_afe2 (ibase+74) /* AFE 2 Interrupt */
#define irq_denc2 (ibase+73) /* DENC #2 VTG Interrupt */
#define irq_asc2 (ibase+72) /* ASC #2 Interrupt */
#define irq_asc1 (ibase+71) /* ASC #1 Interrupt */
#define irq_mod_dma (ibase+70) /* Modulator DMA Interrupt */
#define irq_byte_eng1 (ibase+69) /* Byte Engine Interrupt [1] */
#define irq_byte_eng0 (ibase+68) /* Byte Engine Interrupt [0] */
/* 67 unused (bit 03) */
/* 66 unused (bit 02) */
/* 65 unused (bit 01) */
/* 64 unused (bit 00) */
/*------------- Register: int_stat_1 */
/* 63 unused (bit 31) */
/* 62 unused (bit 30) */
/* 61 unused (bit 29) */
/* 60 unused (bit 28) */
/* 59 unused (bit 27) */
/* 58 unused (bit 26) */
/* 57 unused (bit 25) */
/* 56 unused (bit 24) */
#define irq_buf_dma_mem2mem (ibase+55) /* BufDMA Memory to Memory
* Interrupt */
#define irq_buf_dma_usbtransmit (ibase+54) /* BufDMA USB Transmit
* Interrupt */
#define irq_buf_dma_qpskpodtransmit (ibase+53) /* BufDMA QPSK/POD Tramsit
* Interrupt */
#define irq_buf_dma_transmit_error (ibase+52) /* BufDMA Transmit Error
* Interrupt */
#define irq_buf_dma_usbrecv (ibase+51) /* BufDMA USB Receive
* Interrupt */
#define irq_buf_dma_qpskpodrecv (ibase+50) /* BufDMA QPSK/POD Receive
* Interrupt */
#define irq_buf_dma_recv_error (ibase+49) /* BufDMA Receive Error
* Interrupt */
#define irq_qamdma_transmit_play (ibase+48) /* QAMDMA Transmit/Play
* Interrupt */
#define irq_qamdma_transmit_error (ibase+47) /* QAMDMA Transmit Error
* Interrupt */
#define irq_qamdma_recv2high (ibase+46) /* QAMDMA Receive 2 High
* (Chans 63-32) */
#define irq_qamdma_recv2low (ibase+45) /* QAMDMA Receive 2 Low
* (Chans 31-0) */
#define irq_qamdma_recv1high (ibase+44) /* QAMDMA Receive 1 High
* (Chans 63-32) */
#define irq_qamdma_recv1low (ibase+43) /* QAMDMA Receive 1 Low
* (Chans 31-0) */
#define irq_qamdma_recv_error (ibase+42) /* QAMDMA Receive Error
* Interrupt */
#define irq_mpegsplice (ibase+41) /* MPEG Splice Interrupt */
#define irq_deinterlace_rdy (ibase+40) /* Deinterlacer Frame Ready
* Interrupt */
#define irq_ext_in0 (ibase+39) /* External Interrupt irq_in0 */
#define irq_gpio3 (ibase+38) /* GP I/O IRQ 3 - From GP I/O
* Module */
#define irq_gpio2 (ibase+37) /* GP I/O IRQ 2 - From GP I/O
* Module (ABE_intN) */
#define irq_pcrcmplt1 (ibase+36) /* PCR Capture Complete or
* Discontinuity 1 */
#define irq_pcrcmplt2 (ibase+35) /* PCR Capture Complete or
* Discontinuity 2 */
#define irq_parse_peierr (ibase+34) /* PID Parser Error Detect
* (PEI) */
#define irq_parse_cont_err (ibase+33) /* PID Parser continuity error
* detect */
#define irq_ds1framer (ibase+32) /* DS1 Framer Interrupt */
/*------------- Register: int_stat_0 */
#define irq_gpio1 (ibase+31) /* GP I/O IRQ 1 - From GP I/O
* Module */
#define irq_gpio0 (ibase+30) /* GP I/O IRQ 0 - From GP I/O
* Module */
#define irq_qpsk_out_aloha (ibase+29) /* QPSK Output Slotted Aloha
* (chan 3) Transmission
* Completed OK */
#define irq_qpsk_out_tdma (ibase+28) /* QPSK Output TDMA (chan 2)
* Transmission Completed OK */
#define irq_qpsk_out_reserve (ibase+27) /* QPSK Output Reservation
* (chan 1) Transmission
* Completed OK */
#define irq_qpsk_out_aloha_err (ibase+26) /* QPSK Output Slotted Aloha
* (chan 3)Transmission
* completed with Errors. */
#define irq_qpsk_out_tdma_err (ibase+25) /* QPSK Output TDMA (chan 2)
* Transmission completed with
* Errors. */
#define irq_qpsk_out_rsrv_err (ibase+24) /* QPSK Output Reservation
* (chan 1) Transmission
* completed with Errors */
#define irq_aloha_fail (ibase+23) /* Unsuccessful Resend of Aloha
* for N times. Aloha retry
* timeout for channel 3. */
#define irq_timer1 (ibase+22) /* Programmable Timer
* Interrupt */
#define irq_keyboard (ibase+21) /* Keyboard Module Interrupt */
#define irq_i2c (ibase+20) /* I2C Module Interrupt */
#define irq_spi (ibase+19) /* SPI Module Interrupt */
#define irq_irblaster (ibase+18) /* IR Blaster Interrupt */
#define irq_splice_detect (ibase+17) /* PID Key Change Interrupt or
* Splice Detect Interrupt */
#define irq_se_micro (ibase+16) /* Secure Micro I/F Module
* Interrupt */
#define irq_uart1 (ibase+15) /* UART Interrupt */
#define irq_irrecv (ibase+14) /* IR Receiver Interrupt */
#define irq_host_int1 (ibase+13) /* Host-to-Host Interrupt 1 */
#define irq_host_int0 (ibase+12) /* Host-to-Host Interrupt 0 */
#define irq_qpsk_hecerr (ibase+11) /* QPSK HEC Error Interrupt */
#define irq_qpsk_crcerr (ibase+10) /* QPSK AAL-5 CRC Error
* Interrupt */
/* 9 unused (bit 09) */
/* 8 unused (bit 08) */
#define irq_psicrcerr (ibase+7) /* QAM PSI CRC Error
* Interrupt */
#define irq_psilength_err (ibase+6) /* QAM PSI Length Error
* Interrupt */
#define irq_esfforward (ibase+5) /* ESF Interrupt Mark From
* Forward Path Reference -
* every 3ms when forward Mbits
* and forward slot control
* bytes are updated. */
#define irq_esfreverse (ibase+4) /* ESF Interrupt Mark from
* Reverse Path Reference -
* delayed from forward mark by
* the ranging delay plus a
* fixed amount. When reverse
* Mbits and reverse slot
* control bytes are updated.
* Occurs every 3ms for 3.0M and
* 1.554 M upstream rates and
* every 6 ms for 256K upstream
* rate. */
#define irq_aloha_timeout (ibase+3) /* Slotted-Aloha timeout on
* Channel 1. */
#define irq_reservation (ibase+2) /* Partial (or Incremental)
* Reservation Message Completed
* or Slotted aloha verify for
* channel 1. */
#define irq_aloha3 (ibase+1) /* Slotted-Aloha Message Verify
* Interrupt or Reservation
* increment completed for
* channel 3. */
#define irq_mpeg_d (ibase+0) /* MPEG Decoder Interrupt */
#endif /* _ASM_MACH_POWERTV_INTERRUPTS_H_ */

167
arch/mips/include/asm/mach-powertv/ioremap.h
View File

@ -1,167 +0,0 @@
/*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*
* Portions Copyright (C) Cisco Systems, Inc.
*/
#ifndef __ASM_MACH_POWERTV_IOREMAP_H
#define __ASM_MACH_POWERTV_IOREMAP_H
#include <linux/types.h>
#include <linux/log2.h>
#include <linux/compiler.h>
#include <asm/pgtable-bits.h>
#include <asm/addrspace.h>
/* We're going to mess with bits, so get sizes */
#define IOR_BPC 8 /* Bits per char */
#define IOR_PHYS_BITS (IOR_BPC * sizeof(phys_addr_t))
#define IOR_DMA_BITS (IOR_BPC * sizeof(dma_addr_t))
/*
* Define the granularity of physical/DMA mapping in terms of the number
* of bits that defines the offset within a grain. These will be the
* least significant bits of the address. The rest of a physical or DMA
* address will be used to index into an appropriate table to find the
* offset to add to the address to yield the corresponding DMA or physical
* address, respectively.
*/
#define IOR_LSBITS 22 /* Bits in a grain */
/*
* Compute the number of most significant address bits after removing those
* used for the offset within a grain and then compute the number of table
* entries for the conversion.
*/
#define IOR_PHYS_MSBITS (IOR_PHYS_BITS - IOR_LSBITS)
#define IOR_NUM_PHYS_TO_DMA ((phys_addr_t) 1 << IOR_PHYS_MSBITS)
#define IOR_DMA_MSBITS (IOR_DMA_BITS - IOR_LSBITS)
#define IOR_NUM_DMA_TO_PHYS ((dma_addr_t) 1 << IOR_DMA_MSBITS)
/*
* Define data structures used as elements in the arrays for the conversion
* between physical and DMA addresses. We do some slightly fancy math to
* compute the width of the offset element of the conversion tables so
* that we can have the smallest conversion tables. Next, round up the
* sizes to the next higher power of two, i.e. the offset element will have
* 8, 16, 32, 64, etc. bits. This eliminates the need to mask off any
* bits. Finally, we compute a shift value that puts the most significant
* bits of the offset into the most significant bits of the offset element.
* This makes it more efficient on processors without barrel shifters and
* easier to see the values if the conversion table is dumped in binary.
*/
#define _IOR_OFFSET_WIDTH(n) (1 << order_base_2(n))
#define IOR_OFFSET_WIDTH(n) \
(_IOR_OFFSET_WIDTH(n) < 8 ? 8 : _IOR_OFFSET_WIDTH(n))
#define IOR_PHYS_OFFSET_BITS IOR_OFFSET_WIDTH(IOR_PHYS_MSBITS)
#define IOR_PHYS_SHIFT (IOR_PHYS_BITS - IOR_PHYS_OFFSET_BITS)
#define IOR_DMA_OFFSET_BITS IOR_OFFSET_WIDTH(IOR_DMA_MSBITS)
#define IOR_DMA_SHIFT (IOR_DMA_BITS - IOR_DMA_OFFSET_BITS)
struct ior_phys_to_dma {
dma_addr_t offset:IOR_DMA_OFFSET_BITS __packed
__aligned((IOR_DMA_OFFSET_BITS / IOR_BPC));
};
struct ior_dma_to_phys {
dma_addr_t offset:IOR_PHYS_OFFSET_BITS __packed
__aligned((IOR_PHYS_OFFSET_BITS / IOR_BPC));
};
extern struct ior_phys_to_dma _ior_phys_to_dma[IOR_NUM_PHYS_TO_DMA];
extern struct ior_dma_to_phys _ior_dma_to_phys[IOR_NUM_DMA_TO_PHYS];
static inline dma_addr_t _phys_to_dma_offset_raw(phys_addr_t phys)
{
return (dma_addr_t)_ior_phys_to_dma[phys >> IOR_LSBITS].offset;
}
static inline dma_addr_t _dma_to_phys_offset_raw(dma_addr_t dma)
{
return (dma_addr_t)_ior_dma_to_phys[dma >> IOR_LSBITS].offset;
}
/* These are not portable and should not be used in drivers. Drivers should
* be using ioremap() and friends to map physical addresses to virtual
* addresses and dma_map*() and friends to map virtual addresses into DMA
* addresses and back.
*/
static inline dma_addr_t phys_to_dma(phys_addr_t phys)
{
return phys + (_phys_to_dma_offset_raw(phys) << IOR_PHYS_SHIFT);
}
static inline phys_addr_t dma_to_phys(dma_addr_t dma)
{
return dma + (_dma_to_phys_offset_raw(dma) << IOR_DMA_SHIFT);
}
extern void ioremap_add_map(dma_addr_t phys, phys_addr_t alias,
dma_addr_t size);
/*
* Allow physical addresses to be fixed up to help peripherals located
* outside the low 32-bit range -- generic pass-through version.
*/
static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
{
return phys_addr;
}
/*
* Handle the special case of addresses the area aliased into the first
* 512 MiB of the processor's physical address space. These turn into either
* kseg0 or kseg1 addresses, depending on flags.
*/
static inline void __iomem *plat_ioremap(phys_t start, unsigned long size,
unsigned long flags)
{
phys_addr_t start_offset;
void __iomem *result = NULL;
/* Start by checking to see whether this is an aliased address */
start_offset = _dma_to_phys_offset_raw(start);
/*
* If:
* o the memory is aliased into the first 512 MiB, and
* o the start and end are in the same RAM bank, and
* o we don't have a zero size or wrap around, and
* o we are supposed to create an uncached mapping,
* handle this is a kseg0 or kseg1 address
*/
if (start_offset != 0) {
phys_addr_t last;
dma_addr_t dma_to_phys_offset;
last = start + size - 1;
dma_to_phys_offset =
_dma_to_phys_offset_raw(last) << IOR_DMA_SHIFT;
if (dma_to_phys_offset == start_offset &&
size != 0 && start <= last) {
phys_t adjusted_start;
adjusted_start = start + start_offset;
if (flags == _CACHE_UNCACHED)
result = (void __iomem *) (unsigned long)
CKSEG1ADDR(adjusted_start);
else
result = (void __iomem *) (unsigned long)
CKSEG0ADDR(adjusted_start);
}
}
return result;
}
static inline int plat_iounmap(const volatile void __iomem *addr)
{
return 0;
}
#endif /* __ASM_MACH_POWERTV_IOREMAP_H */

25
arch/mips/include/asm/mach-powertv/irq.h
View File

@ -1,25 +0,0 @@
/*
* Copyright (C) 2009 Cisco Systems, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef _ASM_MACH_POWERTV_IRQ_H
#define _ASM_MACH_POWERTV_IRQ_H
#include <asm/mach-powertv/interrupts.h>
#define MIPS_CPU_IRQ_BASE ibase
#define NR_IRQS 127
#endif

29
arch/mips/include/asm/mach-powertv/powertv-clock.h
View File

@ -1,29 +0,0 @@
/*
* Copyright (C) 2009 Cisco Systems, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/*
* Local definitions for the powertv PCI code
*/
#ifndef _POWERTV_PCI_POWERTV_PCI_H_
#define _POWERTV_PCI_POWERTV_PCI_H_
extern int asic_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
extern int asic_pcie_init(void);
extern int asic_pcie_init(void);
extern int log_level;
#endif

27
arch/mips/include/asm/mach-powertv/war.h
View File

@ -1,27 +0,0 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* This version for the PowerTV platform copied from the Malta version.
*
* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
* Portions copyright (C) 2009 Cisco Systems, Inc.
*/
#ifndef __ASM_MACH_POWERTV_WAR_H
#define __ASM_MACH_POWERTV_WAR_H
#define R4600_V1_INDEX_ICACHEOP_WAR 0
#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
#define R5432_CP0_INTERRUPT_WAR 0
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS4K_ICACHE_REFILL_WAR 1
#define MIPS_CACHE_SYNC_WAR 1
#define TX49XX_ICACHE_INDEX_INV_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR 1
#define R10000_LLSC_WAR 0
#define MIPS34K_MISSED_ITLB_WAR 0
#endif /* __ASM_MACH_POWERTV_WAR_H */

76
arch/mips/include/asm/mips-boards/piix4.h
View File

@ -1,6 +1,7 @@
/*
* Carsten Langgaard, carstenl@mips.com
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
* Copyright (C) 2013 Imagination Technologies Ltd.
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
@ -20,61 +21,26 @@
#ifndef __ASM_MIPS_BOARDS_PIIX4_H
#define __ASM_MIPS_BOARDS_PIIX4_H
/************************************************************************
* IO register offsets
************************************************************************/
#define PIIX4_ICTLR1_ICW1 0x20
#define PIIX4_ICTLR1_ICW2 0x21
#define PIIX4_ICTLR1_ICW3 0x21
#define PIIX4_ICTLR1_ICW4 0x21
#define PIIX4_ICTLR2_ICW1 0xa0
#define PIIX4_ICTLR2_ICW2 0xa1
#define PIIX4_ICTLR2_ICW3 0xa1
#define PIIX4_ICTLR2_ICW4 0xa1
#define PIIX4_ICTLR1_OCW1 0x21
#define PIIX4_ICTLR1_OCW2 0x20
#define PIIX4_ICTLR1_OCW3 0x20
#define PIIX4_ICTLR1_OCW4 0x20
#define PIIX4_ICTLR2_OCW1 0xa1
#define PIIX4_ICTLR2_OCW2 0xa0
#define PIIX4_ICTLR2_OCW3 0xa0
#define PIIX4_ICTLR2_OCW4 0xa0
/* PIRQX Route Control */
#define PIIX4_FUNC0_PIRQRC 0x60
#define PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_DISABLE (1 << 7)
#define PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MASK 0xf
#define PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MAX 16
/* Top Of Memory */
#define PIIX4_FUNC0_TOM 0x69
#define PIIX4_FUNC0_TOM_TOP_OF_MEMORY_MASK 0xf0
/* Deterministic Latency Control */
#define PIIX4_FUNC0_DLC 0x82
#define PIIX4_FUNC0_DLC_USBPR_EN (1 << 2)
#define PIIX4_FUNC0_DLC_PASSIVE_RELEASE_EN (1 << 1)
#define PIIX4_FUNC0_DLC_DELAYED_TRANSACTION_EN (1 << 0)
/************************************************************************
* Register encodings.
************************************************************************/
#define PIIX4_OCW2_NSEOI (0x1 << 5)
#define PIIX4_OCW2_SEOI (0x3 << 5)
#define PIIX4_OCW2_RNSEOI (0x5 << 5)
#define PIIX4_OCW2_RAEOIS (0x4 << 5)
#define PIIX4_OCW2_RAEOIC (0x0 << 5)
#define PIIX4_OCW2_RSEOI (0x7 << 5)
#define PIIX4_OCW2_SP (0x6 << 5)
#define PIIX4_OCW2_NOP (0x2 << 5)
#define PIIX4_OCW2_SEL (0x0 << 3)
#define PIIX4_OCW2_ILS_0 0
#define PIIX4_OCW2_ILS_1 1
#define PIIX4_OCW2_ILS_2 2
#define PIIX4_OCW2_ILS_3 3
#define PIIX4_OCW2_ILS_4 4
#define PIIX4_OCW2_ILS_5 5
#define PIIX4_OCW2_ILS_6 6
#define PIIX4_OCW2_ILS_7 7
#define PIIX4_OCW2_ILS_8 0
#define PIIX4_OCW2_ILS_9 1
#define PIIX4_OCW2_ILS_10 2
#define PIIX4_OCW2_ILS_11 3
#define PIIX4_OCW2_ILS_12 4
#define PIIX4_OCW2_ILS_13 5
#define PIIX4_OCW2_ILS_14 6
#define PIIX4_OCW2_ILS_15 7
#define PIIX4_OCW3_SEL (0x1 << 3)
#define PIIX4_OCW3_IRR 0x2
#define PIIX4_OCW3_ISR 0x3
/* IDE Timing */
#define PIIX4_FUNC1_IDETIM_PRIMARY_LO 0x40
#define PIIX4_FUNC1_IDETIM_PRIMARY_HI 0x41
#define PIIX4_FUNC1_IDETIM_PRIMARY_HI_IDE_DECODE_EN (1 << 7)
#define PIIX4_FUNC1_IDETIM_SECONDARY_LO 0x42
#define PIIX4_FUNC1_IDETIM_SECONDARY_HI 0x43
#define PIIX4_FUNC1_IDETIM_SECONDARY_HI_IDE_DECODE_EN (1 << 7)
#endif /* __ASM_MIPS_BOARDS_PIIX4_H */

22
arch/mips/include/asm/mmu_context.h
View File

@ -24,21 +24,21 @@
#endif /* SMTC */
#include <asm-generic/mm_hooks.h>
#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
#define TLBMISS_HANDLER_SETUP_PGD(pgd) \
do { \
extern void tlbmiss_handler_setup_pgd(unsigned long); \
tlbmiss_handler_setup_pgd((unsigned long)(pgd)); \
} while (0)
#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
#define TLBMISS_HANDLER_SETUP() \
do { \
TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir); \
write_c0_xcontext((unsigned long) smp_processor_id() << 51); \
write_c0_xcontext((unsigned long) smp_processor_id() << \
SMP_CPUID_REGSHIFT); \
} while (0)
#else /* CONFIG_MIPS_PGD_C0_CONTEXT: using pgd_current*/
#else /* !CONFIG_MIPS_PGD_C0_CONTEXT: using pgd_current*/
/*
* For the fast tlb miss handlers, we keep a per cpu array of pointers
@ -47,21 +47,11 @@ do { \
*/
extern unsigned long pgd_current[];
#define TLBMISS_HANDLER_SETUP_PGD(pgd) \
pgd_current[smp_processor_id()] = (unsigned long)(pgd)
#ifdef CONFIG_32BIT
#define TLBMISS_HANDLER_SETUP() \
write_c0_context((unsigned long) smp_processor_id() << 25); \
write_c0_context((unsigned long) smp_processor_id() << \
SMP_CPUID_REGSHIFT); \
back_to_back_c0_hazard(); \
TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
#endif
#ifdef CONFIG_64BIT
#define TLBMISS_HANDLER_SETUP() \
write_c0_context((unsigned long) smp_processor_id() << 26); \
back_to_back_c0_hazard(); \
TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
#endif
#endif /* CONFIG_MIPS_PGD_C0_CONTEXT*/
#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)

14
arch/mips/include/asm/ptrace.h
View File

@ -81,7 +81,6 @@ static inline long regs_return_value(struct pt_regs *regs)
#define instruction_pointer(regs) ((regs)->cp0_epc)
#define profile_pc(regs) instruction_pointer(regs)
#define user_stack_pointer(r) ((r)->regs[29])
extern asmlinkage void syscall_trace_enter(struct pt_regs *regs);
extern asmlinkage void syscall_trace_leave(struct pt_regs *regs);
@ -100,4 +99,17 @@ static inline void die_if_kernel(const char *str, struct pt_regs *regs)
(struct pt_regs *)((sp | (THREAD_SIZE - 1)) + 1 - 32) - 1; \
})
/* Helpers for working with the user stack pointer */
static inline unsigned long user_stack_pointer(struct pt_regs *regs)
{
return regs->regs[29];
}
static inline void user_stack_pointer_set(struct pt_regs *regs,
unsigned long val)
{
regs->regs[29] = val;
}
#endif /* _ASM_PTRACE_H */

41
arch/mips/include/asm/r4kcache.h
View File

@ -15,6 +15,7 @@
#include <asm/asm.h>
#include <asm/cacheops.h>
#include <asm/cpu-features.h>
#include <asm/cpu-type.h>
#include <asm/mipsmtregs.h>
/*
@ -162,7 +163,15 @@ static inline void flush_scache_line_indexed(unsigned long addr)
static inline void flush_icache_line(unsigned long addr)
{
__iflush_prologue
cache_op(Hit_Invalidate_I, addr);
switch (boot_cpu_type()) {
case CPU_LOONGSON2:
cache_op(Hit_Invalidate_I_Loongson23, addr);
break;
default:
cache_op(Hit_Invalidate_I, addr);
break;
}
__iflush_epilogue
}
@ -208,7 +217,15 @@ static inline void flush_scache_line(unsigned long addr)
*/
static inline void protected_flush_icache_line(unsigned long addr)
{
protected_cache_op(Hit_Invalidate_I, addr);
switch (boot_cpu_type()) {
case CPU_LOONGSON2:
protected_cache_op(Hit_Invalidate_I_Loongson23, addr);
break;
default:
protected_cache_op(Hit_Invalidate_I, addr);
break;
}
}
/*
@ -412,8 +429,8 @@ __BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64
__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128)
/* build blast_xxx_range, protected_blast_xxx_range */
#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot) \
static inline void prot##blast_##pfx##cache##_range(unsigned long start, \
#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, extra) \
static inline void prot##extra##blast_##pfx##cache##_range(unsigned long start, \
unsigned long end) \
{ \
unsigned long lsize = cpu_##desc##_line_size(); \
@ -432,13 +449,15 @@ static inline void prot##blast_##pfx##cache##_range(unsigned long start, \
__##pfx##flush_epilogue \
}
__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_)
__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_)
__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_)
__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, )
__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, )
__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, )
__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_, )
__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, )
__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I_Loongson23, \
protected_, loongson23_)
__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , )
__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, , )
/* blast_inv_dcache_range */
__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, )
__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, )
__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, , )
__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, , )
#endif /* _ASM_R4KCACHE_H */

8
arch/mips/include/asm/setup.h
View File

@ -5,6 +5,14 @@
extern void setup_early_printk(void);
#ifdef CONFIG_EARLY_PRINTK_8250
extern void setup_8250_early_printk_port(unsigned long base,
unsigned int reg_shift, unsigned int timeout);
#else
static inline void setup_8250_early_printk_port(unsigned long base,
unsigned int reg_shift, unsigned int timeout) {}
#endif
extern void set_handler(unsigned long offset, void *addr, unsigned long len);
extern void set_uncached_handler(unsigned long offset, void *addr, unsigned long len);

24
arch/mips/include/asm/stackframe.h
View File

@ -17,6 +17,7 @@
#include <asm/asmmacro.h>
#include <asm/mipsregs.h>
#include <asm/asm-offsets.h>
#include <asm/thread_info.h>
/*
* For SMTC kernel, global IE should be left set, and interrupts
@ -93,21 +94,8 @@
.endm
#ifdef CONFIG_SMP
#ifdef CONFIG_MIPS_MT_SMTC
#define PTEBASE_SHIFT 19 /* TCBIND */
#define CPU_ID_REG CP0_TCBIND
#define CPU_ID_MFC0 mfc0
#elif defined(CONFIG_MIPS_PGD_C0_CONTEXT)
#define PTEBASE_SHIFT 48 /* XCONTEXT */
#define CPU_ID_REG CP0_XCONTEXT
#define CPU_ID_MFC0 MFC0
#else
#define PTEBASE_SHIFT 23 /* CONTEXT */
#define CPU_ID_REG CP0_CONTEXT
#define CPU_ID_MFC0 MFC0
#endif
.macro get_saved_sp /* SMP variation */
CPU_ID_MFC0 k0, CPU_ID_REG
ASM_CPUID_MFC0 k0, ASM_SMP_CPUID_REG
#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32)
lui k1, %hi(kernelsp)
#else
@ -117,17 +105,17 @@
daddiu k1, %hi(kernelsp)
dsll k1, 16
#endif
LONG_SRL k0, PTEBASE_SHIFT
LONG_SRL k0, SMP_CPUID_PTRSHIFT
LONG_ADDU k1, k0
LONG_L k1, %lo(kernelsp)(k1)
.endm
.macro set_saved_sp stackp temp temp2
CPU_ID_MFC0 \temp, CPU_ID_REG
LONG_SRL \temp, PTEBASE_SHIFT
ASM_CPUID_MFC0 \temp, ASM_SMP_CPUID_REG
LONG_SRL \temp, SMP_CPUID_PTRSHIFT
LONG_S \stackp, kernelsp(\temp)
.endm
#else
#else /* !CONFIG_SMP */
.macro get_saved_sp /* Uniprocessor variation */
#ifdef CONFIG_CPU_JUMP_WORKAROUNDS
/*

116
arch/mips/include/asm/syscall.h Normal file
View File

@ -0,0 +1,116 @@
/*
* Access to user system call parameters and results
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* See asm-generic/syscall.h for descriptions of what we must do here.
*
* Copyright (C) 2012 Ralf Baechle <ralf@linux-mips.org>
*/
#ifndef __ASM_MIPS_SYSCALL_H
#define __ASM_MIPS_SYSCALL_H
#include <linux/audit.h>
#include <linux/elf-em.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/uaccess.h>
#include <asm/ptrace.h>
static inline long syscall_get_nr(struct task_struct *task,
struct pt_regs *regs)
{
return regs->regs[2];
}
static inline unsigned long mips_get_syscall_arg(unsigned long *arg,
struct task_struct *task, struct pt_regs *regs, unsigned int n)
{
unsigned long usp = regs->regs[29];
switch (n) {
case 0: case 1: case 2: case 3:
*arg = regs->regs[4 + n];
return 0;
#ifdef CONFIG_32BIT
case 4: case 5: case 6: case 7:
return get_user(*arg, (int *)usp + 4 * n);
#endif
#ifdef CONFIG_64BIT
case 4: case 5: case 6: case 7:
#ifdef CONFIG_MIPS32_O32
if (test_thread_flag(TIF_32BIT_REGS))
return get_user(*arg, (int *)usp + 4 * n);
else
#endif
*arg = regs->regs[4 + n];
return 0;
#endif
default:
BUG();
}
}
static inline long syscall_get_return_value(struct task_struct *task,
struct pt_regs *regs)
{
return regs->regs[2];
}
static inline void syscall_set_return_value(struct task_struct *task,
struct pt_regs *regs,
int error, long val)
{
if (error) {
regs->regs[2] = -error;
regs->regs[7] = -1;
} else {
regs->regs[2] = val;
regs->regs[7] = 0;
}
}
static inline void syscall_get_arguments(struct task_struct *task,
struct pt_regs *regs,
unsigned int i, unsigned int n,
unsigned long *args)
{
unsigned long arg;
int ret;
while (n--)
ret |= mips_get_syscall_arg(&arg, task, regs, i++);
/*
* No way to communicate an error because this is a void function.
*/
#if 0
return ret;
#endif
}
extern const unsigned long sys_call_table[];
extern const unsigned long sys32_call_table[];
extern const unsigned long sysn32_call_table[];
static inline int __syscall_get_arch(void)
{
int arch = EM_MIPS;
#ifdef CONFIG_64BIT
arch |= __AUDIT_ARCH_64BIT;
#endif
#if defined(__LITTLE_ENDIAN)
arch |= __AUDIT_ARCH_LE;
#endif
return arch;
}
#endif /* __ASM_MIPS_SYSCALL_H */

42
arch/mips/include/asm/thread_info.h
View File

@ -116,6 +116,7 @@ static inline struct thread_info *current_thread_info(void)
#define TIF_32BIT_ADDR 23 /* 32-bit address space (o32/n32) */
#define TIF_FPUBOUND 24 /* thread bound to FPU-full CPU set */
#define TIF_LOAD_WATCH 25 /* If set, load watch registers */
#define TIF_SYSCALL_TRACEPOINT 26 /* syscall tracepoint instrumentation */
#define TIF_SYSCALL_TRACE 31 /* syscall trace active */
#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE)
@ -132,21 +133,54 @@ static inline struct thread_info *current_thread_info(void)
#define _TIF_32BIT_ADDR (1<<TIF_32BIT_ADDR)
#define _TIF_FPUBOUND (1<<TIF_FPUBOUND)
#define _TIF_LOAD_WATCH (1<<TIF_LOAD_WATCH)
#define _TIF_SYSCALL_TRACEPOINT (1<<TIF_SYSCALL_TRACEPOINT)
#define _TIF_WORK_SYSCALL_ENTRY (_TIF_NOHZ | _TIF_SYSCALL_TRACE | \
_TIF_SYSCALL_AUDIT)
_TIF_SYSCALL_AUDIT | _TIF_SYSCALL_TRACEPOINT)
/* work to do in syscall_trace_leave() */
#define _TIF_WORK_SYSCALL_EXIT (_TIF_NOHZ | _TIF_SYSCALL_TRACE | \
_TIF_SYSCALL_AUDIT)
_TIF_SYSCALL_AUDIT | _TIF_SYSCALL_TRACEPOINT)
/* work to do on interrupt/exception return */
#define _TIF_WORK_MASK \
(_TIF_SIGPENDING | _TIF_NEED_RESCHED | _TIF_NOTIFY_RESUME)
/* work to do on any return to u-space */
#define _TIF_ALLWORK_MASK (_TIF_NOHZ | _TIF_WORK_MASK | \
_TIF_WORK_SYSCALL_EXIT)
_TIF_WORK_SYSCALL_EXIT | \
_TIF_SYSCALL_TRACEPOINT)
/*
* We stash processor id into a COP0 register to retrieve it fast
* at kernel exception entry.
*/
#if defined(CONFIG_MIPS_MT_SMTC)
#define SMP_CPUID_REG 2, 2 /* TCBIND */
#define ASM_SMP_CPUID_REG $2, 2
#define SMP_CPUID_PTRSHIFT 19
#elif defined(CONFIG_MIPS_PGD_C0_CONTEXT)
#define SMP_CPUID_REG 20, 0 /* XCONTEXT */
#define ASM_SMP_CPUID_REG $20
#define SMP_CPUID_PTRSHIFT 48
#else
#define SMP_CPUID_REG 4, 0 /* CONTEXT */
#define ASM_SMP_CPUID_REG $4
#define SMP_CPUID_PTRSHIFT 23
#endif
#ifdef CONFIG_64BIT
#define SMP_CPUID_REGSHIFT (SMP_CPUID_PTRSHIFT + 3)
#else
#define SMP_CPUID_REGSHIFT (SMP_CPUID_PTRSHIFT + 2)
#endif
#ifdef CONFIG_MIPS_MT_SMTC
#define ASM_CPUID_MFC0 mfc0
#define UASM_i_CPUID_MFC0 uasm_i_mfc0
#else
#define ASM_CPUID_MFC0 MFC0
#define UASM_i_CPUID_MFC0 UASM_i_MFC0
#endif
#endif /* __KERNEL__ */
#endif /* _ASM_THREAD_INFO_H */

2
arch/mips/include/asm/time.h
View File

@ -75,7 +75,7 @@ extern int init_r4k_clocksource(void);
static inline int init_mips_clocksource(void)
{
#if defined(CONFIG_CSRC_R4K) && !defined(CONFIG_CSRC_GIC)
#ifdef CONFIG_CSRC_R4K
return init_r4k_clocksource();
#else
return 0;

7
arch/mips/include/asm/unistd.h
View File

@ -14,6 +14,13 @@
#include <uapi/asm/unistd.h>
#ifdef CONFIG_MIPS32_N32
#define NR_syscalls (__NR_N32_Linux + __NR_N32_Linux_syscalls)
#elif defined(CONFIG_64BIT)
#define NR_syscalls (__NR_64_Linux + __NR_64_Linux_syscalls)
#else
#define NR_syscalls (__NR_O32_Linux + __NR_O32_Linux_syscalls)
#endif
#ifndef __ASSEMBLY__

9
arch/mips/include/uapi/asm/siginfo.h
View File

@ -33,6 +33,8 @@ struct siginfo;
#error _MIPS_SZLONG neither 32 nor 64
#endif
#define __ARCH_SIGSYS
#include <asm-generic/siginfo.h>
typedef struct siginfo {
@ -97,6 +99,13 @@ typedef struct siginfo {
__ARCH_SI_BAND_T _band; /* POLL_IN, POLL_OUT, POLL_MSG */
int _fd;
} _sigpoll;
/* SIGSYS */
struct {
void __user *_call_addr; /* calling user insn */
int _syscall; /* triggering system call number */
unsigned int _arch; /* AUDIT_ARCH_* of syscall */
} _sigsys;
} _sifields;
} siginfo_t;

3
arch/mips/kernel/Makefile
View File

@ -26,7 +26,6 @@ obj-$(CONFIG_CEVT_TXX9) += cevt-txx9.o
obj-$(CONFIG_CSRC_BCM1480) += csrc-bcm1480.o
obj-$(CONFIG_CSRC_GIC) += csrc-gic.o
obj-$(CONFIG_CSRC_IOASIC) += csrc-ioasic.o
obj-$(CONFIG_CSRC_POWERTV) += csrc-powertv.o
obj-$(CONFIG_CSRC_R4K) += csrc-r4k.o
obj-$(CONFIG_CSRC_SB1250) += csrc-sb1250.o
obj-$(CONFIG_SYNC_R4K) += sync-r4k.o
@ -35,6 +34,7 @@ obj-$(CONFIG_STACKTRACE) += stacktrace.o
obj-$(CONFIG_MODULES) += mips_ksyms.o module.o
obj-$(CONFIG_MODULES_USE_ELF_RELA) += module-rela.o
obj-$(CONFIG_FTRACE_SYSCALLS) += ftrace.o
obj-$(CONFIG_FUNCTION_TRACER) += mcount.o ftrace.o
obj-$(CONFIG_CPU_R4K_FPU) += r4k_fpu.o r4k_switch.o
@ -84,6 +84,7 @@ obj-$(CONFIG_GPIO_TXX9) += gpio_txx9.o
obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel.o crash.o
obj-$(CONFIG_CRASH_DUMP) += crash_dump.o
obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
obj-$(CONFIG_EARLY_PRINTK_8250) += early_printk_8250.o
obj-$(CONFIG_SPINLOCK_TEST) += spinlock_test.o
obj-$(CONFIG_MIPS_MACHINE) += mips_machine.o

32
arch/mips/kernel/cpu-probe.c
View File

@ -376,13 +376,33 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
__cpu_name[cpu] = "R4000PC";
}
} else {
int cca = read_c0_config() & CONF_CM_CMASK;
int mc;
/*
* SC and MC versions can't be reliably told apart,
* but only the latter support coherent caching
* modes so assume the firmware has set the KSEG0
* coherency attribute reasonably (if uncached, we
* assume SC).
*/
switch (cca) {
case CONF_CM_CACHABLE_CE:
case CONF_CM_CACHABLE_COW:
case CONF_CM_CACHABLE_CUW:
mc = 1;
break;
default:
mc = 0;
break;
}
if ((c->processor_id & PRID_REV_MASK) >=
PRID_REV_R4400) {
c->cputype = CPU_R4400SC;
__cpu_name[cpu] = "R4400SC";
c->cputype = mc ? CPU_R4400MC : CPU_R4400SC;
__cpu_name[cpu] = mc ? "R4400MC" : "R4400SC";
} else {
c->cputype = CPU_R4000SC;
__cpu_name[cpu] = "R4000SC";
c->cputype = mc ? CPU_R4000MC : CPU_R4000SC;
__cpu_name[cpu] = mc ? "R4000MC" : "R4000SC";
}
}
@ -1079,8 +1099,8 @@ void cpu_report(void)
{
struct cpuinfo_mips *c = &current_cpu_data;
printk(KERN_INFO "CPU revision is: %08x (%s)\n",
c->processor_id, cpu_name_string());
pr_info("CPU%d revision is: %08x (%s)\n",
smp_processor_id(), c->processor_id, cpu_name_string());
if (c->options & MIPS_CPU_FPU)
printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
}

151
arch/mips/kernel/csrc-powertv.c
View File

@ -1,151 +0,0 @@
/*
* Copyright (C) 2008 Scientific-Atlanta, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
/*
* The file comes from kernel/csrc-r4k.c
*/
#include <linux/clocksource.h>
#include <linux/init.h>
#include <asm/time.h> /* Not included in linux/time.h */
#include <asm/mach-powertv/asic_regs.h>
#include "powertv-clock.h"
/* MIPS PLL Register Definitions */
#define PLL_GET_M(x) (((x) >> 8) & 0x000000FF)
#define PLL_GET_N(x) (((x) >> 16) & 0x000000FF)
#define PLL_GET_P(x) (((x) >> 24) & 0x00000007)
/*
* returns: Clock frequency in kHz
*/
unsigned int __init mips_get_pll_freq(void)
{
unsigned int pll_reg, m, n, p;
unsigned int fin = 54000; /* Base frequency in kHz */
unsigned int fout;
/* Read PLL register setting */
pll_reg = asic_read(mips_pll_setup);
m = PLL_GET_M(pll_reg);
n = PLL_GET_N(pll_reg);
p = PLL_GET_P(pll_reg);
pr_info("MIPS PLL Register:0x%x M=%d N=%d P=%d\n", pll_reg, m, n, p);
/* Calculate clock frequency = (2 * N * 54MHz) / (M * (2**P)) */
fout = ((2 * n * fin) / (m * (0x01 << p)));
pr_info("MIPS Clock Freq=%d kHz\n", fout);
return fout;
}
static cycle_t c0_hpt_read(struct clocksource *cs)
{
return read_c0_count();
}
static struct clocksource clocksource_mips = {
.name = "powertv-counter",
.read = c0_hpt_read,
.mask = CLOCKSOURCE_MASK(32),
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
};
static void __init powertv_c0_hpt_clocksource_init(void)
{
unsigned int pll_freq = mips_get_pll_freq();
pr_info("CPU frequency %d.%02d MHz\n", pll_freq / 1000,
(pll_freq % 1000) * 100 / 1000);
mips_hpt_frequency = pll_freq / 2 * 1000;
clocksource_mips.rating = 200 + mips_hpt_frequency / 10000000;
clocksource_register_hz(&clocksource_mips, mips_hpt_frequency);
}
/**
* struct tim_c - free running counter
* @hi: High 16 bits of the counter
* @lo: Low 32 bits of the counter
*
* Lays out the structure of the free running counter in memory. This counter
* increments at a rate of 27 MHz/8 on all platforms.
*/
struct tim_c {
unsigned int hi;
unsigned int lo;
};
static struct tim_c *tim_c;
static cycle_t tim_c_read(struct clocksource *cs)
{
unsigned int hi;
unsigned int next_hi;
unsigned int lo;
hi = readl(&tim_c->hi);
for (;;) {
lo = readl(&tim_c->lo);
next_hi = readl(&tim_c->hi);
if (next_hi == hi)
break;
hi = next_hi;
}
pr_crit("%s: read %llx\n", __func__, ((u64) hi << 32) | lo);
return ((u64) hi << 32) | lo;
}
#define TIM_C_SIZE 48 /* # bits in the timer */
static struct clocksource clocksource_tim_c = {
.name = "powertv-tim_c",
.read = tim_c_read,
.mask = CLOCKSOURCE_MASK(TIM_C_SIZE),
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
};
/**
* powertv_tim_c_clocksource_init - set up a clock source for the TIM_C clock
*
* We know that TIM_C counts at 27 MHz/8, so each cycle corresponds to
* 1 / (27,000,000/8) seconds.
*/
static void __init powertv_tim_c_clocksource_init(void)
{
const unsigned long counts_per_second = 27000000 / 8;
clocksource_tim_c.rating = 200;
clocksource_register_hz(&clocksource_tim_c, counts_per_second);
tim_c = (struct tim_c *) asic_reg_addr(tim_ch);
}
/**
powertv_clocksource_init - initialize all clocksources
*/
void __init powertv_clocksource_init(void)
{
powertv_c0_hpt_clocksource_init();
powertv_tim_c_clocksource_init();
}

66
arch/mips/kernel/early_printk_8250.c Normal file
View File

@ -0,0 +1,66 @@
/*
* 8250/16550-type serial ports prom_putchar()
*
* Copyright (C) 2010 Yoichi Yuasa <yuasa@linux-mips.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <linux/io.h>
#include <linux/serial_core.h>
#include <linux/serial_reg.h>
static void __iomem *serial8250_base;
static unsigned int serial8250_reg_shift;
static unsigned int serial8250_tx_timeout;
void setup_8250_early_printk_port(unsigned long base, unsigned int reg_shift,
unsigned int timeout)
{
serial8250_base = (void __iomem *)base;
serial8250_reg_shift = reg_shift;
serial8250_tx_timeout = timeout;
}
static inline u8 serial_in(int offset)
{
return readb(serial8250_base + (offset << serial8250_reg_shift));
}
static inline void serial_out(int offset, char value)
{
writeb(value, serial8250_base + (offset << serial8250_reg_shift));
}
void prom_putchar(char c)
{
unsigned int timeout;
int status, bits;
if (!serial8250_base)
return;
timeout = serial8250_tx_timeout;
bits = UART_LSR_TEMT | UART_LSR_THRE;
do {
status = serial_in(UART_LSR);
if (--timeout == 0)
break;
} while ((status & bits) != bits);
if (timeout)
serial_out(UART_TX, c);
}

33
arch/mips/kernel/ftrace.c
View File

@ -11,11 +11,14 @@
#include <linux/uaccess.h>
#include <linux/init.h>
#include <linux/ftrace.h>
#include <linux/syscalls.h>
#include <asm/asm.h>
#include <asm/asm-offsets.h>
#include <asm/cacheflush.h>
#include <asm/syscall.h>
#include <asm/uasm.h>
#include <asm/unistd.h>
#include <asm-generic/sections.h>
@ -364,3 +367,33 @@ out:
WARN_ON(1);
}
#endif /* CONFIG_FUNCTION_GRAPH_TRACER */
#ifdef CONFIG_FTRACE_SYSCALLS
#ifdef CONFIG_32BIT
unsigned long __init arch_syscall_addr(int nr)
{
return (unsigned long)sys_call_table[nr - __NR_O32_Linux];
}
#endif
#ifdef CONFIG_64BIT
unsigned long __init arch_syscall_addr(int nr)
{
#ifdef CONFIG_MIPS32_N32
if (nr >= __NR_N32_Linux && nr <= __NR_N32_Linux + __NR_N32_Linux_syscalls)
return (unsigned long)sysn32_call_table[nr - __NR_N32_Linux];
#endif
if (nr >= __NR_64_Linux && nr <= __NR_64_Linux + __NR_64_Linux_syscalls)
return (unsigned long)sys_call_table[nr - __NR_64_Linux];
#ifdef CONFIG_MIPS32_O32
if (nr >= __NR_O32_Linux && nr <= __NR_O32_Linux + __NR_O32_Linux_syscalls)
return (unsigned long)sys32_call_table[nr - __NR_O32_Linux];
#endif
return (unsigned long) &sys_ni_syscall;
}
#endif
#endif /* CONFIG_FTRACE_SYSCALLS */

14
arch/mips/kernel/genex.S
View File

@ -374,12 +374,20 @@ NESTED(except_vec_nmi, 0, sp)
NESTED(nmi_handler, PT_SIZE, sp)
.set push
.set noat
/*
* Clear ERL - restore segment mapping
* Clear BEV - required for page fault exception handler to work
*/
mfc0 k0, CP0_STATUS
ori k0, k0, ST0_EXL
li k1, ~(ST0_BEV | ST0_ERL)
and k0, k0, k1
mtc0 k0, CP0_STATUS
_ehb
SAVE_ALL
move a0, sp
jal nmi_exception_handler
RESTORE_ALL
.set mips3
eret
/* nmi_exception_handler never returns */
.set pop
END(nmi_handler)

2
arch/mips/kernel/irq_cpu.c
View File

@ -150,7 +150,7 @@ int __init mips_cpu_intc_init(struct device_node *of_node,
domain = irq_domain_add_legacy(of_node, 8, MIPS_CPU_IRQ_BASE, 0,
&mips_cpu_intc_irq_domain_ops, NULL);
if (!domain)
panic("Failed to add irqdomain for MIPS CPU\n");
panic("Failed to add irqdomain for MIPS CPU");
return 0;
}

3
arch/mips/kernel/module.c
View File

@ -23,6 +23,7 @@
#include <linux/moduleloader.h>
#include <linux/elf.h>
#include <linux/mm.h>
#include <linux/numa.h>
#include <linux/vmalloc.h>
#include <linux/slab.h>
#include <linux/fs.h>
@ -46,7 +47,7 @@ static DEFINE_SPINLOCK(dbe_lock);
void *module_alloc(unsigned long size)
{
return __vmalloc_node_range(size, 1, MODULE_START, MODULE_END,
GFP_KERNEL, PAGE_KERNEL, -1,
GFP_KERNEL, PAGE_KERNEL, NUMA_NO_NODE,
__builtin_return_address(0));
}
#endif

199
arch/mips/kernel/ptrace.c
View File

@ -16,16 +16,20 @@
*/
#include <linux/compiler.h>
#include <linux/context_tracking.h>
#include <linux/elf.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/mm.h>
#include <linux/errno.h>
#include <linux/ptrace.h>
#include <linux/regset.h>
#include <linux/smp.h>
#include <linux/user.h>
#include <linux/security.h>
#include <linux/tracehook.h>
#include <linux/audit.h>
#include <linux/seccomp.h>
#include <linux/ftrace.h>
#include <asm/byteorder.h>
#include <asm/cpu.h>
@ -35,10 +39,14 @@
#include <asm/mipsmtregs.h>
#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/syscall.h>
#include <asm/uaccess.h>
#include <asm/bootinfo.h>
#include <asm/reg.h>
#define CREATE_TRACE_POINTS
#include <trace/events/syscalls.h>
/*
* Called by kernel/ptrace.c when detaching..
*
@ -255,6 +263,133 @@ int ptrace_set_watch_regs(struct task_struct *child,
return 0;
}
/* regset get/set implementations */
static int gpr_get(struct task_struct *target,
const struct user_regset *regset,
unsigned int pos, unsigned int count,
void *kbuf, void __user *ubuf)
{
struct pt_regs *regs = task_pt_regs(target);
return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
regs, 0, sizeof(*regs));
}
static int gpr_set(struct task_struct *target,
const struct user_regset *regset,
unsigned int pos, unsigned int count,
const void *kbuf, const void __user *ubuf)
{
struct pt_regs newregs;
int ret;
ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
&newregs,
0, sizeof(newregs));
if (ret)
return ret;
*task_pt_regs(target) = newregs;
return 0;
}
static int fpr_get(struct task_struct *target,
const struct user_regset *regset,
unsigned int pos, unsigned int count,
void *kbuf, void __user *ubuf)
{
return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
&target->thread.fpu,
0, sizeof(elf_fpregset_t));
/* XXX fcr31 */
}
static int fpr_set(struct task_struct *target,
const struct user_regset *regset,
unsigned int pos, unsigned int count,
const void *kbuf, const void __user *ubuf)
{
return user_regset_copyin(&pos, &count, &kbuf, &ubuf,
&target->thread.fpu,
0, sizeof(elf_fpregset_t));
/* XXX fcr31 */
}
enum mips_regset {
REGSET_GPR,
REGSET_FPR,
};
static const struct user_regset mips_regsets[] = {
[REGSET_GPR] = {
.core_note_type = NT_PRSTATUS,
.n = ELF_NGREG,
.size = sizeof(unsigned int),
.align = sizeof(unsigned int),
.get = gpr_get,
.set = gpr_set,
},
[REGSET_FPR] = {
.core_note_type = NT_PRFPREG,
.n = ELF_NFPREG,
.size = sizeof(elf_fpreg_t),
.align = sizeof(elf_fpreg_t),
.get = fpr_get,
.set = fpr_set,
},
};
static const struct user_regset_view user_mips_view = {
.name = "mips",
.e_machine = ELF_ARCH,
.ei_osabi = ELF_OSABI,
.regsets = mips_regsets,
.n = ARRAY_SIZE(mips_regsets),
};
static const struct user_regset mips64_regsets[] = {
[REGSET_GPR] = {
.core_note_type = NT_PRSTATUS,
.n = ELF_NGREG,
.size = sizeof(unsigned long),
.align = sizeof(unsigned long),
.get = gpr_get,
.set = gpr_set,
},
[REGSET_FPR] = {
.core_note_type = NT_PRFPREG,
.n = ELF_NFPREG,
.size = sizeof(elf_fpreg_t),
.align = sizeof(elf_fpreg_t),
.get = fpr_get,
.set = fpr_set,
},
};
static const struct user_regset_view user_mips64_view = {
.name = "mips",
.e_machine = ELF_ARCH,
.ei_osabi = ELF_OSABI,
.regsets = mips64_regsets,
.n = ARRAY_SIZE(mips_regsets),
};
const struct user_regset_view *task_user_regset_view(struct task_struct *task)
{
#ifdef CONFIG_32BIT
return &user_mips_view;
#endif
#ifdef CONFIG_MIPS32_O32
if (test_thread_flag(TIF_32BIT_REGS))
return &user_mips_view;
#endif
return &user_mips64_view;
}
long arch_ptrace(struct task_struct *child, long request,
unsigned long addr, unsigned long data)
{
@ -517,52 +652,27 @@ long arch_ptrace(struct task_struct *child, long request,
return ret;
}
static inline int audit_arch(void)
{
int arch = EM_MIPS;
#ifdef CONFIG_64BIT
arch |= __AUDIT_ARCH_64BIT;
#endif
#if defined(__LITTLE_ENDIAN)
arch |= __AUDIT_ARCH_LE;
#endif
return arch;
}
/*
* Notification of system call entry/exit
* - triggered by current->work.syscall_trace
*/
asmlinkage void syscall_trace_enter(struct pt_regs *regs)
{
long ret = 0;
user_exit();
/* do the secure computing check first */
secure_computing_strict(regs->regs[2]);
if (!(current->ptrace & PT_PTRACED))
goto out;
if (test_thread_flag(TIF_SYSCALL_TRACE) &&
tracehook_report_syscall_entry(regs))
ret = -1;
if (!test_thread_flag(TIF_SYSCALL_TRACE))
goto out;
if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT)))
trace_sys_enter(regs, regs->regs[2]);
/* The 0x80 provides a way for the tracing parent to distinguish
between a syscall stop and SIGTRAP delivery */
ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD) ?
0x80 : 0));
/*
* this isn't the same as continuing with a signal, but it will do
* for normal use. strace only continues with a signal if the
* stopping signal is not SIGTRAP. -brl
*/
if (current->exit_code) {
send_sig(current->exit_code, current, 1);
current->exit_code = 0;
}
out:
audit_syscall_entry(audit_arch(), regs->regs[2],
audit_syscall_entry(__syscall_get_arch(),
regs->regs[2],
regs->regs[4], regs->regs[5],
regs->regs[6], regs->regs[7]);
}
@ -582,26 +692,11 @@ asmlinkage void syscall_trace_leave(struct pt_regs *regs)
audit_syscall_exit(regs);
if (!(current->ptrace & PT_PTRACED))
return;
if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT)))
trace_sys_exit(regs, regs->regs[2]);
if (!test_thread_flag(TIF_SYSCALL_TRACE))
return;
/* The 0x80 provides a way for the tracing parent to distinguish
between a syscall stop and SIGTRAP delivery */
ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD) ?
0x80 : 0));
/*
* this isn't the same as continuing with a signal, but it will do
* for normal use. strace only continues with a signal if the
* stopping signal is not SIGTRAP. -brl
*/
if (current->exit_code) {
send_sig(current->exit_code, current, 1);
current->exit_code = 0;
}
if (test_thread_flag(TIF_SYSCALL_TRACE))
tracehook_report_syscall_exit(regs, 0);
user_enter();
}

846
arch/mips/kernel/scall32-o32.S
View File

@ -40,17 +40,58 @@ NESTED(handle_sys, PT_SIZE, sp)
sw t1, PT_EPC(sp)
beqz t0, illegal_syscall
sll t0, v0, 3
sll t0, v0, 2
la t1, sys_call_table
addu t1, t0
lw t2, (t1) # syscall routine
lw t3, 4(t1) # >= 0 if we need stack arguments
beqz t2, illegal_syscall
sw a3, PT_R26(sp) # save a3 for syscall restarting
bgez t3, stackargs
stack_done:
/*
* More than four arguments. Try to deal with it by copying the
* stack arguments from the user stack to the kernel stack.
* This Sucks (TM).
*/
lw t0, PT_R29(sp) # get old user stack pointer
/*
* We intentionally keep the kernel stack a little below the top of
* userspace so we don't have to do a slower byte accurate check here.
*/
lw t5, TI_ADDR_LIMIT($28)
addu t4, t0, 32
and t5, t4
bltz t5, bad_stack # -> sp is bad
/*
* Ok, copy the args from the luser stack to the kernel stack.
* t3 is the precomputed number of instruction bytes needed to
* load or store arguments 6-8.
*/
.set push
.set noreorder
.set nomacro
1: lw t5, 16(t0) # argument #5 from usp
4: lw t6, 20(t0) # argument #6 from usp
3: lw t7, 24(t0) # argument #7 from usp
2: lw t8, 28(t0) # argument #8 from usp
sw t5, 16(sp) # argument #5 to ksp
sw t6, 20(sp) # argument #6 to ksp
sw t7, 24(sp) # argument #7 to ksp
sw t8, 28(sp) # argument #8 to ksp
.set pop
.section __ex_table,"a"
PTR 1b,bad_stack
PTR 2b,bad_stack
PTR 3b,bad_stack
PTR 4b,bad_stack
.previous
lw t0, TI_FLAGS($28) # syscall tracing enabled?
li t1, _TIF_WORK_SYSCALL_ENTRY
and t0, t1
@ -101,66 +142,6 @@ syscall_trace_entry:
/* ------------------------------------------------------------------------ */
/*
* More than four arguments. Try to deal with it by copying the
* stack arguments from the user stack to the kernel stack.
* This Sucks (TM).
*/
stackargs:
lw t0, PT_R29(sp) # get old user stack pointer
/*
* We intentionally keep the kernel stack a little below the top of
* userspace so we don't have to do a slower byte accurate check here.
*/
lw t5, TI_ADDR_LIMIT($28)
addu t4, t0, 32
and t5, t4
bltz t5, bad_stack # -> sp is bad
/* Ok, copy the args from the luser stack to the kernel stack.
* t3 is the precomputed number of instruction bytes needed to
* load or store arguments 6-8.
*/
la t1, 5f # load up to 3 arguments
subu t1, t3
1: lw t5, 16(t0) # argument #5 from usp
.set push
.set noreorder
.set nomacro
jr t1
addiu t1, 6f - 5f
2: lw t8, 28(t0) # argument #8 from usp
3: lw t7, 24(t0) # argument #7 from usp
4: lw t6, 20(t0) # argument #6 from usp
5: jr t1
sw t5, 16(sp) # argument #5 to ksp
#ifdef CONFIG_CPU_MICROMIPS
sw t8, 28(sp) # argument #8 to ksp
nop
sw t7, 24(sp) # argument #7 to ksp
nop
sw t6, 20(sp) # argument #6 to ksp
nop
#else
sw t8, 28(sp) # argument #8 to ksp
sw t7, 24(sp) # argument #7 to ksp
sw t6, 20(sp) # argument #6 to ksp
#endif
6: j stack_done # go back
nop
.set pop
.section __ex_table,"a"
PTR 1b,bad_stack
PTR 2b,bad_stack
PTR 3b,bad_stack
PTR 4b,bad_stack
.previous
/*
* The stackpointer for a call with more than 4 arguments is bad.
* We probably should handle this case a bit more drastic.
@ -187,7 +168,7 @@ illegal_syscall:
subu t0, a0, __NR_O32_Linux # check syscall number
sltiu v0, t0, __NR_O32_Linux_syscalls + 1
beqz t0, einval # do not recurse
sll t1, t0, 3
sll t1, t0, 2
beqz v0, einval
lw t2, sys_call_table(t1) # syscall routine
@ -218,260 +199,248 @@ einval: li v0, -ENOSYS
jr ra
END(sys_syscall)
.macro fifty ptr, nargs, from=1, to=50
sys \ptr \nargs
.if \to-\from
fifty \ptr,\nargs,"(\from+1)",\to
.endif
.endm
.macro mille ptr, nargs, from=1, to=20
fifty \ptr,\nargs
.if \to-\from
mille \ptr,\nargs,"(\from+1)",\to
.endif
.endm
.macro syscalltable
sys sys_syscall 8 /* 4000 */
sys sys_exit 1
sys __sys_fork 0
sys sys_read 3
sys sys_write 3
sys sys_open 3 /* 4005 */
sys sys_close 1
sys sys_waitpid 3
sys sys_creat 2
sys sys_link 2
sys sys_unlink 1 /* 4010 */
sys sys_execve 0
sys sys_chdir 1
sys sys_time 1
sys sys_mknod 3
sys sys_chmod 2 /* 4015 */
sys sys_lchown 3
sys sys_ni_syscall 0
sys sys_ni_syscall 0 /* was sys_stat */
sys sys_lseek 3
sys sys_getpid 0 /* 4020 */
sys sys_mount 5
sys sys_oldumount 1
sys sys_setuid 1
sys sys_getuid 0
sys sys_stime 1 /* 4025 */
sys sys_ptrace 4
sys sys_alarm 1
sys sys_ni_syscall 0 /* was sys_fstat */
sys sys_pause 0
sys sys_utime 2 /* 4030 */
sys sys_ni_syscall 0
sys sys_ni_syscall 0
sys sys_access 2
sys sys_nice 1
sys sys_ni_syscall 0 /* 4035 */
sys sys_sync 0
sys sys_kill 2
sys sys_rename 2
sys sys_mkdir 2
sys sys_rmdir 1 /* 4040 */
sys sys_dup 1
sys sysm_pipe 0
sys sys_times 1
sys sys_ni_syscall 0
sys sys_brk 1 /* 4045 */
sys sys_setgid 1
sys sys_getgid 0
sys sys_ni_syscall 0 /* was signal(2) */
sys sys_geteuid 0
sys sys_getegid 0 /* 4050 */
sys sys_acct 1
sys sys_umount 2
sys sys_ni_syscall 0
sys sys_ioctl 3
sys sys_fcntl 3 /* 4055 */
sys sys_ni_syscall 2
sys sys_setpgid 2
sys sys_ni_syscall 0
sys sys_olduname 1
sys sys_umask 1 /* 4060 */
sys sys_chroot 1
sys sys_ustat 2
sys sys_dup2 2
sys sys_getppid 0
sys sys_getpgrp 0 /* 4065 */
sys sys_setsid 0
sys sys_sigaction 3
sys sys_sgetmask 0
sys sys_ssetmask 1
sys sys_setreuid 2 /* 4070 */
sys sys_setregid 2
sys sys_sigsuspend 0
sys sys_sigpending 1
sys sys_sethostname 2
sys sys_setrlimit 2 /* 4075 */
sys sys_getrlimit 2
sys sys_getrusage 2
sys sys_gettimeofday 2
sys sys_settimeofday 2
sys sys_getgroups 2 /* 4080 */
sys sys_setgroups 2
sys sys_ni_syscall 0 /* old_select */
sys sys_symlink 2
sys sys_ni_syscall 0 /* was sys_lstat */
sys sys_readlink 3 /* 4085 */
sys sys_uselib 1
sys sys_swapon 2
sys sys_reboot 3
sys sys_old_readdir 3
sys sys_mips_mmap 6 /* 4090 */
sys sys_munmap 2
sys sys_truncate 2
sys sys_ftruncate 2
sys sys_fchmod 2
sys sys_fchown 3 /* 4095 */
sys sys_getpriority 2
sys sys_setpriority 3
sys sys_ni_syscall 0
sys sys_statfs 2
sys sys_fstatfs 2 /* 4100 */
sys sys_ni_syscall 0 /* was ioperm(2) */
sys sys_socketcall 2
sys sys_syslog 3
sys sys_setitimer 3
sys sys_getitimer 2 /* 4105 */
sys sys_newstat 2
sys sys_newlstat 2
sys sys_newfstat 2
sys sys_uname 1
sys sys_ni_syscall 0 /* 4110 was iopl(2) */
sys sys_vhangup 0
sys sys_ni_syscall 0 /* was sys_idle() */
sys sys_ni_syscall 0 /* was sys_vm86 */
sys sys_wait4 4
sys sys_swapoff 1 /* 4115 */
sys sys_sysinfo 1
sys sys_ipc 6
sys sys_fsync 1
sys sys_sigreturn 0
sys __sys_clone 6 /* 4120 */
sys sys_setdomainname 2
sys sys_newuname 1
sys sys_ni_syscall 0 /* sys_modify_ldt */
sys sys_adjtimex 1
sys sys_mprotect 3 /* 4125 */
sys sys_sigprocmask 3
sys sys_ni_syscall 0 /* was create_module */
sys sys_init_module 5
sys sys_delete_module 1
sys sys_ni_syscall 0 /* 4130 was get_kernel_syms */
sys sys_quotactl 4
sys sys_getpgid 1
sys sys_fchdir 1
sys sys_bdflush 2
sys sys_sysfs 3 /* 4135 */
sys sys_personality 1
sys sys_ni_syscall 0 /* for afs_syscall */
sys sys_setfsuid 1
sys sys_setfsgid 1
sys sys_llseek 5 /* 4140 */
sys sys_getdents 3
sys sys_select 5
sys sys_flock 2
sys sys_msync 3
sys sys_readv 3 /* 4145 */
sys sys_writev 3
sys sys_cacheflush 3
sys sys_cachectl 3
sys sys_sysmips 4
sys sys_ni_syscall 0 /* 4150 */
sys sys_getsid 1
sys sys_fdatasync 1
sys sys_sysctl 1
sys sys_mlock 2
sys sys_munlock 2 /* 4155 */
sys sys_mlockall 1
sys sys_munlockall 0
sys sys_sched_setparam 2
sys sys_sched_getparam 2
sys sys_sched_setscheduler 3 /* 4160 */
sys sys_sched_getscheduler 1
sys sys_sched_yield 0
sys sys_sched_get_priority_max 1
sys sys_sched_get_priority_min 1
sys sys_sched_rr_get_interval 2 /* 4165 */
sys sys_nanosleep, 2
sys sys_mremap, 5
sys sys_accept 3
sys sys_bind 3
sys sys_connect 3 /* 4170 */
sys sys_getpeername 3
sys sys_getsockname 3
sys sys_getsockopt 5
sys sys_listen 2
sys sys_recv 4 /* 4175 */
sys sys_recvfrom 6
sys sys_recvmsg 3
sys sys_send 4
sys sys_sendmsg 3
sys sys_sendto 6 /* 4180 */
sys sys_setsockopt 5
sys sys_shutdown 2
sys sys_socket 3
sys sys_socketpair 4
sys sys_setresuid 3 /* 4185 */
sys sys_getresuid 3
sys sys_ni_syscall 0 /* was sys_query_module */
sys sys_poll 3
sys sys_ni_syscall 0 /* was nfsservctl */
sys sys_setresgid 3 /* 4190 */
sys sys_getresgid 3
sys sys_prctl 5
sys sys_rt_sigreturn 0
sys sys_rt_sigaction 4
sys sys_rt_sigprocmask 4 /* 4195 */
sys sys_rt_sigpending 2
sys sys_rt_sigtimedwait 4
sys sys_rt_sigqueueinfo 3
sys sys_rt_sigsuspend 0
sys sys_pread64 6 /* 4200 */
sys sys_pwrite64 6
sys sys_chown 3
sys sys_getcwd 2
sys sys_capget 2
sys sys_capset 2 /* 4205 */
sys sys_sigaltstack 0
sys sys_sendfile 4
sys sys_ni_syscall 0
sys sys_ni_syscall 0
sys sys_mips_mmap2 6 /* 4210 */
sys sys_truncate64 4
sys sys_ftruncate64 4
sys sys_stat64 2
sys sys_lstat64 2
sys sys_fstat64 2 /* 4215 */
sys sys_pivot_root 2
sys sys_mincore 3
sys sys_madvise 3
sys sys_getdents64 3
sys sys_fcntl64 3 /* 4220 */
sys sys_ni_syscall 0
sys sys_gettid 0
sys sys_readahead 5
sys sys_setxattr 5
sys sys_lsetxattr 5 /* 4225 */
sys sys_fsetxattr 5
sys sys_getxattr 4
sys sys_lgetxattr 4
sys sys_fgetxattr 4
sys sys_listxattr 3 /* 4230 */
sys sys_llistxattr 3
sys sys_flistxattr 3
sys sys_removexattr 2
sys sys_lremovexattr 2
sys sys_fremovexattr 2 /* 4235 */
sys sys_tkill 2
sys sys_sendfile64 5
sys sys_futex 6
.align 2
.type sys_call_table, @object
EXPORT(sys_call_table)
PTR sys_syscall /* 4000 */
PTR sys_exit
PTR __sys_fork
PTR sys_read
PTR sys_write
PTR sys_open /* 4005 */
PTR sys_close
PTR sys_waitpid
PTR sys_creat
PTR sys_link
PTR sys_unlink /* 4010 */
PTR sys_execve
PTR sys_chdir
PTR sys_time
PTR sys_mknod
PTR sys_chmod /* 4015 */
PTR sys_lchown
PTR sys_ni_syscall
PTR sys_ni_syscall /* was sys_stat */
PTR sys_lseek
PTR sys_getpid /* 4020 */
PTR sys_mount
PTR sys_oldumount
PTR sys_setuid
PTR sys_getuid
PTR sys_stime /* 4025 */
PTR sys_ptrace
PTR sys_alarm
PTR sys_ni_syscall /* was sys_fstat */
PTR sys_pause
PTR sys_utime /* 4030 */
PTR sys_ni_syscall
PTR sys_ni_syscall
PTR sys_access
PTR sys_nice
PTR sys_ni_syscall /* 4035 */
PTR sys_sync
PTR sys_kill
PTR sys_rename
PTR sys_mkdir
PTR sys_rmdir /* 4040 */
PTR sys_dup
PTR sysm_pipe
PTR sys_times
PTR sys_ni_syscall
PTR sys_brk /* 4045 */
PTR sys_setgid
PTR sys_getgid
PTR sys_ni_syscall /* was signal(2) */
PTR sys_geteuid
PTR sys_getegid /* 4050 */
PTR sys_acct
PTR sys_umount
PTR sys_ni_syscall
PTR sys_ioctl
PTR sys_fcntl /* 4055 */
PTR sys_ni_syscall
PTR sys_setpgid
PTR sys_ni_syscall
PTR sys_olduname
PTR sys_umask /* 4060 */
PTR sys_chroot
PTR sys_ustat
PTR sys_dup2
PTR sys_getppid
PTR sys_getpgrp /* 4065 */
PTR sys_setsid
PTR sys_sigaction
PTR sys_sgetmask
PTR sys_ssetmask
PTR sys_setreuid /* 4070 */
PTR sys_setregid
PTR sys_sigsuspend
PTR sys_sigpending
PTR sys_sethostname
PTR sys_setrlimit /* 4075 */
PTR sys_getrlimit
PTR sys_getrusage
PTR sys_gettimeofday
PTR sys_settimeofday
PTR sys_getgroups /* 4080 */
PTR sys_setgroups
PTR sys_ni_syscall /* old_select */
PTR sys_symlink
PTR sys_ni_syscall /* was sys_lstat */
PTR sys_readlink /* 4085 */
PTR sys_uselib
PTR sys_swapon
PTR sys_reboot
PTR sys_old_readdir
PTR sys_mips_mmap /* 4090 */
PTR sys_munmap
PTR sys_truncate
PTR sys_ftruncate
PTR sys_fchmod
PTR sys_fchown /* 4095 */
PTR sys_getpriority
PTR sys_setpriority
PTR sys_ni_syscall
PTR sys_statfs
PTR sys_fstatfs /* 4100 */
PTR sys_ni_syscall /* was ioperm(2) */
PTR sys_socketcall
PTR sys_syslog
PTR sys_setitimer
PTR sys_getitimer /* 4105 */
PTR sys_newstat
PTR sys_newlstat
PTR sys_newfstat
PTR sys_uname
PTR sys_ni_syscall /* 4110 was iopl(2) */
PTR sys_vhangup
PTR sys_ni_syscall /* was sys_idle() */
PTR sys_ni_syscall /* was sys_vm86 */
PTR sys_wait4
PTR sys_swapoff /* 4115 */
PTR sys_sysinfo
PTR sys_ipc
PTR sys_fsync
PTR sys_sigreturn
PTR __sys_clone /* 4120 */
PTR sys_setdomainname
PTR sys_newuname
PTR sys_ni_syscall /* sys_modify_ldt */
PTR sys_adjtimex
PTR sys_mprotect /* 4125 */
PTR sys_sigprocmask
PTR sys_ni_syscall /* was create_module */
PTR sys_init_module
PTR sys_delete_module
PTR sys_ni_syscall /* 4130 was get_kernel_syms */
PTR sys_quotactl
PTR sys_getpgid
PTR sys_fchdir
PTR sys_bdflush
PTR sys_sysfs /* 4135 */
PTR sys_personality
PTR sys_ni_syscall /* for afs_syscall */
PTR sys_setfsuid
PTR sys_setfsgid
PTR sys_llseek /* 4140 */
PTR sys_getdents
PTR sys_select
PTR sys_flock
PTR sys_msync
PTR sys_readv /* 4145 */
PTR sys_writev
PTR sys_cacheflush
PTR sys_cachectl
PTR sys_sysmips
PTR sys_ni_syscall /* 4150 */
PTR sys_getsid
PTR sys_fdatasync
PTR sys_sysctl
PTR sys_mlock
PTR sys_munlock /* 4155 */
PTR sys_mlockall
PTR sys_munlockall
PTR sys_sched_setparam
PTR sys_sched_getparam
PTR sys_sched_setscheduler /* 4160 */
PTR sys_sched_getscheduler
PTR sys_sched_yield
PTR sys_sched_get_priority_max
PTR sys_sched_get_priority_min
PTR sys_sched_rr_get_interval /* 4165 */
PTR sys_nanosleep
PTR sys_mremap
PTR sys_accept
PTR sys_bind
PTR sys_connect /* 4170 */
PTR sys_getpeername
PTR sys_getsockname
PTR sys_getsockopt
PTR sys_listen
PTR sys_recv /* 4175 */
PTR sys_recvfrom
PTR sys_recvmsg
PTR sys_send
PTR sys_sendmsg
PTR sys_sendto /* 4180 */
PTR sys_setsockopt
PTR sys_shutdown
PTR sys_socket
PTR sys_socketpair
PTR sys_setresuid /* 4185 */
PTR sys_getresuid
PTR sys_ni_syscall /* was sys_query_module */
PTR sys_poll
PTR sys_ni_syscall /* was nfsservctl */
PTR sys_setresgid /* 4190 */
PTR sys_getresgid
PTR sys_prctl
PTR sys_rt_sigreturn
PTR sys_rt_sigaction
PTR sys_rt_sigprocmask /* 4195 */
PTR sys_rt_sigpending
PTR sys_rt_sigtimedwait
PTR sys_rt_sigqueueinfo
PTR sys_rt_sigsuspend
PTR sys_pread64 /* 4200 */
PTR sys_pwrite64
PTR sys_chown
PTR sys_getcwd
PTR sys_capget
PTR sys_capset /* 4205 */
PTR sys_sigaltstack
PTR sys_sendfile
PTR sys_ni_syscall
PTR sys_ni_syscall
PTR sys_mips_mmap2 /* 4210 */
PTR sys_truncate64
PTR sys_ftruncate64
PTR sys_stat64
PTR sys_lstat64
PTR sys_fstat64 /* 4215 */
PTR sys_pivot_root
PTR sys_mincore
PTR sys_madvise
PTR sys_getdents64
PTR sys_fcntl64 /* 4220 */
PTR sys_ni_syscall
PTR sys_gettid
PTR sys_readahead
PTR sys_setxattr
PTR sys_lsetxattr /* 4225 */
PTR sys_fsetxattr
PTR sys_getxattr
PTR sys_lgetxattr
PTR sys_fgetxattr
PTR sys_listxattr /* 4230 */
PTR sys_llistxattr
PTR sys_flistxattr
PTR sys_removexattr
PTR sys_lremovexattr
PTR sys_fremovexattr /* 4235 */
PTR sys_tkill
PTR sys_sendfile64
PTR sys_futex
#ifdef CONFIG_MIPS_MT_FPAFF
/*
* For FPU affinity scheduling on MIPS MT processors, we need to
@ -480,132 +449,117 @@ einval: li v0, -ENOSYS
* these hooks for the 32-bit kernel - there is no MIPS64 MT processor
* atm.
*/
sys mipsmt_sys_sched_setaffinity 3
sys mipsmt_sys_sched_getaffinity 3
PTR mipsmt_sys_sched_setaffinity
PTR mipsmt_sys_sched_getaffinity
#else
sys sys_sched_setaffinity 3
sys sys_sched_getaffinity 3 /* 4240 */
PTR sys_sched_setaffinity
PTR sys_sched_getaffinity /* 4240 */
#endif /* CONFIG_MIPS_MT_FPAFF */
sys sys_io_setup 2
sys sys_io_destroy 1
sys sys_io_getevents 5
sys sys_io_submit 3
sys sys_io_cancel 3 /* 4245 */
sys sys_exit_group 1
sys sys_lookup_dcookie 4
sys sys_epoll_create 1
sys sys_epoll_ctl 4
sys sys_epoll_wait 4 /* 4250 */
sys sys_remap_file_pages 5
sys sys_set_tid_address 1
sys sys_restart_syscall 0
sys sys_fadvise64_64 7
sys sys_statfs64 3 /* 4255 */
sys sys_fstatfs64 2
sys sys_timer_create 3
sys sys_timer_settime 4
sys sys_timer_gettime 2
sys sys_timer_getoverrun 1 /* 4260 */
sys sys_timer_delete 1
sys sys_clock_settime 2
sys sys_clock_gettime 2
sys sys_clock_getres 2
sys sys_clock_nanosleep 4 /* 4265 */
sys sys_tgkill 3
sys sys_utimes 2
sys sys_mbind 4
sys sys_ni_syscall 0 /* sys_get_mempolicy */
sys sys_ni_syscall 0 /* 4270 sys_set_mempolicy */
sys sys_mq_open 4
sys sys_mq_unlink 1
sys sys_mq_timedsend 5
sys sys_mq_timedreceive 5
sys sys_mq_notify 2 /* 4275 */
sys sys_mq_getsetattr 3
sys sys_ni_syscall 0 /* sys_vserver */
sys sys_waitid 5
sys sys_ni_syscall 0 /* available, was setaltroot */
sys sys_add_key 5 /* 4280 */
sys sys_request_key 4
sys sys_keyctl 5
sys sys_set_thread_area 1
sys sys_inotify_init 0
sys sys_inotify_add_watch 3 /* 4285 */
sys sys_inotify_rm_watch 2
sys sys_migrate_pages 4
sys sys_openat 4
sys sys_mkdirat 3
sys sys_mknodat 4 /* 4290 */
sys sys_fchownat 5
sys sys_futimesat 3
sys sys_fstatat64 4
sys sys_unlinkat 3
sys sys_renameat 4 /* 4295 */
sys sys_linkat 5
sys sys_symlinkat 3
sys sys_readlinkat 4
sys sys_fchmodat 3
sys sys_faccessat 3 /* 4300 */
sys sys_pselect6 6
sys sys_ppoll 5
sys sys_unshare 1
sys sys_splice 6
sys sys_sync_file_range 7 /* 4305 */
sys sys_tee 4
sys sys_vmsplice 4
sys sys_move_pages 6
sys sys_set_robust_list 2
sys sys_get_robust_list 3 /* 4310 */
sys sys_kexec_load 4
sys sys_getcpu 3
sys sys_epoll_pwait 6
sys sys_ioprio_set 3
sys sys_ioprio_get 2 /* 4315 */
sys sys_utimensat 4
sys sys_signalfd 3
sys sys_ni_syscall 0 /* was timerfd */
sys sys_eventfd 1
sys sys_fallocate 6 /* 4320 */
sys sys_timerfd_create 2
sys sys_timerfd_gettime 2
sys sys_timerfd_settime 4
sys sys_signalfd4 4
sys sys_eventfd2 2 /* 4325 */
sys sys_epoll_create1 1
sys sys_dup3 3
sys sys_pipe2 2
sys sys_inotify_init1 1
sys sys_preadv 6 /* 4330 */
sys sys_pwritev 6
sys sys_rt_tgsigqueueinfo 4
sys sys_perf_event_open 5
sys sys_accept4 4
sys sys_recvmmsg 5 /* 4335 */
sys sys_fanotify_init 2
sys sys_fanotify_mark 6
sys sys_prlimit64 4
sys sys_name_to_handle_at 5
sys sys_open_by_handle_at 3 /* 4340 */
sys sys_clock_adjtime 2
sys sys_syncfs 1
sys sys_sendmmsg 4
sys sys_setns 2
sys sys_process_vm_readv 6 /* 4345 */
sys sys_process_vm_writev 6
sys sys_kcmp 5
sys sys_finit_module 3
.endm
/* We pre-compute the number of _instruction_ bytes needed to
load or store the arguments 6-8. Negative values are ignored. */
.macro sys function, nargs
PTR \function
LONG (\nargs << 2) - (5 << 2)
.endm
.align 3
.type sys_call_table,@object
EXPORT(sys_call_table)
syscalltable
.size sys_call_table, . - sys_call_table
PTR sys_io_setup
PTR sys_io_destroy
PTR sys_io_getevents
PTR sys_io_submit
PTR sys_io_cancel /* 4245 */
PTR sys_exit_group
PTR sys_lookup_dcookie
PTR sys_epoll_create
PTR sys_epoll_ctl
PTR sys_epoll_wait /* 4250 */
PTR sys_remap_file_pages
PTR sys_set_tid_address
PTR sys_restart_syscall
PTR sys_fadvise64_64
PTR sys_statfs64 /* 4255 */
PTR sys_fstatfs64
PTR sys_timer_create
PTR sys_timer_settime
PTR sys_timer_gettime
PTR sys_timer_getoverrun /* 4260 */
PTR sys_timer_delete
PTR sys_clock_settime
PTR sys_clock_gettime
PTR sys_clock_getres
PTR sys_clock_nanosleep /* 4265 */
PTR sys_tgkill
PTR sys_utimes
PTR sys_mbind
PTR sys_ni_syscall /* sys_get_mempolicy */
PTR sys_ni_syscall /* 4270 sys_set_mempolicy */
PTR sys_mq_open
PTR sys_mq_unlink
PTR sys_mq_timedsend
PTR sys_mq_timedreceive
PTR sys_mq_notify /* 4275 */
PTR sys_mq_getsetattr
PTR sys_ni_syscall /* sys_vserver */
PTR sys_waitid
PTR sys_ni_syscall /* available, was setaltroot */
PTR sys_add_key /* 4280 */
PTR sys_request_key
PTR sys_keyctl
PTR sys_set_thread_area
PTR sys_inotify_init
PTR sys_inotify_add_watch /* 4285 */
PTR sys_inotify_rm_watch
PTR sys_migrate_pages
PTR sys_openat
PTR sys_mkdirat
PTR sys_mknodat /* 4290 */
PTR sys_fchownat
PTR sys_futimesat
PTR sys_fstatat64
PTR sys_unlinkat
PTR sys_renameat /* 4295 */
PTR sys_linkat
PTR sys_symlinkat
PTR sys_readlinkat
PTR sys_fchmodat
PTR sys_faccessat /* 4300 */
PTR sys_pselect6
PTR sys_ppoll
PTR sys_unshare
PTR sys_splice
PTR sys_sync_file_range /* 4305 */
PTR sys_tee
PTR sys_vmsplice
PTR sys_move_pages
PTR sys_set_robust_list
PTR sys_get_robust_list /* 4310 */
PTR sys_kexec_load
PTR sys_getcpu
PTR sys_epoll_pwait
PTR sys_ioprio_set
PTR sys_ioprio_get /* 4315 */
PTR sys_utimensat
PTR sys_signalfd
PTR sys_ni_syscall /* was timerfd */
PTR sys_eventfd
PTR sys_fallocate /* 4320 */
PTR sys_timerfd_create
PTR sys_timerfd_gettime
PTR sys_timerfd_settime
PTR sys_signalfd4
PTR sys_eventfd2 /* 4325 */
PTR sys_epoll_create1
PTR sys_dup3
PTR sys_pipe2
PTR sys_inotify_init1
PTR sys_preadv /* 4330 */
PTR sys_pwritev
PTR sys_rt_tgsigqueueinfo
PTR sys_perf_event_open
PTR sys_accept4
PTR sys_recvmmsg /* 4335 */
PTR sys_fanotify_init
PTR sys_fanotify_mark
PTR sys_prlimit64
PTR sys_name_to_handle_at
PTR sys_open_by_handle_at /* 4340 */
PTR sys_clock_adjtime
PTR sys_syncfs
PTR sys_sendmmsg
PTR sys_setns
PTR sys_process_vm_readv /* 4345 */
PTR sys_process_vm_writev
PTR sys_kcmp
PTR sys_finit_module

3
arch/mips/kernel/scall64-64.S
View File

@ -114,7 +114,8 @@ illegal_syscall:
END(handle_sys64)
.align 3
sys_call_table:
.type sys_call_table, @object
EXPORT(sys_call_table)
PTR sys_read /* 5000 */
PTR sys_write
PTR sys_open

1
arch/mips/kernel/scall64-n32.S
View File

@ -103,6 +103,7 @@ not_n32_scall:
END(handle_sysn32)
.type sysn32_call_table, @object
EXPORT(sysn32_call_table)
PTR sys_read /* 6000 */
PTR sys_write

10
arch/mips/kernel/scall64-o32.S
View File

@ -53,7 +53,7 @@ NESTED(handle_sys, PT_SIZE, sp)
sll a3, a3, 0
dsll t0, v0, 3 # offset into table
ld t2, (sys_call_table - (__NR_O32_Linux * 8))(t0)
ld t2, (sys32_call_table - (__NR_O32_Linux * 8))(t0)
sd a3, PT_R26(sp) # save a3 for syscall restarting
@ -168,7 +168,7 @@ LEAF(sys32_syscall)
beqz t0, einval # do not recurse
dsll t1, t0, 3
beqz v0, einval
ld t2, sys_call_table(t1) # syscall routine
ld t2, sys32_call_table(t1) # syscall routine
move a0, a1 # shift argument registers
move a1, a2
@ -190,8 +190,8 @@ einval: li v0, -ENOSYS
END(sys32_syscall)
.align 3
.type sys_call_table,@object
sys_call_table:
.type sys32_call_table,@object
EXPORT(sys32_call_table)
PTR sys32_syscall /* 4000 */
PTR sys_exit
PTR __sys_fork
@ -541,4 +541,4 @@ sys_call_table:
PTR compat_sys_process_vm_writev
PTR sys_kcmp
PTR sys_finit_module
.size sys_call_table,.-sys_call_table
.size sys32_call_table,.-sys32_call_table

19
arch/mips/kernel/setup.c
View File

@ -300,12 +300,13 @@ static void __init bootmem_init(void)
int i;
/*
* Init any data related to initrd. It's a nop if INITRD is
* not selected. Once that done we can determine the low bound
* of usable memory.
* Sanity check any INITRD first. We don't take it into account
* for bootmem setup initially, rely on the end-of-kernel-code
* as our memory range starting point. Once bootmem is inited we
* will reserve the area used for the initrd.
*/
reserved_end = max(init_initrd(),
(unsigned long) PFN_UP(__pa_symbol(&_end)));
init_initrd();
reserved_end = (unsigned long) PFN_UP(__pa_symbol(&_end));
/*
* max_low_pfn is not a number of pages. The number of pages
@ -362,6 +363,14 @@ static void __init bootmem_init(void)
max_low_pfn = PFN_DOWN(HIGHMEM_START);
}
#ifdef CONFIG_BLK_DEV_INITRD
/*
* mapstart should be after initrd_end
*/
if (initrd_end)
mapstart = max(mapstart, (unsigned long)PFN_UP(__pa(initrd_end)));
#endif
/*
* Initialize the boot-time allocator with low memory only.
*/

4
arch/mips/kernel/smp-bmips.c
View File

@ -136,10 +136,10 @@ static void bmips_prepare_cpus(unsigned int max_cpus)
{
if (request_irq(IPI0_IRQ, bmips_ipi_interrupt, IRQF_PERCPU,
"smp_ipi0", NULL))
panic("Can't request IPI0 interrupt\n");
panic("Can't request IPI0 interrupt");
if (request_irq(IPI1_IRQ, bmips_ipi_interrupt, IRQF_PERCPU,
"smp_ipi1", NULL))
panic("Can't request IPI1 interrupt\n");
panic("Can't request IPI1 interrupt");
}
/*

1
arch/mips/kernel/smp.c
View File

@ -150,7 +150,6 @@ asmlinkage void start_secondary(void)
void __irq_entry smp_call_function_interrupt(void)
{
irq_enter();
generic_smp_call_function_single_interrupt();
generic_smp_call_function_interrupt();
irq_exit();
}

38
arch/mips/kernel/traps.c
View File

@ -330,6 +330,7 @@ void show_regs(struct pt_regs *regs)
void show_registers(struct pt_regs *regs)
{
const int field = 2 * sizeof(unsigned long);
mm_segment_t old_fs = get_fs();
__show_regs(regs);
print_modules();
@ -344,9 +345,13 @@ void show_registers(struct pt_regs *regs)
printk("*HwTLS: %0*lx\n", field, tls);
}
if (!user_mode(regs))
/* Necessary for getting the correct stack content */
set_fs(KERNEL_DS);
show_stacktrace(current, regs);
show_code((unsigned int __user *) regs->cp0_epc);
printk("\n");
set_fs(old_fs);
}
static int regs_to_trapnr(struct pt_regs *regs)
@ -366,7 +371,8 @@ void __noreturn die(const char *str, struct pt_regs *regs)
oops_enter();
if (notify_die(DIE_OOPS, str, regs, 0, regs_to_trapnr(regs), SIGSEGV) == NOTIFY_STOP)
if (notify_die(DIE_OOPS, str, regs, 0, regs_to_trapnr(regs),
SIGSEGV) == NOTIFY_STOP)
sig = 0;
console_verbose();
@ -457,8 +463,8 @@ asmlinkage void do_be(struct pt_regs *regs)
printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
data ? "Data" : "Instruction",
field, regs->cp0_epc, field, regs->regs[31]);
if (notify_die(DIE_OOPS, "bus error", regs, 0, regs_to_trapnr(regs), SIGBUS)
== NOTIFY_STOP)
if (notify_die(DIE_OOPS, "bus error", regs, 0, regs_to_trapnr(regs),
SIGBUS) == NOTIFY_STOP)
goto out;
die_if_kernel("Oops", regs);
@ -727,8 +733,8 @@ asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
siginfo_t info = {0};
prev_state = exception_enter();
if (notify_die(DIE_FP, "FP exception", regs, 0, regs_to_trapnr(regs), SIGFPE)
== NOTIFY_STOP)
if (notify_die(DIE_FP, "FP exception", regs, 0, regs_to_trapnr(regs),
SIGFPE) == NOTIFY_STOP)
goto out;
die_if_kernel("FP exception in kernel code", regs);
@ -798,7 +804,8 @@ static void do_trap_or_bp(struct pt_regs *regs, unsigned int code,
return;
#endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */
if (notify_die(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
if (notify_die(DIE_TRAP, str, regs, code, regs_to_trapnr(regs),
SIGTRAP) == NOTIFY_STOP)
return;
/*
@ -892,12 +899,14 @@ asmlinkage void do_bp(struct pt_regs *regs)
*/
switch (bcode) {
case BRK_KPROBE_BP:
if (notify_die(DIE_BREAK, "debug", regs, bcode, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
if (notify_die(DIE_BREAK, "debug", regs, bcode,
regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
goto out;
else
break;
case BRK_KPROBE_SSTEPBP:
if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode,
regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
goto out;
else
break;
@ -961,8 +970,8 @@ asmlinkage void do_ri(struct pt_regs *regs)
int status = -1;
prev_state = exception_enter();
if (notify_die(DIE_RI, "RI Fault", regs, 0, regs_to_trapnr(regs), SIGILL)
== NOTIFY_STOP)
if (notify_die(DIE_RI, "RI Fault", regs, 0, regs_to_trapnr(regs),
SIGILL) == NOTIFY_STOP)
goto out;
die_if_kernel("Reserved instruction in kernel code", regs);
@ -1488,10 +1497,14 @@ int register_nmi_notifier(struct notifier_block *nb)
void __noreturn nmi_exception_handler(struct pt_regs *regs)
{
char str[100];
raw_notifier_call_chain(&nmi_chain, 0, regs);
bust_spinlocks(1);
printk("NMI taken!!!!\n");
die("NMI", regs);
snprintf(str, 100, "CPU%d NMI taken, CP0_EPC=%lx\n",
smp_processor_id(), regs->cp0_epc);
regs->cp0_epc = read_c0_errorepc();
die(str, regs);
}
#define VECTORSPACING 0x100 /* for EI/VI mode */
@ -1554,7 +1567,6 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
unsigned char *b;
BUG_ON(!cpu_has_veic && !cpu_has_vint);
BUG_ON((n < 0) && (n > 9));
if (addr == NULL) {
handler = (unsigned long) do_default_vi;

2
arch/mips/lantiq/irq.c
View File

@ -390,7 +390,7 @@ int __init icu_of_init(struct device_node *node, struct device_node *parent)
ret = of_irq_to_resource_table(eiu_node,
ltq_eiu_irq, exin_avail);
if (ret != exin_avail)
panic("failed to load external irq resources\n");
panic("failed to load external irq resources");
if (request_mem_region(res.start, resource_size(&res),
res.name) < 0)

2
arch/mips/lantiq/xway/sysctrl.c
View File

@ -128,7 +128,7 @@ static int pmu_enable(struct clk *clk)
do {} while (--retry && (pmu_r32(PWDSR(clk->module)) & clk->bits));
if (!retry)
panic("activating PMU module failed!\n");
panic("activating PMU module failed!");
return 0;
}

52
arch/mips/mm/c-r4k.c
View File

@ -346,14 +346,8 @@ static void r4k_blast_scache_setup(void)
static inline void local_r4k___flush_cache_all(void * args)
{
#if defined(CONFIG_CPU_LOONGSON2)
r4k_blast_scache();
return;
#endif
r4k_blast_dcache();
r4k_blast_icache();
switch (current_cpu_type()) {
case CPU_LOONGSON2:
case CPU_R4000SC:
case CPU_R4000MC:
case CPU_R4400SC:
@ -361,7 +355,18 @@ static inline void local_r4k___flush_cache_all(void * args)
case CPU_R10000:
case CPU_R12000:
case CPU_R14000:
/*
* These caches are inclusive caches, that is, if something
* is not cached in the S-cache, we know it also won't be
* in one of the primary caches.
*/
r4k_blast_scache();
break;
default:
r4k_blast_dcache();
r4k_blast_icache();
break;
}
}
@ -572,8 +577,17 @@ static inline void local_r4k_flush_icache_range(unsigned long start, unsigned lo
if (end - start > icache_size)
r4k_blast_icache();
else
protected_blast_icache_range(start, end);
else {
switch (boot_cpu_type()) {
case CPU_LOONGSON2:
protected_blast_icache_range(start, end);
break;
default:
protected_loongson23_blast_icache_range(start, end);
break;
}
}
}
static inline void local_r4k_flush_icache_range_ipi(void *args)
@ -1109,15 +1123,14 @@ static void probe_pcache(void)
case CPU_ALCHEMY:
c->icache.flags |= MIPS_CACHE_IC_F_DC;
break;
}
#ifdef CONFIG_CPU_LOONGSON2
/*
* LOONGSON2 has 4 way icache, but when using indexed cache op,
* one op will act on all 4 ways
*/
c->icache.ways = 1;
#endif
case CPU_LOONGSON2:
/*
* LOONGSON2 has 4 way icache, but when using indexed cache op,
* one op will act on all 4 ways
*/
c->icache.ways = 1;
}
printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n",
icache_size >> 10,
@ -1193,7 +1206,6 @@ static int probe_scache(void)
return 1;
}
#if defined(CONFIG_CPU_LOONGSON2)
static void __init loongson2_sc_init(void)
{
struct cpuinfo_mips *c = &current_cpu_data;
@ -1209,7 +1221,6 @@ static void __init loongson2_sc_init(void)
c->options |= MIPS_CPU_INCLUSIVE_CACHES;
}
#endif
extern int r5k_sc_init(void);
extern int rm7k_sc_init(void);
@ -1259,11 +1270,10 @@ static void setup_scache(void)
#endif
return;
#if defined(CONFIG_CPU_LOONGSON2)
case CPU_LOONGSON2:
loongson2_sc_init();
return;
#endif
case CPU_XLP:
/* don't need to worry about L2, fully coherent */
return;

4
arch/mips/mm/dma-default.c
View File

@ -297,7 +297,6 @@ static void mips_dma_sync_single_for_cpu(struct device *dev,
static void mips_dma_sync_single_for_device(struct device *dev,
dma_addr_t dma_handle, size_t size, enum dma_data_direction direction)
{
plat_extra_sync_for_device(dev);
if (!plat_device_is_coherent(dev))
__dma_sync(dma_addr_to_page(dev, dma_handle),
dma_handle & ~PAGE_MASK, size, direction);
@ -327,7 +326,7 @@ static void mips_dma_sync_sg_for_device(struct device *dev,
int mips_dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
{
return plat_dma_mapping_error(dev, dma_addr);
return 0;
}
int mips_dma_supported(struct device *dev, u64 mask)
@ -340,7 +339,6 @@ void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
{
BUG_ON(direction == DMA_NONE);
plat_extra_sync_for_device(dev);
if (!plat_device_is_coherent(dev))
__dma_sync_virtual(vaddr, size, direction);
}

2
arch/mips/mm/tlb-funcs.S
View File

@ -16,12 +16,10 @@
#define FASTPATH_SIZE 128
#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
LEAF(tlbmiss_handler_setup_pgd)
.space 16 * 4
END(tlbmiss_handler_setup_pgd)
EXPORT(tlbmiss_handler_setup_pgd_end)
#endif
LEAF(handle_tlbm)
.space FASTPATH_SIZE * 4

37
arch/mips/mm/tlb-r4k.c
View File

@ -52,21 +52,26 @@ extern void build_tlb_refill_handler(void);
#endif /* CONFIG_MIPS_MT_SMTC */
#if defined(CONFIG_CPU_LOONGSON2)
/*
* LOONGSON2 has a 4 entry itlb which is a subset of dtlb,
* unfortrunately, itlb is not totally transparent to software.
*/
#define FLUSH_ITLB write_c0_diag(4);
static inline void flush_itlb(void)
{
switch (current_cpu_type()) {
case CPU_LOONGSON2:
write_c0_diag(4);
break;
default:
break;
}
}
#define FLUSH_ITLB_VM(vma) { if ((vma)->vm_flags & VM_EXEC) write_c0_diag(4); }
#else
#define FLUSH_ITLB
#define FLUSH_ITLB_VM(vma)
#endif
static inline void flush_itlb_vm(struct vm_area_struct *vma)
{
if (vma->vm_flags & VM_EXEC)
flush_itlb();
}
void local_flush_tlb_all(void)
{
@ -93,7 +98,7 @@ void local_flush_tlb_all(void)
}
tlbw_use_hazard();
write_c0_entryhi(old_ctx);
FLUSH_ITLB;
flush_itlb();
EXIT_CRITICAL(flags);
}
EXPORT_SYMBOL(local_flush_tlb_all);
@ -155,7 +160,7 @@ void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
} else {
drop_mmu_context(mm, cpu);
}
FLUSH_ITLB;
flush_itlb();
EXIT_CRITICAL(flags);
}
}
@ -197,7 +202,7 @@ void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
} else {
local_flush_tlb_all();
}
FLUSH_ITLB;
flush_itlb();
EXIT_CRITICAL(flags);
}
@ -230,7 +235,7 @@ void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
finish:
write_c0_entryhi(oldpid);
FLUSH_ITLB_VM(vma);
flush_itlb_vm(vma);
EXIT_CRITICAL(flags);
}
}
@ -262,7 +267,7 @@ void local_flush_tlb_one(unsigned long page)
tlbw_use_hazard();
}
write_c0_entryhi(oldpid);
FLUSH_ITLB;
flush_itlb();
EXIT_CRITICAL(flags);
}
@ -335,7 +340,7 @@ void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte)
tlb_write_indexed();
}
tlbw_use_hazard();
FLUSH_ITLB_VM(vma);
flush_itlb_vm(vma);
EXIT_CRITICAL(flags);
}

299
arch/mips/mm/tlbex.c
View File

@ -340,10 +340,6 @@ static struct work_registers build_get_work_registers(u32 **p)
{
struct work_registers r;
int smp_processor_id_reg;
int smp_processor_id_sel;
int smp_processor_id_shift;
if (scratch_reg >= 0) {
/* Save in CPU local C0_KScratch? */
UASM_i_MTC0(p, 1, c0_kscratch(), scratch_reg);
@ -354,25 +350,9 @@ static struct work_registers build_get_work_registers(u32 **p)
}
if (num_possible_cpus() > 1) {
#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
smp_processor_id_shift = 51;
smp_processor_id_reg = 20; /* XContext */
smp_processor_id_sel = 0;
#else
# ifdef CONFIG_32BIT
smp_processor_id_shift = 25;
smp_processor_id_reg = 4; /* Context */
smp_processor_id_sel = 0;
# endif
# ifdef CONFIG_64BIT
smp_processor_id_shift = 26;
smp_processor_id_reg = 4; /* Context */
smp_processor_id_sel = 0;
# endif
#endif
/* Get smp_processor_id */
UASM_i_MFC0(p, K0, smp_processor_id_reg, smp_processor_id_sel);
UASM_i_SRL_SAFE(p, K0, K0, smp_processor_id_shift);
UASM_i_CPUID_MFC0(p, K0, SMP_CPUID_REG);
UASM_i_SRL_SAFE(p, K0, K0, SMP_CPUID_REGSHIFT);
/* handler_reg_save index in K0 */
UASM_i_SLL(p, K0, K0, ilog2(sizeof(struct tlb_reg_save)));
@ -819,11 +799,11 @@ build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
}
/* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */
#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
if (pgd_reg != -1) {
/* pgd is in pgd_reg */
UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg);
} else {
#if defined(CONFIG_MIPS_PGD_C0_CONTEXT)
/*
* &pgd << 11 stored in CONTEXT [23..63].
*/
@ -835,30 +815,18 @@ build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
/* 1 0 1 0 1 << 6 xkphys cached */
uasm_i_ori(p, ptr, ptr, 0x540);
uasm_i_drotr(p, ptr, ptr, 11);
}
#elif defined(CONFIG_SMP)
# ifdef CONFIG_MIPS_MT_SMTC
/*
* SMTC uses TCBind value as "CPU" index
*/
uasm_i_mfc0(p, ptr, C0_TCBIND);
uasm_i_dsrl_safe(p, ptr, ptr, 19);
# else
/*
* 64 bit SMP running in XKPHYS has smp_processor_id() << 3
* stored in CONTEXT.
*/
uasm_i_dmfc0(p, ptr, C0_CONTEXT);
uasm_i_dsrl_safe(p, ptr, ptr, 23);
# endif
UASM_i_LA_mostly(p, tmp, pgdc);
uasm_i_daddu(p, ptr, ptr, tmp);
uasm_i_dmfc0(p, tmp, C0_BADVADDR);
uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr);
UASM_i_CPUID_MFC0(p, ptr, SMP_CPUID_REG);
uasm_i_dsrl_safe(p, ptr, ptr, SMP_CPUID_PTRSHIFT);
UASM_i_LA_mostly(p, tmp, pgdc);
uasm_i_daddu(p, ptr, ptr, tmp);
uasm_i_dmfc0(p, tmp, C0_BADVADDR);
uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr);
#else
UASM_i_LA_mostly(p, ptr, pgdc);
uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr);
UASM_i_LA_mostly(p, ptr, pgdc);
uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr);
#endif
}
uasm_l_vmalloc_done(l, *p);
@ -953,31 +921,25 @@ build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
static void __maybe_unused
build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr)
{
long pgdc = (long)pgd_current;
if (pgd_reg != -1) {
/* pgd is in pgd_reg */
uasm_i_mfc0(p, ptr, c0_kscratch(), pgd_reg);
uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
} else {
long pgdc = (long)pgd_current;
/* 32 bit SMP has smp_processor_id() stored in CONTEXT. */
/* 32 bit SMP has smp_processor_id() stored in CONTEXT. */
#ifdef CONFIG_SMP
#ifdef CONFIG_MIPS_MT_SMTC
/*
* SMTC uses TCBind value as "CPU" index
*/
uasm_i_mfc0(p, ptr, C0_TCBIND);
UASM_i_LA_mostly(p, tmp, pgdc);
uasm_i_srl(p, ptr, ptr, 19);
uasm_i_mfc0(p, ptr, SMP_CPUID_REG);
UASM_i_LA_mostly(p, tmp, pgdc);
uasm_i_srl(p, ptr, ptr, SMP_CPUID_PTRSHIFT);
uasm_i_addu(p, ptr, tmp, ptr);
#else
/*
* smp_processor_id() << 2 is stored in CONTEXT.
*/
uasm_i_mfc0(p, ptr, C0_CONTEXT);
UASM_i_LA_mostly(p, tmp, pgdc);
uasm_i_srl(p, ptr, ptr, 23);
UASM_i_LA_mostly(p, ptr, pgdc);
#endif
uasm_i_addu(p, ptr, tmp, ptr);
#else
UASM_i_LA_mostly(p, ptr, pgdc);
#endif
uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr);
uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr);
}
uasm_i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */
uasm_i_sll(p, tmp, tmp, PGD_T_LOG2);
uasm_i_addu(p, ptr, ptr, tmp); /* add in pgd offset */
@ -1349,95 +1311,100 @@ static void build_r4000_tlb_refill_handler(void)
* need three, with the second nop'ed and the third being
* unused.
*/
/* Loongson2 ebase is different than r4k, we have more space */
#if defined(CONFIG_32BIT) || defined(CONFIG_CPU_LOONGSON2)
if ((p - tlb_handler) > 64)
panic("TLB refill handler space exceeded");
#else
if (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 1)
|| (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 3)
&& uasm_insn_has_bdelay(relocs,
tlb_handler + MIPS64_REFILL_INSNS - 3)))
panic("TLB refill handler space exceeded");
#endif
/*
* Now fold the handler in the TLB refill handler space.
*/
#if defined(CONFIG_32BIT) || defined(CONFIG_CPU_LOONGSON2)
f = final_handler;
/* Simplest case, just copy the handler. */
uasm_copy_handler(relocs, labels, tlb_handler, p, f);
final_len = p - tlb_handler;
#else /* CONFIG_64BIT */
f = final_handler + MIPS64_REFILL_INSNS;
if ((p - tlb_handler) <= MIPS64_REFILL_INSNS) {
/* Just copy the handler. */
uasm_copy_handler(relocs, labels, tlb_handler, p, f);
final_len = p - tlb_handler;
} else {
switch (boot_cpu_type()) {
default:
if (sizeof(long) == 4) {
case CPU_LOONGSON2:
/* Loongson2 ebase is different than r4k, we have more space */
if ((p - tlb_handler) > 64)
panic("TLB refill handler space exceeded");
/*
* Now fold the handler in the TLB refill handler space.
*/
f = final_handler;
/* Simplest case, just copy the handler. */
uasm_copy_handler(relocs, labels, tlb_handler, p, f);
final_len = p - tlb_handler;
break;
} else {
if (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 1)
|| (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 3)
&& uasm_insn_has_bdelay(relocs,
tlb_handler + MIPS64_REFILL_INSNS - 3)))
panic("TLB refill handler space exceeded");
/*
* Now fold the handler in the TLB refill handler space.
*/
f = final_handler + MIPS64_REFILL_INSNS;
if ((p - tlb_handler) <= MIPS64_REFILL_INSNS) {
/* Just copy the handler. */
uasm_copy_handler(relocs, labels, tlb_handler, p, f);
final_len = p - tlb_handler;
} else {
#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
const enum label_id ls = label_tlb_huge_update;
const enum label_id ls = label_tlb_huge_update;
#else
const enum label_id ls = label_vmalloc;
const enum label_id ls = label_vmalloc;
#endif
u32 *split;
int ov = 0;
int i;
u32 *split;
int ov = 0;
int i;
for (i = 0; i < ARRAY_SIZE(labels) && labels[i].lab != ls; i++)
;
BUG_ON(i == ARRAY_SIZE(labels));
split = labels[i].addr;
for (i = 0; i < ARRAY_SIZE(labels) && labels[i].lab != ls; i++)
;
BUG_ON(i == ARRAY_SIZE(labels));
split = labels[i].addr;
/*
* See if we have overflown one way or the other.
*/
if (split > tlb_handler + MIPS64_REFILL_INSNS ||
split < p - MIPS64_REFILL_INSNS)
ov = 1;
/*
* See if we have overflown one way or the other.
*/
if (split > tlb_handler + MIPS64_REFILL_INSNS ||
split < p - MIPS64_REFILL_INSNS)
ov = 1;
if (ov) {
/*
* Split two instructions before the end. One
* for the branch and one for the instruction
* in the delay slot.
*/
split = tlb_handler + MIPS64_REFILL_INSNS - 2;
if (ov) {
/*
* Split two instructions before the end. One
* for the branch and one for the instruction
* in the delay slot.
*/
split = tlb_handler + MIPS64_REFILL_INSNS - 2;
/*
* If the branch would fall in a delay slot,
* we must back up an additional instruction
* so that it is no longer in a delay slot.
*/
if (uasm_insn_has_bdelay(relocs, split - 1))
split--;
}
/* Copy first part of the handler. */
uasm_copy_handler(relocs, labels, tlb_handler, split, f);
f += split - tlb_handler;
/*
* If the branch would fall in a delay slot,
* we must back up an additional instruction
* so that it is no longer in a delay slot.
*/
if (uasm_insn_has_bdelay(relocs, split - 1))
split--;
}
/* Copy first part of the handler. */
uasm_copy_handler(relocs, labels, tlb_handler, split, f);
f += split - tlb_handler;
if (ov) {
/* Insert branch. */
uasm_l_split(&l, final_handler);
uasm_il_b(&f, &r, label_split);
if (uasm_insn_has_bdelay(relocs, split))
uasm_i_nop(&f);
else {
uasm_copy_handler(relocs, labels,
split, split + 1, f);
uasm_move_labels(labels, f, f + 1, -1);
f++;
split++;
if (ov) {
/* Insert branch. */
uasm_l_split(&l, final_handler);
uasm_il_b(&f, &r, label_split);
if (uasm_insn_has_bdelay(relocs, split))
uasm_i_nop(&f);
else {
uasm_copy_handler(relocs, labels,
split, split + 1, f);
uasm_move_labels(labels, f, f + 1, -1);
f++;
split++;
}
}
/* Copy the rest of the handler. */
uasm_copy_handler(relocs, labels, split, p, final_handler);
final_len = (f - (final_handler + MIPS64_REFILL_INSNS)) +
(p - split);
}
}
/* Copy the rest of the handler. */
uasm_copy_handler(relocs, labels, split, p, final_handler);
final_len = (f - (final_handler + MIPS64_REFILL_INSNS)) +
(p - split);
break;
}
#endif /* CONFIG_64BIT */
uasm_resolve_relocs(relocs, labels);
pr_debug("Wrote TLB refill handler (%u instructions).\n",
@ -1451,28 +1418,30 @@ static void build_r4000_tlb_refill_handler(void)
extern u32 handle_tlbl[], handle_tlbl_end[];
extern u32 handle_tlbs[], handle_tlbs_end[];
extern u32 handle_tlbm[], handle_tlbm_end[];
#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
extern u32 tlbmiss_handler_setup_pgd[], tlbmiss_handler_setup_pgd_end[];
static void build_r4000_setup_pgd(void)
static void build_setup_pgd(void)
{
const int a0 = 4;
const int a1 = 5;
const int __maybe_unused a1 = 5;
const int __maybe_unused a2 = 6;
u32 *p = tlbmiss_handler_setup_pgd;
const int tlbmiss_handler_setup_pgd_size =
tlbmiss_handler_setup_pgd_end - tlbmiss_handler_setup_pgd;
struct uasm_label *l = labels;
struct uasm_reloc *r = relocs;
#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
long pgdc = (long)pgd_current;
#endif
memset(tlbmiss_handler_setup_pgd, 0, tlbmiss_handler_setup_pgd_size *
sizeof(tlbmiss_handler_setup_pgd[0]));
memset(labels, 0, sizeof(labels));
memset(relocs, 0, sizeof(relocs));
pgd_reg = allocate_kscratch();
#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
if (pgd_reg == -1) {
struct uasm_label *l = labels;
struct uasm_reloc *r = relocs;
/* PGD << 11 in c0_Context */
/*
* If it is a ckseg0 address, convert to a physical
@ -1494,6 +1463,26 @@ static void build_r4000_setup_pgd(void)
uasm_i_jr(&p, 31);
UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg);
}
#else
#ifdef CONFIG_SMP
/* Save PGD to pgd_current[smp_processor_id()] */
UASM_i_CPUID_MFC0(&p, a1, SMP_CPUID_REG);
UASM_i_SRL_SAFE(&p, a1, a1, SMP_CPUID_PTRSHIFT);
UASM_i_LA_mostly(&p, a2, pgdc);
UASM_i_ADDU(&p, a2, a2, a1);
UASM_i_SW(&p, a0, uasm_rel_lo(pgdc), a2);
#else
UASM_i_LA_mostly(&p, a2, pgdc);
UASM_i_SW(&p, a0, uasm_rel_lo(pgdc), a2);
#endif /* SMP */
uasm_i_jr(&p, 31);
/* if pgd_reg is allocated, save PGD also to scratch register */
if (pgd_reg != -1)
UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg);
else
uasm_i_nop(&p);
#endif
if (p >= tlbmiss_handler_setup_pgd_end)
panic("tlbmiss_handler_setup_pgd space exceeded");
@ -1504,7 +1493,6 @@ static void build_r4000_setup_pgd(void)
dump_handler("tlbmiss_handler", tlbmiss_handler_setup_pgd,
tlbmiss_handler_setup_pgd_size);
}
#endif
static void
iPTE_LW(u32 **p, unsigned int pte, unsigned int ptr)
@ -2197,10 +2185,8 @@ static void flush_tlb_handlers(void)
(unsigned long)handle_tlbs_end);
local_flush_icache_range((unsigned long)handle_tlbm,
(unsigned long)handle_tlbm_end);
#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
local_flush_icache_range((unsigned long)tlbmiss_handler_setup_pgd,
(unsigned long)tlbmiss_handler_setup_pgd_end);
#endif
}
void build_tlb_refill_handler(void)
@ -2232,6 +2218,7 @@ void build_tlb_refill_handler(void)
if (!run_once) {
if (!cpu_has_local_ebase)
build_r3000_tlb_refill_handler();
build_setup_pgd();
build_r3000_tlb_load_handler();
build_r3000_tlb_store_handler();
build_r3000_tlb_modify_handler();
@ -2255,9 +2242,7 @@ void build_tlb_refill_handler(void)
default:
if (!run_once) {
scratch_reg = allocate_kscratch();
#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
build_r4000_setup_pgd();
#endif
build_setup_pgd();
build_r4000_tlb_load_handler();
build_r4000_tlb_store_handler();
build_r4000_tlb_modify_handler();

1
arch/mips/mti-malta/malta-int.c
View File

@ -37,7 +37,6 @@
#include <asm/irq_regs.h>
#include <asm/mips-boards/malta.h>
#include <asm/mips-boards/maltaint.h>
#include <asm/mips-boards/piix4.h>
#include <asm/gt64120.h>
#include <asm/mips-boards/generic.h>
#include <asm/mips-boards/msc01_pci.h>

2
arch/mips/netlogic/common/smp.c
View File

@ -245,7 +245,7 @@ static int nlm_parse_cpumask(cpumask_t *wakeup_mask)
return threadmode;
unsupp:
panic("Unsupported CPU mask %lx\n",
panic("Unsupported CPU mask %lx",
(unsigned long)cpumask_bits(wakeup_mask)[0]);
return 0;
}

36
arch/mips/pci/fixup-malta.c
View File

@ -1,5 +1,6 @@
#include <linux/init.h>
#include <linux/pci.h>
#include <asm/mips-boards/piix4.h>
/* PCI interrupt pins */
#define PCIA 1
@ -53,7 +54,8 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
static void malta_piix_func0_fixup(struct pci_dev *pdev)
{
unsigned char reg_val;
static int piixirqmap[16] = { /* PIIX PIRQC[A:D] irq mappings */
/* PIIX PIRQC[A:D] irq mappings */
static int piixirqmap[PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MAX] = {
0, 0, 0, 3,
4, 5, 6, 7,
0, 9, 10, 11,
@ -63,11 +65,12 @@ static void malta_piix_func0_fixup(struct pci_dev *pdev)
/* Interrogate PIIX4 to get PCI IRQ mapping */
for (i = 0; i <= 3; i++) {
pci_read_config_byte(pdev, 0x60+i, &reg_val);
if (reg_val & 0x80)
pci_read_config_byte(pdev, PIIX4_FUNC0_PIRQRC+i, &reg_val);
if (reg_val & PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_DISABLE)
pci_irq[PCIA+i] = 0; /* Disabled */
else
pci_irq[PCIA+i] = piixirqmap[reg_val & 15];
pci_irq[PCIA+i] = piixirqmap[reg_val &
PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MASK];
}
/* Done by YAMON 2.00 onwards */
@ -76,8 +79,9 @@ static void malta_piix_func0_fixup(struct pci_dev *pdev)
* Set top of main memory accessible by ISA or DMA
* devices to 16 Mb.
*/
pci_read_config_byte(pdev, 0x69, &reg_val);
pci_write_config_byte(pdev, 0x69, reg_val | 0xf0);
pci_read_config_byte(pdev, PIIX4_FUNC0_TOM, &reg_val);
pci_write_config_byte(pdev, PIIX4_FUNC0_TOM, reg_val |
PIIX4_FUNC0_TOM_TOP_OF_MEMORY_MASK);
}
}
@ -93,10 +97,14 @@ static void malta_piix_func1_fixup(struct pci_dev *pdev)
/*
* IDE Decode enable.
*/
pci_read_config_byte(pdev, 0x41, &reg_val);
pci_write_config_byte(pdev, 0x41, reg_val|0x80);
pci_read_config_byte(pdev, 0x43, &reg_val);
pci_write_config_byte(pdev, 0x43, reg_val|0x80);
pci_read_config_byte(pdev, PIIX4_FUNC1_IDETIM_PRIMARY_HI,
&reg_val);
pci_write_config_byte(pdev, PIIX4_FUNC1_IDETIM_PRIMARY_HI,
reg_val|PIIX4_FUNC1_IDETIM_PRIMARY_HI_IDE_DECODE_EN);
pci_read_config_byte(pdev, PIIX4_FUNC1_IDETIM_SECONDARY_HI,
&reg_val);
pci_write_config_byte(pdev, PIIX4_FUNC1_IDETIM_SECONDARY_HI,
reg_val|PIIX4_FUNC1_IDETIM_SECONDARY_HI_IDE_DECODE_EN);
}
}
@ -108,10 +116,12 @@ static void quirk_dlcsetup(struct pci_dev *dev)
{
u8 odlc, ndlc;
(void) pci_read_config_byte(dev, 0x82, &odlc);
(void) pci_read_config_byte(dev, PIIX4_FUNC0_DLC, &odlc);
/* Enable passive releases and delayed transaction */
ndlc = odlc | 7;
(void) pci_write_config_byte(dev, 0x82, ndlc);
ndlc = odlc | PIIX4_FUNC0_DLC_USBPR_EN |
PIIX4_FUNC0_DLC_PASSIVE_RELEASE_EN |
PIIX4_FUNC0_DLC_DELAYED_TRANSACTION_EN;
(void) pci_write_config_byte(dev, PIIX4_FUNC0_DLC, ndlc);
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0,

3
arch/mips/pci/pci-ar71xx.c
View File

@ -363,9 +363,6 @@ static int ar71xx_pci_probe(struct platform_device *pdev)
spin_lock_init(&apc->lock);
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg_base");
if (!res)
return -EINVAL;
apc->cfg_base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(apc->cfg_base))
return PTR_ERR(apc->cfg_base);

9
arch/mips/pci/pci-ar724x.c
View File

@ -362,25 +362,16 @@ static int ar724x_pci_probe(struct platform_device *pdev)
return -ENOMEM;
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ctrl_base");
if (!res)
return -EINVAL;
apc->ctrl_base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(apc->ctrl_base))
return PTR_ERR(apc->ctrl_base);
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg_base");
if (!res)
return -EINVAL;
apc->devcfg_base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(apc->devcfg_base))
return PTR_ERR(apc->devcfg_base);
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "crp_base");
if (!res)
return -EINVAL;
apc->crp_base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(apc->crp_base))
return PTR_ERR(apc->crp_base);

50
arch/mips/pci/pci.c
View File

@ -120,51 +120,37 @@ static void pcibios_scanbus(struct pci_controller *hose)
#ifdef CONFIG_OF
void pci_load_of_ranges(struct pci_controller *hose, struct device_node *node)
{
const __be32 *ranges;
int rlen;
int pna = of_n_addr_cells(node);
int np = pna + 5;
struct of_pci_range range;
struct of_pci_range_parser parser;
pr_info("PCI host bridge %s ranges:\n", node->full_name);
ranges = of_get_property(node, "ranges", &rlen);
if (ranges == NULL)
return;
hose->of_node = node;
while ((rlen -= np * 4) >= 0) {
u32 pci_space;
struct resource *res = NULL;
u64 addr, size;
if (of_pci_range_parser_init(&parser, node))
return;
pci_space = be32_to_cpup(&ranges[0]);
addr = of_translate_address(node, ranges + 3);
size = of_read_number(ranges + pna + 3, 2);
ranges += np;
switch ((pci_space >> 24) & 0x3) {
case 1: /* PCI IO space */
for_each_of_pci_range(&parser, &range) {
struct resource *res = NULL;
switch (range.flags & IORESOURCE_TYPE_BITS) {
case IORESOURCE_IO:
pr_info(" IO 0x%016llx..0x%016llx\n",
addr, addr + size - 1);
range.cpu_addr,
range.cpu_addr + range.size - 1);
hose->io_map_base =
(unsigned long)ioremap(addr, size);
(unsigned long)ioremap(range.cpu_addr,
range.size);
res = hose->io_resource;
res->flags = IORESOURCE_IO;
break;
case 2: /* PCI Memory space */
case 3: /* PCI 64 bits Memory space */
case IORESOURCE_MEM:
pr_info(" MEM 0x%016llx..0x%016llx\n",
addr, addr + size - 1);
range.cpu_addr,
range.cpu_addr + range.size - 1);
res = hose->mem_resource;
res->flags = IORESOURCE_MEM;
break;
}
if (res != NULL) {
res->start = addr;
res->name = node->full_name;
res->end = res->start + size - 1;
res->parent = NULL;
res->sibling = NULL;
res->child = NULL;
}
if (res != NULL)
of_pci_range_to_resource(&range, node, res);
}
}

12
arch/mips/powertv/Kconfig
View File

@ -1,12 +0,0 @@
config BOOTLOADER_FAMILY
string "POWERTV Bootloader Family string"
default "85"
depends on POWERTV
help
This value should be specified when the bootloader driver is disabled
and must be exactly two characters long. Families supported are:
R1 - RNG-100 R2 - RNG-200
A1 - Class A B1 - Class B
E1 - Class E F1 - Class F
44 - 45xx 46 - 46xx
85 - 85xx 86 - 86xx

29
arch/mips/powertv/Makefile
View File

@ -1,29 +0,0 @@
#
# Carsten Langgaard, carstenl@mips.com
# Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
#
# Carsten Langgaard, carstenl@mips.com
# Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
# Portions copyright (C) 2009 Cisco Systems, Inc.
#
# This program is free software; you can distribute it and/or modify it
# under the terms of the GNU General Public License (Version 2) as
# published by the Free Software Foundation.
#
# This program is distributed in the hope it will be useful, but WITHOUT
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
# for more details.
#
# You should have received a copy of the GNU General Public License along
# with this program; if not, write to the Free Software Foundation, Inc.,
# 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
#
# Makefile for the Cisco PowerTV-specific kernel interface routines
# under Linux.
#
obj-y += init.o ioremap.o memory.o powertv_setup.o reset.o time.o \
asic/ pci/
obj-$(CONFIG_USB) += powertv-usb.o

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