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ARM: OMAP2+: clock: add support for indexed memmaps

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Using indexed memmaps is required for isolating the actual memory access
from the clock code. Now, the driver providing the support for the clock IP
block provides the low level routines for reading/writing clock registers
also.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
This commit is contained in:
Tero Kristo 2013-10-22 11:47:08 +03:00 committed by Mike Turquette
parent 6a67920811
commit 3ada6b10aa
2 changed files with 30 additions and 1 deletions
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26
arch/arm/mach-omap2/clock.c
View File

@ -26,7 +26,6 @@
#include <linux/clk-private.h>
#include <asm/cpu.h>
#include <trace/events/power.h>
#include "soc.h"
@ -56,6 +55,31 @@ u16 cpu_mask;
static bool clkdm_control = true;
static LIST_HEAD(clk_hw_omap_clocks);
void __iomem *clk_memmaps[CLK_MAX_MEMMAPS];
void omap2_clk_writel(u32 val, struct clk_hw_omap *clk, void __iomem *reg)
{
if (clk->flags & MEMMAP_ADDRESSING) {
struct clk_omap_reg *r = (struct clk_omap_reg *)&reg;
writel_relaxed(val, clk_memmaps[r->index] + r->offset);
} else {
writel_relaxed(val, reg);
}
}
u32 omap2_clk_readl(struct clk_hw_omap *clk, void __iomem *reg)
{
u32 val;
if (clk->flags & MEMMAP_ADDRESSING) {
struct clk_omap_reg *r = (struct clk_omap_reg *)&reg;
val = readl_relaxed(clk_memmaps[r->index] + r->offset);
} else {
val = readl_relaxed(reg);
}
return val;
}
/*
* Used for clocks that have the same value as the parent clock,

5
arch/arm/mach-omap2/clock.h
View File

@ -254,6 +254,9 @@ void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
const char *core_ck_name,
const char *mpu_ck_name);
u32 omap2_clk_readl(struct clk_hw_omap *clk, void __iomem *reg);
void omap2_clk_writel(u32 val, struct clk_hw_omap *clk, void __iomem *reg);
extern u16 cpu_mask;
extern const struct clkops clkops_omap2_dflt_wait;
@ -288,6 +291,8 @@ extern const struct clksel_rate div_1_3_rates[];
extern const struct clksel_rate div_1_4_rates[];
extern const struct clksel_rate div31_1to31_rates[];
extern void __iomem *clk_memmaps[];
extern int am33xx_clk_init(void);
extern int omap2_clkops_enable_clkdm(struct clk_hw *hw);