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https://github.com/torvalds/linux.git
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Merge branch 'stmmac-taprio'
Jose Abreu says: ==================== net: stmmac: TSN support using TAPRIO API This series adds TSN support (EST and Frame Preemption) for stmmac driver. 1) Adds the HW specific support for EST in GMAC5+ cores. 2) Adds the HW specific support for EST in XGMAC3+ cores. 3) Integrates EST HW specific support with TAPRIO scheduler API. 4) Adds the Frame Preemption suppor on stmmac TAPRIO implementation. 5) Adds the HW specific support for Frame Preemption in GMAC5+ cores. 6) Adds the HW specific support for Frame Preemption in XGMAC3+ cores. 7) Adds support for HW debug counters for Frame Preemption available in GMAC5+ cores. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
commit
3a74a62d3c
@ -363,6 +363,11 @@ struct dma_features {
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unsigned int dvlan;
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unsigned int l3l4fnum;
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unsigned int arpoffsel;
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/* TSN Features */
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unsigned int estwid;
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unsigned int estdep;
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unsigned int estsel;
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unsigned int fpesel;
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};
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/* GMAC TX FIFO is 8K, Rx FIFO is 16K */
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@ -64,6 +64,8 @@
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#define GMAC_RXQCTRL_MCBCQEN_SHIFT 20
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#define GMAC_RXQCTRL_TACPQE BIT(21)
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#define GMAC_RXQCTRL_TACPQE_SHIFT 21
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#define GMAC_RXQCTRL_FPRQ GENMASK(26, 24)
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#define GMAC_RXQCTRL_FPRQ_SHIFT 24
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/* MAC Packet Filtering */
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#define GMAC_PACKET_FILTER_PR BIT(0)
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@ -176,6 +178,8 @@ enum power_event {
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#define GMAC_CONFIG_SARC GENMASK(30, 28)
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#define GMAC_CONFIG_SARC_SHIFT 28
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#define GMAC_CONFIG_IPC BIT(27)
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#define GMAC_CONFIG_IPG GENMASK(26, 24)
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#define GMAC_CONFIG_IPG_SHIFT 24
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#define GMAC_CONFIG_2K BIT(22)
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#define GMAC_CONFIG_ACS BIT(20)
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#define GMAC_CONFIG_BE BIT(18)
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@ -183,6 +187,7 @@ enum power_event {
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#define GMAC_CONFIG_JE BIT(16)
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#define GMAC_CONFIG_PS BIT(15)
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#define GMAC_CONFIG_FES BIT(14)
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#define GMAC_CONFIG_FES_SHIFT 14
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#define GMAC_CONFIG_DM BIT(13)
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#define GMAC_CONFIG_LM BIT(12)
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#define GMAC_CONFIG_DCRS BIT(9)
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@ -190,6 +195,9 @@ enum power_event {
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#define GMAC_CONFIG_RE BIT(0)
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/* MAC extended config */
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#define GMAC_CONFIG_EIPG GENMASK(29, 25)
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#define GMAC_CONFIG_EIPG_SHIFT 25
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#define GMAC_CONFIG_EIPG_EN BIT(24)
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#define GMAC_CONFIG_HDSMS GENMASK(22, 20)
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#define GMAC_CONFIG_HDSMS_SHIFT 20
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#define GMAC_CONFIG_HDSMS_256 (0x2 << GMAC_CONFIG_HDSMS_SHIFT)
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@ -231,6 +239,10 @@ enum power_event {
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/* MAC HW features3 bitmap */
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#define GMAC_HW_FEAT_ASP GENMASK(29, 28)
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#define GMAC_HW_FEAT_FPESEL BIT(26)
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#define GMAC_HW_FEAT_ESTWID GENMASK(21, 20)
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#define GMAC_HW_FEAT_ESTDEP GENMASK(19, 17)
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#define GMAC_HW_FEAT_ESTSEL BIT(16)
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#define GMAC_HW_FEAT_FRPES GENMASK(14, 13)
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#define GMAC_HW_FEAT_FRPBS GENMASK(12, 11)
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#define GMAC_HW_FEAT_FRPSEL BIT(10)
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@ -984,6 +984,8 @@ const struct stmmac_ops dwmac410_ops = {
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.set_arp_offload = dwmac4_set_arp_offload,
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.config_l3_filter = dwmac4_config_l3_filter,
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.config_l4_filter = dwmac4_config_l4_filter,
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.est_configure = dwmac5_est_configure,
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.fpe_configure = dwmac5_fpe_configure,
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};
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const struct stmmac_ops dwmac510_ops = {
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@ -1027,6 +1029,8 @@ const struct stmmac_ops dwmac510_ops = {
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.set_arp_offload = dwmac4_set_arp_offload,
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.config_l3_filter = dwmac4_config_l3_filter,
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.config_l4_filter = dwmac4_config_l4_filter,
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.est_configure = dwmac5_est_configure,
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.fpe_configure = dwmac5_fpe_configure,
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};
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int dwmac4_setup(struct stmmac_priv *priv)
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@ -404,6 +404,10 @@ static void dwmac4_get_hw_feature(void __iomem *ioaddr,
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/* 5.10 Features */
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dma_cap->asp = (hw_cap & GMAC_HW_FEAT_ASP) >> 28;
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dma_cap->fpesel = (hw_cap & GMAC_HW_FEAT_FPESEL) >> 26;
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dma_cap->estwid = (hw_cap & GMAC_HW_FEAT_ESTWID) >> 20;
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dma_cap->estdep = (hw_cap & GMAC_HW_FEAT_ESTDEP) >> 17;
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dma_cap->estsel = (hw_cap & GMAC_HW_FEAT_ESTSEL) >> 16;
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dma_cap->frpes = (hw_cap & GMAC_HW_FEAT_FRPES) >> 13;
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dma_cap->frpbs = (hw_cap & GMAC_HW_FEAT_FRPBS) >> 11;
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dma_cap->frpsel = (hw_cap & GMAC_HW_FEAT_FRPSEL) >> 10;
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@ -550,3 +550,121 @@ int dwmac5_flex_pps_config(void __iomem *ioaddr, int index,
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writel(val, ioaddr + MAC_PPS_CONTROL);
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return 0;
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}
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static int dwmac5_est_write(void __iomem *ioaddr, u32 reg, u32 val, bool gcl)
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{
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u32 ctrl;
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writel(val, ioaddr + MTL_EST_GCL_DATA);
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ctrl = (reg << ADDR_SHIFT);
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ctrl |= gcl ? 0 : GCRR;
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writel(ctrl, ioaddr + MTL_EST_GCL_CONTROL);
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ctrl |= SRWO;
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writel(ctrl, ioaddr + MTL_EST_GCL_CONTROL);
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return readl_poll_timeout(ioaddr + MTL_EST_GCL_CONTROL,
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ctrl, !(ctrl & SRWO), 100, 5000);
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}
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int dwmac5_est_configure(void __iomem *ioaddr, struct stmmac_est *cfg,
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unsigned int ptp_rate)
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{
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u32 speed, total_offset, offset, ctrl, ctr_low;
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u32 extcfg = readl(ioaddr + GMAC_EXT_CONFIG);
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u32 mac_cfg = readl(ioaddr + GMAC_CONFIG);
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int i, ret = 0x0;
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u64 total_ctr;
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if (extcfg & GMAC_CONFIG_EIPG_EN) {
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offset = (extcfg & GMAC_CONFIG_EIPG) >> GMAC_CONFIG_EIPG_SHIFT;
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offset = 104 + (offset * 8);
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} else {
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offset = (mac_cfg & GMAC_CONFIG_IPG) >> GMAC_CONFIG_IPG_SHIFT;
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offset = 96 - (offset * 8);
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}
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speed = mac_cfg & (GMAC_CONFIG_PS | GMAC_CONFIG_FES);
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speed = speed >> GMAC_CONFIG_FES_SHIFT;
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switch (speed) {
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case 0x0:
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offset = offset * 1000; /* 1G */
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break;
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case 0x1:
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offset = offset * 400; /* 2.5G */
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break;
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case 0x2:
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offset = offset * 100000; /* 10M */
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break;
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case 0x3:
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offset = offset * 10000; /* 100M */
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break;
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default:
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return -EINVAL;
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}
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offset = offset / 1000;
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ret |= dwmac5_est_write(ioaddr, BTR_LOW, cfg->btr[0], false);
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ret |= dwmac5_est_write(ioaddr, BTR_HIGH, cfg->btr[1], false);
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ret |= dwmac5_est_write(ioaddr, TER, cfg->ter, false);
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ret |= dwmac5_est_write(ioaddr, LLR, cfg->gcl_size, false);
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if (ret)
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return ret;
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total_offset = 0;
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for (i = 0; i < cfg->gcl_size; i++) {
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ret = dwmac5_est_write(ioaddr, i, cfg->gcl[i] + offset, true);
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if (ret)
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return ret;
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total_offset += offset;
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}
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total_ctr = cfg->ctr[0] + cfg->ctr[1] * 1000000000;
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total_ctr += total_offset;
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ctr_low = do_div(total_ctr, 1000000000);
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ret |= dwmac5_est_write(ioaddr, CTR_LOW, ctr_low, false);
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ret |= dwmac5_est_write(ioaddr, CTR_HIGH, total_ctr, false);
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if (ret)
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return ret;
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ctrl = readl(ioaddr + MTL_EST_CONTROL);
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ctrl &= ~PTOV;
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ctrl |= ((1000000000 / ptp_rate) * 6) << PTOV_SHIFT;
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if (cfg->enable)
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ctrl |= EEST | SSWL;
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else
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ctrl &= ~EEST;
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writel(ctrl, ioaddr + MTL_EST_CONTROL);
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return 0;
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}
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void dwmac5_fpe_configure(void __iomem *ioaddr, u32 num_txq, u32 num_rxq,
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bool enable)
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{
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u32 value;
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if (!enable) {
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value = readl(ioaddr + MAC_FPE_CTRL_STS);
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value &= ~EFPE;
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writel(value, ioaddr + MAC_FPE_CTRL_STS);
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}
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value = readl(ioaddr + GMAC_RXQ_CTRL1);
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value &= ~GMAC_RXQCTRL_FPRQ;
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value |= (num_rxq - 1) << GMAC_RXQCTRL_FPRQ_SHIFT;
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writel(value, ioaddr + GMAC_RXQ_CTRL1);
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value = readl(ioaddr + MAC_FPE_CTRL_STS);
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value |= EFPE;
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writel(value, ioaddr + MAC_FPE_CTRL_STS);
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}
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@ -11,6 +11,9 @@
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#define PRTYEN BIT(1)
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#define TMOUTEN BIT(0)
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#define MAC_FPE_CTRL_STS 0x00000234
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#define EFPE BIT(0)
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#define MAC_PPS_CONTROL 0x00000b70
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#define PPS_MAXIDX(x) ((((x) + 1) * 8) - 1)
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#define PPS_MINIDX(x) ((x) * 8)
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@ -30,6 +33,23 @@
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#define MAC_PPSx_INTERVAL(x) (0x00000b88 + ((x) * 0x10))
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#define MAC_PPSx_WIDTH(x) (0x00000b8c + ((x) * 0x10))
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#define MTL_EST_CONTROL 0x00000c50
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#define PTOV GENMASK(31, 24)
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#define PTOV_SHIFT 24
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#define SSWL BIT(1)
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#define EEST BIT(0)
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#define MTL_EST_GCL_CONTROL 0x00000c80
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#define BTR_LOW 0x0
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#define BTR_HIGH 0x1
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#define CTR_LOW 0x2
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#define CTR_HIGH 0x3
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#define TER 0x4
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#define LLR 0x5
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#define ADDR_SHIFT 8
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#define GCRR BIT(2)
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#define SRWO BIT(0)
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#define MTL_EST_GCL_DATA 0x00000c84
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#define MTL_RXP_CONTROL_STATUS 0x00000ca0
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#define RXPI BIT(31)
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#define NPE GENMASK(23, 16)
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@ -83,5 +103,9 @@ int dwmac5_rxp_config(void __iomem *ioaddr, struct stmmac_tc_entry *entries,
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int dwmac5_flex_pps_config(void __iomem *ioaddr, int index,
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struct stmmac_pps_cfg *cfg, bool enable,
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u32 sub_second_inc, u32 systime_flags);
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int dwmac5_est_configure(void __iomem *ioaddr, struct stmmac_est *cfg,
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unsigned int ptp_rate);
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void dwmac5_fpe_configure(void __iomem *ioaddr, u32 num_txq, u32 num_rxq,
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bool enable);
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#endif /* __DWMAC5_H__ */
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@ -73,6 +73,9 @@
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#define XGMAC_RXQ_CTRL0 0x000000a0
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#define XGMAC_RXQEN(x) GENMASK((x) * 2 + 1, (x) * 2)
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#define XGMAC_RXQEN_SHIFT(x) ((x) * 2)
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#define XGMAC_RXQ_CTRL1 0x000000a4
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#define XGMAC_RQ GENMASK(7, 4)
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#define XGMAC_RQ_SHIFT 4
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#define XGMAC_RXQ_CTRL2 0x000000a8
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#define XGMAC_RXQ_CTRL3 0x000000ac
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#define XGMAC_PSRQ(x) GENMASK((x) * 8 + 7, (x) * 8)
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@ -136,6 +139,10 @@
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#define XGMAC_HWFEAT_TXQCNT GENMASK(9, 6)
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#define XGMAC_HWFEAT_RXQCNT GENMASK(3, 0)
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#define XGMAC_HW_FEATURE3 0x00000128
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#define XGMAC_HWFEAT_FPESEL BIT(26)
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#define XGMAC_HWFEAT_ESTWID GENMASK(24, 23)
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#define XGMAC_HWFEAT_ESTDEP GENMASK(22, 20)
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#define XGMAC_HWFEAT_ESTSEL BIT(19)
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#define XGMAC_HWFEAT_ASP GENMASK(15, 14)
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#define XGMAC_HWFEAT_DVLAN BIT(13)
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#define XGMAC_HWFEAT_FRPES GENMASK(12, 11)
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@ -148,6 +155,8 @@
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#define XGMAC_MDIO_ADDR 0x00000200
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#define XGMAC_MDIO_DATA 0x00000204
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#define XGMAC_MDIO_C22P 0x00000220
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#define XGMAC_FPE_CTRL_STS 0x00000280
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#define XGMAC_EFPE BIT(0)
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#define XGMAC_ADDRx_HIGH(x) (0x00000300 + (x) * 0x8)
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#define XGMAC_ADDR_MAX 32
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#define XGMAC_AE BIT(31)
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@ -237,6 +246,22 @@
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#define XGMAC_TC_PRTY_MAP1 0x00001044
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#define XGMAC_PSTC(x) GENMASK((x) * 8 + 7, (x) * 8)
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#define XGMAC_PSTC_SHIFT(x) ((x) * 8)
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#define XGMAC_MTL_EST_CONTROL 0x00001050
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#define XGMAC_PTOV GENMASK(31, 23)
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#define XGMAC_PTOV_SHIFT 23
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#define XGMAC_SSWL BIT(1)
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#define XGMAC_EEST BIT(0)
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#define XGMAC_MTL_EST_GCL_CONTROL 0x00001080
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#define XGMAC_BTR_LOW 0x0
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#define XGMAC_BTR_HIGH 0x1
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#define XGMAC_CTR_LOW 0x2
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#define XGMAC_CTR_HIGH 0x3
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#define XGMAC_TER 0x4
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#define XGMAC_LLR 0x5
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#define XGMAC_ADDR_SHIFT 8
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#define XGMAC_GCRR BIT(2)
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#define XGMAC_SRWO BIT(0)
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#define XGMAC_MTL_EST_GCL_DATA 0x00001084
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#define XGMAC_MTL_RXP_CONTROL_STATUS 0x000010a0
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#define XGMAC_RXPI BIT(31)
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#define XGMAC_NPE GENMASK(23, 16)
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@ -1359,6 +1359,80 @@ static void dwxgmac2_set_arp_offload(struct mac_device_info *hw, bool en,
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writel(value, ioaddr + XGMAC_RX_CONFIG);
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}
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static int dwxgmac3_est_write(void __iomem *ioaddr, u32 reg, u32 val, bool gcl)
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{
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u32 ctrl;
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writel(val, ioaddr + XGMAC_MTL_EST_GCL_DATA);
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ctrl = (reg << XGMAC_ADDR_SHIFT);
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ctrl |= gcl ? 0 : XGMAC_GCRR;
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writel(ctrl, ioaddr + XGMAC_MTL_EST_GCL_CONTROL);
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ctrl |= XGMAC_SRWO;
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writel(ctrl, ioaddr + XGMAC_MTL_EST_GCL_CONTROL);
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return readl_poll_timeout_atomic(ioaddr + XGMAC_MTL_EST_GCL_CONTROL,
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ctrl, !(ctrl & XGMAC_SRWO), 100, 5000);
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}
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static int dwxgmac3_est_configure(void __iomem *ioaddr, struct stmmac_est *cfg,
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unsigned int ptp_rate)
|
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{
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int i, ret = 0x0;
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u32 ctrl;
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ret |= dwxgmac3_est_write(ioaddr, XGMAC_BTR_LOW, cfg->btr[0], false);
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ret |= dwxgmac3_est_write(ioaddr, XGMAC_BTR_HIGH, cfg->btr[1], false);
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ret |= dwxgmac3_est_write(ioaddr, XGMAC_TER, cfg->ter, false);
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ret |= dwxgmac3_est_write(ioaddr, XGMAC_LLR, cfg->gcl_size, false);
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ret |= dwxgmac3_est_write(ioaddr, XGMAC_CTR_LOW, cfg->ctr[0], false);
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ret |= dwxgmac3_est_write(ioaddr, XGMAC_CTR_HIGH, cfg->ctr[1], false);
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if (ret)
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return ret;
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for (i = 0; i < cfg->gcl_size; i++) {
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ret = dwxgmac3_est_write(ioaddr, i, cfg->gcl[i], true);
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if (ret)
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return ret;
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}
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ctrl = readl(ioaddr + XGMAC_MTL_EST_CONTROL);
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ctrl &= ~XGMAC_PTOV;
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ctrl |= ((1000000000 / ptp_rate) * 9) << XGMAC_PTOV_SHIFT;
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if (cfg->enable)
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ctrl |= XGMAC_EEST | XGMAC_SSWL;
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else
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ctrl &= ~XGMAC_EEST;
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writel(ctrl, ioaddr + XGMAC_MTL_EST_CONTROL);
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return 0;
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}
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static void dwxgmac3_fpe_configure(void __iomem *ioaddr, u32 num_txq,
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u32 num_rxq, bool enable)
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{
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u32 value;
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if (!enable) {
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value = readl(ioaddr + XGMAC_FPE_CTRL_STS);
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value &= ~XGMAC_EFPE;
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writel(value, ioaddr + XGMAC_FPE_CTRL_STS);
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}
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value = readl(ioaddr + XGMAC_RXQ_CTRL1);
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value &= ~XGMAC_RQ;
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value |= (num_rxq - 1) << XGMAC_RQ_SHIFT;
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writel(value, ioaddr + XGMAC_RXQ_CTRL1);
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value = readl(ioaddr + XGMAC_FPE_CTRL_STS);
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value |= XGMAC_EFPE;
|
||||
writel(value, ioaddr + XGMAC_FPE_CTRL_STS);
|
||||
}
|
||||
|
||||
const struct stmmac_ops dwxgmac210_ops = {
|
||||
.core_init = dwxgmac2_core_init,
|
||||
.set_mac = dwxgmac2_set_mac,
|
||||
@ -1402,6 +1476,8 @@ const struct stmmac_ops dwxgmac210_ops = {
|
||||
.config_l3_filter = dwxgmac2_config_l3_filter,
|
||||
.config_l4_filter = dwxgmac2_config_l4_filter,
|
||||
.set_arp_offload = dwxgmac2_set_arp_offload,
|
||||
.est_configure = dwxgmac3_est_configure,
|
||||
.fpe_configure = dwxgmac3_fpe_configure,
|
||||
};
|
||||
|
||||
int dwxgmac2_setup(struct stmmac_priv *priv)
|
||||
|
||||
@ -429,6 +429,10 @@ static void dwxgmac2_get_hw_feature(void __iomem *ioaddr,
|
||||
|
||||
/* MAC HW feature 3 */
|
||||
hw_cap = readl(ioaddr + XGMAC_HW_FEATURE3);
|
||||
dma_cap->fpesel = (hw_cap & XGMAC_HWFEAT_FPESEL) >> 26;
|
||||
dma_cap->estwid = (hw_cap & XGMAC_HWFEAT_ESTWID) >> 23;
|
||||
dma_cap->estdep = (hw_cap & XGMAC_HWFEAT_ESTDEP) >> 20;
|
||||
dma_cap->estsel = (hw_cap & XGMAC_HWFEAT_ESTSEL) >> 19;
|
||||
dma_cap->asp = (hw_cap & XGMAC_HWFEAT_ASP) >> 14;
|
||||
dma_cap->dvlan = (hw_cap & XGMAC_HWFEAT_DVLAN) >> 13;
|
||||
dma_cap->frpes = (hw_cap & XGMAC_HWFEAT_FRPES) >> 11;
|
||||
|
||||
@ -276,6 +276,7 @@ struct stmmac_safety_stats;
|
||||
struct stmmac_tc_entry;
|
||||
struct stmmac_pps_cfg;
|
||||
struct stmmac_rss;
|
||||
struct stmmac_est;
|
||||
|
||||
/* Helpers to program the MAC core */
|
||||
struct stmmac_ops {
|
||||
@ -373,6 +374,10 @@ struct stmmac_ops {
|
||||
bool en, bool udp, bool sa, bool inv,
|
||||
u32 match);
|
||||
void (*set_arp_offload)(struct mac_device_info *hw, bool en, u32 addr);
|
||||
int (*est_configure)(void __iomem *ioaddr, struct stmmac_est *cfg,
|
||||
unsigned int ptp_rate);
|
||||
void (*fpe_configure)(void __iomem *ioaddr, u32 num_txq, u32 num_rxq,
|
||||
bool enable);
|
||||
};
|
||||
|
||||
#define stmmac_core_init(__priv, __args...) \
|
||||
@ -459,6 +464,10 @@ struct stmmac_ops {
|
||||
stmmac_do_callback(__priv, mac, config_l4_filter, __args)
|
||||
#define stmmac_set_arp_offload(__priv, __args...) \
|
||||
stmmac_do_void_callback(__priv, mac, set_arp_offload, __args)
|
||||
#define stmmac_est_configure(__priv, __args...) \
|
||||
stmmac_do_callback(__priv, mac, est_configure, __args)
|
||||
#define stmmac_fpe_configure(__priv, __args...) \
|
||||
stmmac_do_void_callback(__priv, mac, fpe_configure, __args)
|
||||
|
||||
/* PTP and HW Timer helpers */
|
||||
struct stmmac_hwtimestamp {
|
||||
@ -516,6 +525,7 @@ struct stmmac_priv;
|
||||
struct tc_cls_u32_offload;
|
||||
struct tc_cbs_qopt_offload;
|
||||
struct flow_cls_offload;
|
||||
struct tc_taprio_qopt_offload;
|
||||
|
||||
struct stmmac_tc_ops {
|
||||
int (*init)(struct stmmac_priv *priv);
|
||||
@ -525,6 +535,8 @@ struct stmmac_tc_ops {
|
||||
struct tc_cbs_qopt_offload *qopt);
|
||||
int (*setup_cls)(struct stmmac_priv *priv,
|
||||
struct flow_cls_offload *cls);
|
||||
int (*setup_taprio)(struct stmmac_priv *priv,
|
||||
struct tc_taprio_qopt_offload *qopt);
|
||||
};
|
||||
|
||||
#define stmmac_tc_init(__priv, __args...) \
|
||||
@ -535,6 +547,8 @@ struct stmmac_tc_ops {
|
||||
stmmac_do_callback(__priv, tc, setup_cbs, __args)
|
||||
#define stmmac_tc_setup_cls(__priv, __args...) \
|
||||
stmmac_do_callback(__priv, tc, setup_cls, __args)
|
||||
#define stmmac_tc_setup_taprio(__priv, __args...) \
|
||||
stmmac_do_callback(__priv, tc, setup_taprio, __args)
|
||||
|
||||
struct stmmac_counters;
|
||||
|
||||
|
||||
@ -119,6 +119,13 @@
|
||||
#define MMC_RX_ICMP_GD_OCTETS 0x180
|
||||
#define MMC_RX_ICMP_ERR_OCTETS 0x184
|
||||
|
||||
#define MMC_TX_FPE_FRAG 0x1a8
|
||||
#define MMC_TX_HOLD_REQ 0x1ac
|
||||
#define MMC_RX_PKT_ASSEMBLY_ERR 0x1c8
|
||||
#define MMC_RX_PKT_SMD_ERR 0x1cc
|
||||
#define MMC_RX_PKT_ASSEMBLY_OK 0x1d0
|
||||
#define MMC_RX_FPE_FRAG 0x1d4
|
||||
|
||||
/* XGMAC MMC Registers */
|
||||
#define MMC_XGMAC_TX_OCTET_GB 0x14
|
||||
#define MMC_XGMAC_TX_PKT_GB 0x1c
|
||||
@ -315,6 +322,15 @@ static void dwmac_mmc_read(void __iomem *mmcaddr, struct stmmac_counters *mmc)
|
||||
mmc->mmc_rx_tcp_err_octets += readl(mmcaddr + MMC_RX_TCP_ERR_OCTETS);
|
||||
mmc->mmc_rx_icmp_gd_octets += readl(mmcaddr + MMC_RX_ICMP_GD_OCTETS);
|
||||
mmc->mmc_rx_icmp_err_octets += readl(mmcaddr + MMC_RX_ICMP_ERR_OCTETS);
|
||||
|
||||
mmc->mmc_tx_fpe_fragment_cntr += readl(mmcaddr + MMC_TX_FPE_FRAG);
|
||||
mmc->mmc_tx_hold_req_cntr += readl(mmcaddr + MMC_TX_HOLD_REQ);
|
||||
mmc->mmc_rx_packet_assembly_err_cntr +=
|
||||
readl(mmcaddr + MMC_RX_PKT_ASSEMBLY_ERR);
|
||||
mmc->mmc_rx_packet_smd_err_cntr += readl(mmcaddr + MMC_RX_PKT_SMD_ERR);
|
||||
mmc->mmc_rx_packet_assembly_ok_cntr +=
|
||||
readl(mmcaddr + MMC_RX_PKT_ASSEMBLY_OK);
|
||||
mmc->mmc_rx_fpe_fragment_cntr += readl(mmcaddr + MMC_RX_FPE_FRAG);
|
||||
}
|
||||
|
||||
const struct stmmac_mmc_ops dwmac_mmc_ops = {
|
||||
|
||||
@ -4076,6 +4076,8 @@ static int stmmac_setup_tc(struct net_device *ndev, enum tc_setup_type type,
|
||||
priv, priv, true);
|
||||
case TC_SETUP_QDISC_CBS:
|
||||
return stmmac_tc_setup_cbs(priv, priv, type_data);
|
||||
case TC_SETUP_QDISC_TAPRIO:
|
||||
return stmmac_tc_setup_taprio(priv, priv, type_data);
|
||||
default:
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
|
||||
@ -591,9 +591,144 @@ static int tc_setup_cls(struct stmmac_priv *priv,
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int tc_setup_taprio(struct stmmac_priv *priv,
|
||||
struct tc_taprio_qopt_offload *qopt)
|
||||
{
|
||||
u32 size, wid = priv->dma_cap.estwid, dep = priv->dma_cap.estdep;
|
||||
struct plat_stmmacenet_data *plat = priv->plat;
|
||||
struct timespec64 time;
|
||||
bool fpe = false;
|
||||
int i, ret = 0;
|
||||
|
||||
if (!priv->dma_cap.estsel)
|
||||
return -EOPNOTSUPP;
|
||||
|
||||
switch (wid) {
|
||||
case 0x1:
|
||||
wid = 16;
|
||||
break;
|
||||
case 0x2:
|
||||
wid = 20;
|
||||
break;
|
||||
case 0x3:
|
||||
wid = 24;
|
||||
break;
|
||||
default:
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
|
||||
switch (dep) {
|
||||
case 0x1:
|
||||
dep = 64;
|
||||
break;
|
||||
case 0x2:
|
||||
dep = 128;
|
||||
break;
|
||||
case 0x3:
|
||||
dep = 256;
|
||||
break;
|
||||
case 0x4:
|
||||
dep = 512;
|
||||
break;
|
||||
case 0x5:
|
||||
dep = 1024;
|
||||
break;
|
||||
default:
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
|
||||
if (!qopt->enable)
|
||||
goto disable;
|
||||
if (qopt->num_entries >= dep)
|
||||
return -EINVAL;
|
||||
if (!qopt->base_time)
|
||||
return -ERANGE;
|
||||
if (!qopt->cycle_time)
|
||||
return -ERANGE;
|
||||
|
||||
if (!plat->est) {
|
||||
plat->est = devm_kzalloc(priv->device, sizeof(*plat->est),
|
||||
GFP_KERNEL);
|
||||
if (!plat->est)
|
||||
return -ENOMEM;
|
||||
} else {
|
||||
memset(plat->est, 0, sizeof(*plat->est));
|
||||
}
|
||||
|
||||
size = qopt->num_entries;
|
||||
|
||||
priv->plat->est->gcl_size = size;
|
||||
priv->plat->est->enable = qopt->enable;
|
||||
|
||||
for (i = 0; i < size; i++) {
|
||||
s64 delta_ns = qopt->entries[i].interval;
|
||||
u32 gates = qopt->entries[i].gate_mask;
|
||||
|
||||
if (delta_ns > GENMASK(wid, 0))
|
||||
return -ERANGE;
|
||||
if (gates > GENMASK(31 - wid, 0))
|
||||
return -ERANGE;
|
||||
|
||||
switch (qopt->entries[i].command) {
|
||||
case TC_TAPRIO_CMD_SET_GATES:
|
||||
if (fpe)
|
||||
return -EINVAL;
|
||||
break;
|
||||
case TC_TAPRIO_CMD_SET_AND_HOLD:
|
||||
gates |= BIT(0);
|
||||
fpe = true;
|
||||
break;
|
||||
case TC_TAPRIO_CMD_SET_AND_RELEASE:
|
||||
gates &= ~BIT(0);
|
||||
fpe = true;
|
||||
break;
|
||||
default:
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
|
||||
priv->plat->est->gcl[i] = delta_ns | (gates << wid);
|
||||
}
|
||||
|
||||
/* Adjust for real system time */
|
||||
time = ktime_to_timespec64(qopt->base_time);
|
||||
priv->plat->est->btr[0] = (u32)time.tv_nsec;
|
||||
priv->plat->est->btr[1] = (u32)time.tv_sec;
|
||||
|
||||
priv->plat->est->ctr[0] = (u32)(qopt->cycle_time % NSEC_PER_SEC);
|
||||
priv->plat->est->ctr[1] = (u32)(qopt->cycle_time / NSEC_PER_SEC);
|
||||
|
||||
if (fpe && !priv->dma_cap.fpesel)
|
||||
return -EOPNOTSUPP;
|
||||
|
||||
ret = stmmac_fpe_configure(priv, priv->ioaddr,
|
||||
priv->plat->tx_queues_to_use,
|
||||
priv->plat->rx_queues_to_use, fpe);
|
||||
if (ret && fpe) {
|
||||
netdev_err(priv->dev, "failed to enable Frame Preemption\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = stmmac_est_configure(priv, priv->ioaddr, priv->plat->est,
|
||||
priv->plat->clk_ptp_rate);
|
||||
if (ret) {
|
||||
netdev_err(priv->dev, "failed to configure EST\n");
|
||||
goto disable;
|
||||
}
|
||||
|
||||
netdev_info(priv->dev, "configured EST\n");
|
||||
return 0;
|
||||
|
||||
disable:
|
||||
priv->plat->est->enable = false;
|
||||
stmmac_est_configure(priv, priv->ioaddr, priv->plat->est,
|
||||
priv->plat->clk_ptp_rate);
|
||||
return ret;
|
||||
}
|
||||
|
||||
const struct stmmac_tc_ops dwmac510_tc_ops = {
|
||||
.init = tc_init,
|
||||
.setup_cls_u32 = tc_setup_cls_u32,
|
||||
.setup_cbs = tc_setup_cbs,
|
||||
.setup_cls = tc_setup_cls,
|
||||
.setup_taprio = tc_setup_taprio,
|
||||
};
|
||||
|
||||
@ -109,6 +109,18 @@ struct stmmac_axi {
|
||||
bool axi_rb;
|
||||
};
|
||||
|
||||
#define EST_GCL 1024
|
||||
struct stmmac_est {
|
||||
int enable;
|
||||
u32 btr_offset[2];
|
||||
u32 btr[2];
|
||||
u32 ctr[2];
|
||||
u32 ter;
|
||||
u32 gcl_unaligned[EST_GCL];
|
||||
u32 gcl[EST_GCL];
|
||||
u32 gcl_size;
|
||||
};
|
||||
|
||||
struct stmmac_rxq_cfg {
|
||||
u8 mode_to_use;
|
||||
u32 chan;
|
||||
@ -139,6 +151,7 @@ struct plat_stmmacenet_data {
|
||||
struct device_node *phylink_node;
|
||||
struct device_node *mdio_node;
|
||||
struct stmmac_dma_cfg *dma_cfg;
|
||||
struct stmmac_est *est;
|
||||
int clk_csr;
|
||||
int has_gmac;
|
||||
int enh_desc;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user