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PCI: starfive: Add JH7110 PCIe controller
Add StarFive JH7110 SoC PCIe controller platform driver code, JH7110 with PLDA host PCIe core. Link: https://lore.kernel.org/linux-pci/20240328091835.14797-22-minda.chen@starfivetech.com Co-developed-by: Kevin Xie <kevin.xie@starfivetech.com> Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Mason Huo <mason.huo@starfivetech.com>
This commit is contained in:
Minda Chen
Bjorn Helgaas
parent
22fe322397
commit
39b91eb40c
@ -17492,6 +17492,7 @@ M: Kevin Xie <kevin.xie@starfivetech.com>
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L: linux-pci@vger.kernel.org
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S: Maintained
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F: Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml
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F: drivers/pci/controller/plda/pcie-starfive.c
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PCIE ENDPOINT DRIVER FOR QUALCOMM
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M: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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@ -15,4 +15,16 @@ config PCIE_MICROCHIP_HOST
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Say Y here if you want kernel to support the Microchip AXI PCIe
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Host Bridge driver.
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config PCIE_STARFIVE_HOST
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tristate "StarFive PCIe host controller"
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depends on PCI_MSI && OF
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depends on ARCH_STARFIVE || COMPILE_TEST
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select PCIE_PLDA_HOST
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help
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Say Y here if you want to support the StarFive PCIe controller in
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host mode. StarFive PCIe controller uses PLDA PCIe core.
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If you choose to build this driver as module it will be dynamically
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linked and module will be called pcie-starfive.ko.
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endmenu
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@ -1,3 +1,4 @@
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# SPDX-License-Identifier: GPL-2.0
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obj-$(CONFIG_PCIE_PLDA_HOST) += pcie-plda-host.o
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obj-$(CONFIG_PCIE_MICROCHIP_HOST) += pcie-microchip-host.o
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obj-$(CONFIG_PCIE_STARFIVE_HOST) += pcie-starfive.o
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@ -10,10 +10,20 @@
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#define PLDA_MAX_NUM_MSI_IRQS 32
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/* PCIe Bridge Phy Regs */
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#define GEN_SETTINGS 0x80
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#define RP_ENABLE 1
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#define PCIE_PCI_IDS_DW1 0x9c
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#define IDS_CLASS_CODE_SHIFT 16
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#define REVISION_ID_MASK GENMASK(7, 0)
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#define CLASS_CODE_ID_MASK GENMASK(31, 8)
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#define PCIE_PCI_IRQ_DW0 0xa8
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#define MSIX_CAP_MASK BIT(31)
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#define NUM_MSI_MSGS_MASK GENMASK(6, 4)
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#define NUM_MSI_MSGS_SHIFT 4
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#define PCI_MISC 0xb4
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#define PHY_FUNCTION_DIS BIT(15)
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#define PCIE_WINROM 0xfc
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#define PREF_MEM_WIN_64_SUPPORT BIT(3)
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#define IMASK_LOCAL 0x180
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#define DMA_END_ENGINE_0_MASK 0x00000000u
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@ -65,6 +75,8 @@
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#define ISTATUS_HOST 0x18c
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#define IMSI_ADDR 0x190
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#define ISTATUS_MSI 0x194
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#define PMSG_SUPPORT_RX 0x3f0
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#define PMSG_LTR_SUPPORT BIT(2)
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/* PCIe Master table init defines */
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#define ATR0_PCIE_WIN0_SRCADDR_PARAM 0x600u
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@ -86,6 +98,8 @@
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#define PCIE_TX_RX_INTERFACE 0x00000000u
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#define PCIE_CONFIG_INTERFACE 0x00000001u
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#define CONFIG_SPACE_ADDR_OFFSET 0x1000u
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#define ATR_ENTRY_SIZE 32
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enum plda_int_event {
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@ -201,4 +215,59 @@ static inline void plda_set_default_msi(struct plda_msi *msi)
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msi->vector_phy = IMSI_ADDR;
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msi->num_vectors = PLDA_MAX_NUM_MSI_IRQS;
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}
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#endif
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static inline void plda_pcie_enable_root_port(struct plda_pcie_rp *plda)
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{
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u32 value;
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value = readl_relaxed(plda->bridge_addr + GEN_SETTINGS);
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value |= RP_ENABLE;
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writel_relaxed(value, plda->bridge_addr + GEN_SETTINGS);
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}
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static inline void plda_pcie_set_standard_class(struct plda_pcie_rp *plda)
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{
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u32 value;
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/* set class code and reserve revision id */
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value = readl_relaxed(plda->bridge_addr + PCIE_PCI_IDS_DW1);
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value &= REVISION_ID_MASK;
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value |= (PCI_CLASS_BRIDGE_PCI << IDS_CLASS_CODE_SHIFT);
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writel_relaxed(value, plda->bridge_addr + PCIE_PCI_IDS_DW1);
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}
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static inline void plda_pcie_set_pref_win_64bit(struct plda_pcie_rp *plda)
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{
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u32 value;
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value = readl_relaxed(plda->bridge_addr + PCIE_WINROM);
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value |= PREF_MEM_WIN_64_SUPPORT;
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writel_relaxed(value, plda->bridge_addr + PCIE_WINROM);
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}
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static inline void plda_pcie_disable_ltr(struct plda_pcie_rp *plda)
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{
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u32 value;
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value = readl_relaxed(plda->bridge_addr + PMSG_SUPPORT_RX);
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value &= ~PMSG_LTR_SUPPORT;
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writel_relaxed(value, plda->bridge_addr + PMSG_SUPPORT_RX);
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}
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static inline void plda_pcie_disable_func(struct plda_pcie_rp *plda)
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{
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u32 value;
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value = readl_relaxed(plda->bridge_addr + PCI_MISC);
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value |= PHY_FUNCTION_DIS;
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writel_relaxed(value, plda->bridge_addr + PCI_MISC);
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}
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static inline void plda_pcie_write_rc_bar(struct plda_pcie_rp *plda, u64 val)
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{
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void __iomem *addr = plda->bridge_addr + CONFIG_SPACE_ADDR_OFFSET;
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writel_relaxed(lower_32_bits(val), addr + PCI_BASE_ADDRESS_0);
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writel_relaxed(upper_32_bits(val), addr + PCI_BASE_ADDRESS_1);
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}
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#endif /* _PCIE_PLDA_H */
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488
drivers/pci/controller/plda/pcie-starfive.c
Normal file
488
drivers/pci/controller/plda/pcie-starfive.c
Normal file
@ -0,0 +1,488 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* PCIe host controller driver for StarFive JH7110 Soc.
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*
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* Copyright (C) 2023 StarFive Technology Co., Ltd.
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*/
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/gpio/consumer.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/of_pci.h>
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#include <linux/pci.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <linux/reset.h>
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#include "../../pci.h"
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#include "pcie-plda.h"
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#define PCIE_FUNC_NUM 4
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/* system control */
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#define STG_SYSCON_PCIE0_BASE 0x48
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#define STG_SYSCON_PCIE1_BASE 0x1f8
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#define STG_SYSCON_AR_OFFSET 0x78
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#define STG_SYSCON_AXI4_SLVL_AR_MASK GENMASK(22, 8)
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#define STG_SYSCON_AXI4_SLVL_PHY_AR(x) FIELD_PREP(GENMASK(20, 17), x)
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#define STG_SYSCON_AW_OFFSET 0x7c
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#define STG_SYSCON_AXI4_SLVL_AW_MASK GENMASK(14, 0)
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#define STG_SYSCON_AXI4_SLVL_PHY_AW(x) FIELD_PREP(GENMASK(12, 9), x)
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#define STG_SYSCON_CLKREQ BIT(22)
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#define STG_SYSCON_CKREF_SRC_MASK GENMASK(19, 18)
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#define STG_SYSCON_RP_NEP_OFFSET 0xe8
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#define STG_SYSCON_K_RP_NEP BIT(8)
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#define STG_SYSCON_LNKSTA_OFFSET 0x170
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#define DATA_LINK_ACTIVE BIT(5)
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/* Parameters for the waiting for link up routine */
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#define LINK_WAIT_MAX_RETRIES 10
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#define LINK_WAIT_USLEEP_MIN 90000
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#define LINK_WAIT_USLEEP_MAX 100000
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struct starfive_jh7110_pcie {
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struct plda_pcie_rp plda;
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struct reset_control *resets;
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struct clk_bulk_data *clks;
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struct regmap *reg_syscon;
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struct gpio_desc *power_gpio;
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struct gpio_desc *reset_gpio;
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struct phy *phy;
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unsigned int stg_pcie_base;
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int num_clks;
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};
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/*
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* JH7110 PCIe port BAR0/1 can be configured as 64-bit prefetchable memory
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* space. PCIe read and write requests targeting BAR0/1 are routed to so called
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* 'Bridge Configuration space' in PLDA IP datasheet, which contains the bridge
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* internal registers, such as interrupt, DMA and ATU registers...
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* JH7110 can access the Bridge Configuration space by local bus, and don`t
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* want the bridge internal registers accessed by the DMA from EP devices.
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* Thus, they are unimplemented and should be hidden here.
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*/
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static bool starfive_pcie_hide_rc_bar(struct pci_bus *bus, unsigned int devfn,
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int offset)
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{
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if (pci_is_root_bus(bus) && !devfn &&
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(offset == PCI_BASE_ADDRESS_0 || offset == PCI_BASE_ADDRESS_1))
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return true;
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return false;
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}
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static int starfive_pcie_config_write(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 value)
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{
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if (starfive_pcie_hide_rc_bar(bus, devfn, where))
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return PCIBIOS_SUCCESSFUL;
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return pci_generic_config_write(bus, devfn, where, size, value);
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}
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static int starfive_pcie_config_read(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 *value)
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{
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if (starfive_pcie_hide_rc_bar(bus, devfn, where)) {
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*value = 0;
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return PCIBIOS_SUCCESSFUL;
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}
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return pci_generic_config_read(bus, devfn, where, size, value);
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}
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static int starfive_pcie_parse_dt(struct starfive_jh7110_pcie *pcie,
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struct device *dev)
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{
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int domain_nr;
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pcie->num_clks = devm_clk_bulk_get_all(dev, &pcie->clks);
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if (pcie->num_clks < 0)
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return dev_err_probe(dev, pcie->num_clks,
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"failed to get pcie clocks\n");
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pcie->resets = devm_reset_control_array_get_exclusive(dev);
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if (IS_ERR(pcie->resets))
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return dev_err_probe(dev, PTR_ERR(pcie->resets),
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"failed to get pcie resets");
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pcie->reg_syscon =
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syscon_regmap_lookup_by_phandle(dev->of_node,
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"starfive,stg-syscon");
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if (IS_ERR(pcie->reg_syscon))
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return dev_err_probe(dev, PTR_ERR(pcie->reg_syscon),
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"failed to parse starfive,stg-syscon\n");
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pcie->phy = devm_phy_optional_get(dev, NULL);
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if (IS_ERR(pcie->phy))
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return dev_err_probe(dev, PTR_ERR(pcie->phy),
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"failed to get pcie phy\n");
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/*
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* The PCIe domain numbers are set to be static in JH7110 DTS.
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* As the STG system controller defines different bases in PCIe RP0 &
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* RP1, we use them to identify which controller is doing the hardware
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* initialization.
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*/
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domain_nr = of_get_pci_domain_nr(dev->of_node);
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if (domain_nr < 0 || domain_nr > 1)
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return dev_err_probe(dev, -ENODEV,
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"failed to get valid pcie domain\n");
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if (domain_nr == 0)
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pcie->stg_pcie_base = STG_SYSCON_PCIE0_BASE;
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else
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pcie->stg_pcie_base = STG_SYSCON_PCIE1_BASE;
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pcie->reset_gpio = devm_gpiod_get_optional(dev, "perst",
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GPIOD_OUT_HIGH);
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if (IS_ERR(pcie->reset_gpio))
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return dev_err_probe(dev, PTR_ERR(pcie->reset_gpio),
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"failed to get perst-gpio\n");
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pcie->power_gpio = devm_gpiod_get_optional(dev, "enable",
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GPIOD_OUT_LOW);
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if (IS_ERR(pcie->power_gpio))
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return dev_err_probe(dev, PTR_ERR(pcie->power_gpio),
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"failed to get power-gpio\n");
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return 0;
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}
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static struct pci_ops starfive_pcie_ops = {
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.map_bus = plda_pcie_map_bus,
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.read = starfive_pcie_config_read,
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.write = starfive_pcie_config_write,
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};
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static int starfive_pcie_clk_rst_init(struct starfive_jh7110_pcie *pcie)
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{
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struct device *dev = pcie->plda.dev;
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int ret;
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ret = clk_bulk_prepare_enable(pcie->num_clks, pcie->clks);
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if (ret)
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return dev_err_probe(dev, ret, "failed to enable clocks\n");
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ret = reset_control_deassert(pcie->resets);
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if (ret) {
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clk_bulk_disable_unprepare(pcie->num_clks, pcie->clks);
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dev_err_probe(dev, ret, "failed to deassert resets\n");
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}
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return ret;
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}
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static void starfive_pcie_clk_rst_deinit(struct starfive_jh7110_pcie *pcie)
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{
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reset_control_assert(pcie->resets);
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clk_bulk_disable_unprepare(pcie->num_clks, pcie->clks);
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}
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static bool starfive_pcie_link_up(struct plda_pcie_rp *plda)
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{
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struct starfive_jh7110_pcie *pcie =
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container_of(plda, struct starfive_jh7110_pcie, plda);
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int ret;
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u32 stg_reg_val;
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ret = regmap_read(pcie->reg_syscon,
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pcie->stg_pcie_base + STG_SYSCON_LNKSTA_OFFSET,
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&stg_reg_val);
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if (ret) {
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dev_err(pcie->plda.dev, "failed to read link status\n");
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return false;
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}
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return !!(stg_reg_val & DATA_LINK_ACTIVE);
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}
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static int starfive_pcie_host_wait_for_link(struct starfive_jh7110_pcie *pcie)
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{
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int retries;
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/* Check if the link is up or not */
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for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
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if (starfive_pcie_link_up(&pcie->plda)) {
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dev_info(pcie->plda.dev, "port link up\n");
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return 0;
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}
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usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
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}
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return -ETIMEDOUT;
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}
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static int starfive_pcie_enable_phy(struct device *dev,
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struct starfive_jh7110_pcie *pcie)
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{
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int ret;
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if (!pcie->phy)
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return 0;
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ret = phy_init(pcie->phy);
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if (ret)
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return dev_err_probe(dev, ret,
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"failed to initialize pcie phy\n");
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ret = phy_set_mode(pcie->phy, PHY_MODE_PCIE);
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if (ret) {
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dev_err_probe(dev, ret, "failed to set pcie mode\n");
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goto err_phy_on;
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}
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ret = phy_power_on(pcie->phy);
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if (ret) {
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dev_err_probe(dev, ret, "failed to power on pcie phy\n");
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goto err_phy_on;
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}
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return 0;
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err_phy_on:
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phy_exit(pcie->phy);
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return ret;
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}
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static void starfive_pcie_disable_phy(struct starfive_jh7110_pcie *pcie)
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{
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phy_power_off(pcie->phy);
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phy_exit(pcie->phy);
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}
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static void starfive_pcie_host_deinit(struct plda_pcie_rp *plda)
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{
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struct starfive_jh7110_pcie *pcie =
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container_of(plda, struct starfive_jh7110_pcie, plda);
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starfive_pcie_clk_rst_deinit(pcie);
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if (pcie->power_gpio)
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gpiod_set_value_cansleep(pcie->power_gpio, 0);
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starfive_pcie_disable_phy(pcie);
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}
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static int starfive_pcie_host_init(struct plda_pcie_rp *plda)
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{
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struct starfive_jh7110_pcie *pcie =
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container_of(plda, struct starfive_jh7110_pcie, plda);
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struct device *dev = plda->dev;
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||||
int ret;
|
||||
int i;
|
||||
|
||||
ret = starfive_pcie_enable_phy(dev, pcie);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
regmap_update_bits(pcie->reg_syscon,
|
||||
pcie->stg_pcie_base + STG_SYSCON_RP_NEP_OFFSET,
|
||||
STG_SYSCON_K_RP_NEP, STG_SYSCON_K_RP_NEP);
|
||||
|
||||
regmap_update_bits(pcie->reg_syscon,
|
||||
pcie->stg_pcie_base + STG_SYSCON_AW_OFFSET,
|
||||
STG_SYSCON_CKREF_SRC_MASK,
|
||||
FIELD_PREP(STG_SYSCON_CKREF_SRC_MASK, 2));
|
||||
|
||||
regmap_update_bits(pcie->reg_syscon,
|
||||
pcie->stg_pcie_base + STG_SYSCON_AW_OFFSET,
|
||||
STG_SYSCON_CLKREQ, STG_SYSCON_CLKREQ);
|
||||
|
||||
ret = starfive_pcie_clk_rst_init(pcie);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (pcie->power_gpio)
|
||||
gpiod_set_value_cansleep(pcie->power_gpio, 1);
|
||||
|
||||
if (pcie->reset_gpio)
|
||||
gpiod_set_value_cansleep(pcie->reset_gpio, 1);
|
||||
|
||||
/* Disable physical functions except #0 */
|
||||
for (i = 1; i < PCIE_FUNC_NUM; i++) {
|
||||
regmap_update_bits(pcie->reg_syscon,
|
||||
pcie->stg_pcie_base + STG_SYSCON_AR_OFFSET,
|
||||
STG_SYSCON_AXI4_SLVL_AR_MASK,
|
||||
STG_SYSCON_AXI4_SLVL_PHY_AR(i));
|
||||
|
||||
regmap_update_bits(pcie->reg_syscon,
|
||||
pcie->stg_pcie_base + STG_SYSCON_AW_OFFSET,
|
||||
STG_SYSCON_AXI4_SLVL_AW_MASK,
|
||||
STG_SYSCON_AXI4_SLVL_PHY_AW(i));
|
||||
|
||||
plda_pcie_disable_func(plda);
|
||||
}
|
||||
|
||||
regmap_update_bits(pcie->reg_syscon,
|
||||
pcie->stg_pcie_base + STG_SYSCON_AR_OFFSET,
|
||||
STG_SYSCON_AXI4_SLVL_AR_MASK, 0);
|
||||
regmap_update_bits(pcie->reg_syscon,
|
||||
pcie->stg_pcie_base + STG_SYSCON_AW_OFFSET,
|
||||
STG_SYSCON_AXI4_SLVL_AW_MASK, 0);
|
||||
|
||||
plda_pcie_enable_root_port(plda);
|
||||
plda_pcie_write_rc_bar(plda, 0);
|
||||
|
||||
/* PCIe PCI Standard Configuration Identification Settings. */
|
||||
plda_pcie_set_standard_class(plda);
|
||||
|
||||
/*
|
||||
* The LTR message receiving is enabled by the register "PCIe Message
|
||||
* Reception" as default, but the forward id & addr are uninitialized.
|
||||
* If we do not disable LTR message forwarding here, or set a legal
|
||||
* forwarding address, the kernel will get stuck.
|
||||
* To workaround, disable the LTR message forwarding here before using
|
||||
* this feature.
|
||||
*/
|
||||
plda_pcie_disable_ltr(plda);
|
||||
|
||||
/*
|
||||
* Enable the prefetchable memory window 64-bit addressing in JH7110.
|
||||
* The 64-bits prefetchable address translation configurations in ATU
|
||||
* can be work after enable the register setting below.
|
||||
*/
|
||||
plda_pcie_set_pref_win_64bit(plda);
|
||||
|
||||
/*
|
||||
* Ensure that PERST has been asserted for at least 100 ms,
|
||||
* the sleep value is T_PVPERL from PCIe CEM spec r2.0 (Table 2-4)
|
||||
*/
|
||||
msleep(100);
|
||||
if (pcie->reset_gpio)
|
||||
gpiod_set_value_cansleep(pcie->reset_gpio, 0);
|
||||
|
||||
/*
|
||||
* With a Downstream Port (<=5GT/s), software must wait a minimum
|
||||
* of 100ms following exit from a conventional reset before
|
||||
* sending a configuration request to the device.
|
||||
*/
|
||||
msleep(PCIE_RESET_CONFIG_DEVICE_WAIT_MS);
|
||||
|
||||
if (starfive_pcie_host_wait_for_link(pcie))
|
||||
dev_info(dev, "port link down\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct plda_pcie_host_ops sf_host_ops = {
|
||||
.host_init = starfive_pcie_host_init,
|
||||
.host_deinit = starfive_pcie_host_deinit,
|
||||
};
|
||||
|
||||
static const struct plda_event stf_pcie_event = {
|
||||
.intx_event = EVENT_PM_MSI_INT_INTX,
|
||||
.msi_event = EVENT_PM_MSI_INT_MSI
|
||||
};
|
||||
|
||||
static int starfive_pcie_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct starfive_jh7110_pcie *pcie;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct plda_pcie_rp *plda;
|
||||
int ret;
|
||||
|
||||
pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
|
||||
if (!pcie)
|
||||
return -ENOMEM;
|
||||
|
||||
plda = &pcie->plda;
|
||||
plda->dev = dev;
|
||||
|
||||
ret = starfive_pcie_parse_dt(pcie, dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
plda->host_ops = &sf_host_ops;
|
||||
plda->num_events = PLDA_MAX_EVENT_NUM;
|
||||
/* mask doorbell event */
|
||||
plda->events_bitmap = GENMASK(PLDA_INT_EVENT_NUM - 1, 0)
|
||||
& ~BIT(PLDA_AXI_DOORBELL)
|
||||
& ~BIT(PLDA_PCIE_DOORBELL);
|
||||
plda->events_bitmap <<= PLDA_NUM_DMA_EVENTS;
|
||||
ret = plda_pcie_host_init(&pcie->plda, &starfive_pcie_ops,
|
||||
&stf_pcie_event);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
pm_runtime_enable(&pdev->dev);
|
||||
pm_runtime_get_sync(&pdev->dev);
|
||||
platform_set_drvdata(pdev, pcie);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void starfive_pcie_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct starfive_jh7110_pcie *pcie = platform_get_drvdata(pdev);
|
||||
|
||||
pm_runtime_put(&pdev->dev);
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
plda_pcie_host_deinit(&pcie->plda);
|
||||
platform_set_drvdata(pdev, NULL);
|
||||
}
|
||||
|
||||
static int starfive_pcie_suspend_noirq(struct device *dev)
|
||||
{
|
||||
struct starfive_jh7110_pcie *pcie = dev_get_drvdata(dev);
|
||||
|
||||
clk_bulk_disable_unprepare(pcie->num_clks, pcie->clks);
|
||||
starfive_pcie_disable_phy(pcie);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int starfive_pcie_resume_noirq(struct device *dev)
|
||||
{
|
||||
struct starfive_jh7110_pcie *pcie = dev_get_drvdata(dev);
|
||||
int ret;
|
||||
|
||||
ret = starfive_pcie_enable_phy(dev, pcie);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = clk_bulk_prepare_enable(pcie->num_clks, pcie->clks);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to enable clocks\n");
|
||||
starfive_pcie_disable_phy(pcie);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct dev_pm_ops starfive_pcie_pm_ops = {
|
||||
NOIRQ_SYSTEM_SLEEP_PM_OPS(starfive_pcie_suspend_noirq,
|
||||
starfive_pcie_resume_noirq)
|
||||
};
|
||||
|
||||
static const struct of_device_id starfive_pcie_of_match[] = {
|
||||
{ .compatible = "starfive,jh7110-pcie", },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, starfive_pcie_of_match);
|
||||
|
||||
static struct platform_driver starfive_pcie_driver = {
|
||||
.driver = {
|
||||
.name = "pcie-starfive",
|
||||
.of_match_table = of_match_ptr(starfive_pcie_of_match),
|
||||
.pm = pm_sleep_ptr(&starfive_pcie_pm_ops),
|
||||
},
|
||||
.probe = starfive_pcie_probe,
|
||||
.remove_new = starfive_pcie_remove,
|
||||
};
|
||||
module_platform_driver(starfive_pcie_driver);
|
||||
|
||||
MODULE_DESCRIPTION("StarFive JH7110 PCIe host driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
Loading…
Reference in New Issue
Block a user