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drm/radeon/dpm: add smc fan control for SI (v2)
Enable smc fan control for SI boards. Should reduce the fan noise on systems with a higher default fan profile. v2: disable by default, add rpm controls bug: https://bugs.freedesktop.org/show_bug.cgi?id=73338 Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher
parent
4bb62c95a7
commit
39471ad39d
@ -56,6 +56,9 @@
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#define PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE 0x20
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#define PPSMC_STATEFLAG_DEEPSLEEP_BYPASS 0x40
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#define FDO_MODE_HARDWARE 0
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#define FDO_MODE_PIECE_WISE_LINEAR 1
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#define PPSMC_Result_OK ((uint8_t)0x01)
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#define PPSMC_Result_Failed ((uint8_t)0xFF)
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@ -79,6 +82,8 @@ typedef uint8_t PPSMC_Result;
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#define PPSMC_MSG_DisableCac ((uint8_t)0x54)
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#define PPSMC_TDPClampingActive ((uint8_t)0x59)
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#define PPSMC_TDPClampingInactive ((uint8_t)0x5A)
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#define PPSMC_StartFanControl ((uint8_t)0x5B)
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#define PPSMC_StopFanControl ((uint8_t)0x5C)
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#define PPSMC_MSG_NoDisplay ((uint8_t)0x5D)
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#define PPSMC_MSG_HasDisplay ((uint8_t)0x5E)
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#define PPSMC_MSG_UVDPowerOFF ((uint8_t)0x60)
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@ -96,6 +96,9 @@
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#define R600_TEMP_RANGE_MIN (90 * 1000)
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#define R600_TEMP_RANGE_MAX (120 * 1000)
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#define FDO_PWM_MODE_STATIC 1
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#define FDO_PWM_MODE_STATIC_RPM 5
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enum r600_power_level {
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R600_POWER_LEVEL_LOW = 0,
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R600_POWER_LEVEL_MEDIUM = 1,
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@ -3396,6 +3396,15 @@ static int si_process_firmware_header(struct radeon_device *rdev)
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si_pi->mc_reg_table_start = tmp;
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ret = si_read_smc_sram_dword(rdev,
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SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
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SISLANDS_SMC_FIRMWARE_HEADER_fanTable,
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&tmp, si_pi->sram_end);
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if (ret)
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return ret;
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si_pi->fan_table_start = tmp;
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ret = si_read_smc_sram_dword(rdev,
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SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
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SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable,
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@ -5825,20 +5834,20 @@ static int si_thermal_enable_alert(struct radeon_device *rdev,
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if (enable) {
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PPSMC_Result result;
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thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
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rdev->irq.dpm_thermal = true;
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thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
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WREG32(CG_THERMAL_INT, thermal_int);
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rdev->irq.dpm_thermal = false;
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result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
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if (result != PPSMC_Result_OK) {
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DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
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return -EINVAL;
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}
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} else {
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thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
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rdev->irq.dpm_thermal = false;
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thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
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WREG32(CG_THERMAL_INT, thermal_int);
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rdev->irq.dpm_thermal = true;
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}
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WREG32(CG_THERMAL_INT, thermal_int);
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return 0;
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}
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@ -5867,6 +5876,309 @@ static int si_thermal_set_temperature_range(struct radeon_device *rdev,
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return 0;
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}
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static void si_fan_ctrl_set_static_mode(struct radeon_device *rdev, u32 mode)
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{
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struct si_power_info *si_pi = si_get_pi(rdev);
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u32 tmp;
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if (si_pi->fan_ctrl_is_in_default_mode) {
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tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT;
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si_pi->fan_ctrl_default_mode = tmp;
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tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT;
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si_pi->t_min = tmp;
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si_pi->fan_ctrl_is_in_default_mode = false;
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}
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tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
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tmp |= TMIN(0);
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WREG32(CG_FDO_CTRL2, tmp);
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tmp = RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK;
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tmp |= FDO_PWM_MODE(mode);
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WREG32(CG_FDO_CTRL2, tmp);
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}
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static int si_thermal_setup_fan_table(struct radeon_device *rdev)
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{
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struct si_power_info *si_pi = si_get_pi(rdev);
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PP_SIslands_FanTable fan_table = { FDO_MODE_HARDWARE };
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u32 duty100;
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u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2;
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u16 fdo_min, slope1, slope2;
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u32 reference_clock, tmp;
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int ret;
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u64 tmp64;
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if (!si_pi->fan_table_start) {
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rdev->pm.dpm.fan.ucode_fan_control = false;
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return 0;
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}
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duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
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if (duty100 == 0) {
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rdev->pm.dpm.fan.ucode_fan_control = false;
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return 0;
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}
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tmp64 = (u64)rdev->pm.dpm.fan.pwm_min * duty100;
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do_div(tmp64, 10000);
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fdo_min = (u16)tmp64;
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t_diff1 = rdev->pm.dpm.fan.t_med - rdev->pm.dpm.fan.t_min;
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t_diff2 = rdev->pm.dpm.fan.t_high - rdev->pm.dpm.fan.t_med;
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pwm_diff1 = rdev->pm.dpm.fan.pwm_med - rdev->pm.dpm.fan.pwm_min;
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pwm_diff2 = rdev->pm.dpm.fan.pwm_high - rdev->pm.dpm.fan.pwm_med;
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slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
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slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
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fan_table.slope1 = cpu_to_be16(slope1);
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fan_table.slope2 = cpu_to_be16(slope2);
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fan_table.fdo_min = cpu_to_be16(fdo_min);
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fan_table.hys_down = cpu_to_be16(rdev->pm.dpm.fan.t_hyst);
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fan_table.hys_up = cpu_to_be16(1);
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fan_table.hys_slope = cpu_to_be16(1);
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fan_table.temp_resp_lim = cpu_to_be16(5);
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reference_clock = radeon_get_xclk(rdev);
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fan_table.refresh_period = cpu_to_be32((rdev->pm.dpm.fan.cycle_delay *
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reference_clock) / 1600);
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fan_table.fdo_max = cpu_to_be16((u16)duty100);
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tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT;
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fan_table.temp_src = (uint8_t)tmp;
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ret = si_copy_bytes_to_smc(rdev,
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si_pi->fan_table_start,
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(u8 *)(&fan_table),
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sizeof(fan_table),
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si_pi->sram_end);
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if (ret) {
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DRM_ERROR("Failed to load fan table to the SMC.");
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rdev->pm.dpm.fan.ucode_fan_control = false;
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}
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return 0;
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}
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static int si_fan_ctrl_start_smc_fan_control(struct radeon_device *rdev)
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{
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PPSMC_Result ret;
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ret = si_send_msg_to_smc(rdev, PPSMC_StartFanControl);
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if (ret == PPSMC_Result_OK)
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return 0;
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else
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return -EINVAL;
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}
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static int si_fan_ctrl_stop_smc_fan_control(struct radeon_device *rdev)
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{
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PPSMC_Result ret;
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ret = si_send_msg_to_smc(rdev, PPSMC_StopFanControl);
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if (ret == PPSMC_Result_OK)
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return 0;
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else
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return -EINVAL;
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}
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#if 0
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static int si_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev,
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u32 *speed)
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{
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u32 duty, duty100;
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u64 tmp64;
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if (rdev->pm.no_fan)
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return -ENOENT;
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duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
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duty = (RREG32(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT;
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if (duty100 == 0)
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return -EINVAL;
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tmp64 = (u64)duty * 100;
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do_div(tmp64, duty100);
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*speed = (u32)tmp64;
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if (*speed > 100)
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*speed = 100;
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return 0;
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}
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static int si_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev,
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u32 speed)
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{
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u32 tmp;
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u32 duty, duty100;
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u64 tmp64;
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if (rdev->pm.no_fan)
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return -ENOENT;
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if (speed > 100)
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return -EINVAL;
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if (rdev->pm.dpm.fan.ucode_fan_control)
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si_fan_ctrl_stop_smc_fan_control(rdev);
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duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
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if (duty100 == 0)
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return -EINVAL;
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tmp64 = (u64)speed * duty100;
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do_div(tmp64, 100);
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duty = (u32)tmp64;
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tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK;
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tmp |= FDO_STATIC_DUTY(duty);
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WREG32(CG_FDO_CTRL0, tmp);
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si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC);
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return 0;
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}
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static int si_fan_ctrl_get_fan_speed_rpm(struct radeon_device *rdev,
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u32 *speed)
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{
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u32 tach_period;
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u32 xclk = radeon_get_xclk(rdev);
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if (rdev->pm.no_fan)
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return -ENOENT;
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if (rdev->pm.fan_pulses_per_revolution == 0)
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return -ENOENT;
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tach_period = (RREG32(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT;
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if (tach_period == 0)
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return -ENOENT;
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*speed = 60 * xclk * 10000 / tach_period;
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return 0;
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}
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static int si_fan_ctrl_set_fan_speed_rpm(struct radeon_device *rdev,
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u32 speed)
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{
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u32 tach_period, tmp;
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u32 xclk = radeon_get_xclk(rdev);
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if (rdev->pm.no_fan)
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return -ENOENT;
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if (rdev->pm.fan_pulses_per_revolution == 0)
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return -ENOENT;
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if ((speed < rdev->pm.fan_min_rpm) ||
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(speed > rdev->pm.fan_max_rpm))
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return -EINVAL;
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if (rdev->pm.dpm.fan.ucode_fan_control)
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si_fan_ctrl_stop_smc_fan_control(rdev);
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tach_period = 60 * xclk * 10000 / (8 * speed);
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tmp = RREG32(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK;
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tmp |= TARGET_PERIOD(tach_period);
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WREG32(CG_TACH_CTRL, tmp);
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si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC);
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return 0;
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}
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#endif
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static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev)
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{
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struct si_power_info *si_pi = si_get_pi(rdev);
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u32 tmp;
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if (!si_pi->fan_ctrl_is_in_default_mode) {
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tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
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tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode);
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WREG32(CG_FDO_CTRL2, tmp);
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tmp = RREG32(CG_FDO_CTRL2) & TMIN_MASK;
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tmp |= TMIN(si_pi->t_min);
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WREG32(CG_FDO_CTRL2, tmp);
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si_pi->fan_ctrl_is_in_default_mode = true;
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}
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}
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static void si_thermal_start_smc_fan_control(struct radeon_device *rdev)
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{
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if (rdev->pm.dpm.fan.ucode_fan_control) {
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si_fan_ctrl_start_smc_fan_control(rdev);
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si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC);
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}
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}
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static void si_thermal_initialize(struct radeon_device *rdev)
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{
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u32 tmp;
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if (rdev->pm.fan_pulses_per_revolution) {
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tmp = RREG32(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK;
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tmp |= EDGE_PER_REV(rdev->pm.fan_pulses_per_revolution -1);
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WREG32(CG_TACH_CTRL, tmp);
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}
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tmp = RREG32(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK;
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tmp |= TACH_PWM_RESP_RATE(0x28);
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WREG32(CG_FDO_CTRL2, tmp);
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}
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static int si_thermal_start_thermal_controller(struct radeon_device *rdev)
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{
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int ret;
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si_thermal_initialize(rdev);
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ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
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if (ret)
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return ret;
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ret = si_thermal_enable_alert(rdev, true);
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if (ret)
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return ret;
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if (rdev->pm.dpm.fan.ucode_fan_control) {
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ret = si_halt_smc(rdev);
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if (ret)
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return ret;
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ret = si_thermal_setup_fan_table(rdev);
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if (ret)
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return ret;
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ret = si_resume_smc(rdev);
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if (ret)
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return ret;
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si_thermal_start_smc_fan_control(rdev);
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}
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return 0;
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}
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static void si_thermal_stop_thermal_controller(struct radeon_device *rdev)
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{
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if (!rdev->pm.no_fan) {
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si_fan_ctrl_set_default_mode(rdev);
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si_fan_ctrl_stop_smc_fan_control(rdev);
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}
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}
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int si_dpm_enable(struct radeon_device *rdev)
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{
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struct rv7xx_power_info *pi = rv770_get_pi(rdev);
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@ -5979,6 +6291,8 @@ int si_dpm_enable(struct radeon_device *rdev)
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si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
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si_thermal_start_thermal_controller(rdev);
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ni_update_current_ps(rdev, boot_ps);
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return 0;
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@ -6019,6 +6333,7 @@ void si_dpm_disable(struct radeon_device *rdev)
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if (!si_is_smc_running(rdev))
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return;
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si_thermal_stop_thermal_controller(rdev);
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si_disable_ulv(rdev);
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si_clear_vc(rdev);
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if (pi->thermal_protection)
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@ -6557,6 +6872,9 @@ int si_dpm_init(struct radeon_device *rdev)
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rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
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rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
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si_pi->fan_ctrl_is_in_default_mode = true;
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rdev->pm.dpm.fan.ucode_fan_control = false;
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return 0;
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}
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@ -182,6 +182,7 @@ struct si_power_info {
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u32 dte_table_start;
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u32 spll_table_start;
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u32 papm_cfg_table_start;
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u32 fan_table_start;
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/* CAC stuff */
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const struct si_cac_config_reg *cac_weights;
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const struct si_cac_config_reg *lcac_config;
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@ -197,6 +198,10 @@ struct si_power_info {
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/* SVI2 */
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u8 svd_gpio_id;
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u8 svc_gpio_id;
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/* fan control */
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bool fan_ctrl_is_in_default_mode;
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u32 t_min;
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u32 fan_ctrl_default_mode;
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};
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||||
#define SISLANDS_INITIAL_STATE_ARB_INDEX 0
|
||||
|
||||
@ -180,7 +180,10 @@
|
||||
#define DIG_THERM_DPM(x) ((x) << 14)
|
||||
#define DIG_THERM_DPM_MASK 0x003FC000
|
||||
#define DIG_THERM_DPM_SHIFT 14
|
||||
|
||||
#define CG_THERMAL_STATUS 0x704
|
||||
#define FDO_PWM_DUTY(x) ((x) << 9)
|
||||
#define FDO_PWM_DUTY_MASK (0xff << 9)
|
||||
#define FDO_PWM_DUTY_SHIFT 9
|
||||
#define CG_THERMAL_INT 0x708
|
||||
#define DIG_THERM_INTH(x) ((x) << 8)
|
||||
#define DIG_THERM_INTH_MASK 0x0000FF00
|
||||
@ -191,6 +194,10 @@
|
||||
#define THERM_INT_MASK_HIGH (1 << 24)
|
||||
#define THERM_INT_MASK_LOW (1 << 25)
|
||||
|
||||
#define CG_MULT_THERMAL_CTRL 0x710
|
||||
#define TEMP_SEL(x) ((x) << 20)
|
||||
#define TEMP_SEL_MASK (0xff << 20)
|
||||
#define TEMP_SEL_SHIFT 20
|
||||
#define CG_MULT_THERMAL_STATUS 0x714
|
||||
#define ASIC_MAX_TEMP(x) ((x) << 0)
|
||||
#define ASIC_MAX_TEMP_MASK 0x000001ff
|
||||
@ -199,6 +206,37 @@
|
||||
#define CTF_TEMP_MASK 0x0003fe00
|
||||
#define CTF_TEMP_SHIFT 9
|
||||
|
||||
#define CG_FDO_CTRL0 0x754
|
||||
#define FDO_STATIC_DUTY(x) ((x) << 0)
|
||||
#define FDO_STATIC_DUTY_MASK 0x0000000F
|
||||
#define FDO_STATIC_DUTY_SHIFT 0
|
||||
#define CG_FDO_CTRL1 0x758
|
||||
#define FMAX_DUTY100(x) ((x) << 0)
|
||||
#define FMAX_DUTY100_MASK 0x0000000F
|
||||
#define FMAX_DUTY100_SHIFT 0
|
||||
#define CG_FDO_CTRL2 0x75C
|
||||
#define TMIN(x) ((x) << 0)
|
||||
#define TMIN_MASK 0x0000000F
|
||||
#define TMIN_SHIFT 0
|
||||
#define FDO_PWM_MODE(x) ((x) << 11)
|
||||
#define FDO_PWM_MODE_MASK (3 << 11)
|
||||
#define FDO_PWM_MODE_SHIFT 11
|
||||
#define TACH_PWM_RESP_RATE(x) ((x) << 25)
|
||||
#define TACH_PWM_RESP_RATE_MASK (0x7f << 25)
|
||||
#define TACH_PWM_RESP_RATE_SHIFT 25
|
||||
|
||||
#define CG_TACH_CTRL 0x770
|
||||
# define EDGE_PER_REV(x) ((x) << 0)
|
||||
# define EDGE_PER_REV_MASK (0x7 << 0)
|
||||
# define EDGE_PER_REV_SHIFT 0
|
||||
# define TARGET_PERIOD(x) ((x) << 3)
|
||||
# define TARGET_PERIOD_MASK 0xfffffff8
|
||||
# define TARGET_PERIOD_SHIFT 3
|
||||
#define CG_TACH_STATUS 0x774
|
||||
# define TACH_PERIOD(x) ((x) << 0)
|
||||
# define TACH_PERIOD_MASK 0xffffffff
|
||||
# define TACH_PERIOD_SHIFT 0
|
||||
|
||||
#define GENERAL_PWRMGT 0x780
|
||||
# define GLOBAL_PWRMGT_EN (1 << 0)
|
||||
# define STATIC_PM_EN (1 << 1)
|
||||
|
||||
@ -245,6 +245,31 @@ typedef struct SISLANDS_SMC_STATETABLE SISLANDS_SMC_STATETABLE;
|
||||
#define SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd 0x11c
|
||||
#define SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc 0x120
|
||||
|
||||
struct PP_SIslands_FanTable
|
||||
{
|
||||
uint8_t fdo_mode;
|
||||
uint8_t padding;
|
||||
int16_t temp_min;
|
||||
int16_t temp_med;
|
||||
int16_t temp_max;
|
||||
int16_t slope1;
|
||||
int16_t slope2;
|
||||
int16_t fdo_min;
|
||||
int16_t hys_up;
|
||||
int16_t hys_down;
|
||||
int16_t hys_slope;
|
||||
int16_t temp_resp_lim;
|
||||
int16_t temp_curr;
|
||||
int16_t slope_curr;
|
||||
int16_t pwm_curr;
|
||||
uint32_t refresh_period;
|
||||
int16_t fdo_max;
|
||||
uint8_t temp_src;
|
||||
int8_t padding2;
|
||||
};
|
||||
|
||||
typedef struct PP_SIslands_FanTable PP_SIslands_FanTable;
|
||||
|
||||
#define SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES 16
|
||||
#define SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES 32
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user