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ARM: 5791/1: ARM: MM: use 64bytes of L1 cache on plat S5PC1xx

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Samsung S5PC1xx SoCs are based on ARM Coretex8, which has 64 bytes of L1
cache line size. Enable proper handling of L1 cache on these SoCs.

Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Marek Szyprowski 2009-11-19 11:30:30 +01:00 committed by Russell King
parent b43149c168
commit 394168389c
1 changed files with 1 additions and 1 deletions
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arch/arm/mm/Kconfig
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@ -777,5 +777,5 @@ config CACHE_XSC3L2
config ARM_L1_CACHE_SHIFT
int
default 6 if ARCH_OMAP3
default 6 if ARCH_OMAP3 || ARCH_S5PC1XX
default 5