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x86/KVM/VMX: Use MSR save list for IA32_FLUSH_CMD if required
If the L1D flush module parameter is set to 'always' and the IA32_FLUSH_CMD MSR is available, optimize the VMENTER code with the MSR save list. Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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@ -6237,6 +6237,16 @@ static void ept_set_mmio_spte_mask(void)
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VMX_EPT_MISCONFIG_WX_VALUE);
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}
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static bool vmx_l1d_use_msr_save_list(void)
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{
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if (!enable_ept || !boot_cpu_has_bug(X86_BUG_L1TF) ||
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static_cpu_has(X86_FEATURE_HYPERVISOR) ||
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!static_cpu_has(X86_FEATURE_FLUSH_L1D))
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return false;
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return vmentry_l1d_flush == VMENTER_L1D_FLUSH_ALWAYS;
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}
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#define VMX_XSS_EXIT_BITMAP 0
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/*
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* Sets up the vmcs for emulated real mode.
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@ -6358,6 +6368,12 @@ static void vmx_vcpu_setup(struct vcpu_vmx *vmx)
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vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
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vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
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}
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/*
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* If flushing the L1D cache on every VMENTER is enforced and the
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* MSR is available, use the MSR save list.
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*/
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if (vmx_l1d_use_msr_save_list())
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add_atomic_switch_msr(vmx, MSR_IA32_FLUSH_CMD, L1D_FLUSH, 0, true);
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}
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static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
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@ -9607,11 +9623,26 @@ static void vmx_l1d_flush(struct kvm_vcpu *vcpu)
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bool always;
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/*
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* If the mitigation mode is 'flush always', keep the flush bit
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* set, otherwise clear it. It gets set again either from
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* vcpu_run() or from one of the unsafe VMEXIT handlers.
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* This code is only executed when:
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* - the flush mode is 'cond'
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* - the flush mode is 'always' and the flush MSR is not
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* available
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*
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* If the CPU has the flush MSR then clear the flush bit because
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* 'always' mode is handled via the MSR save list.
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*
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* If the MSR is not avaibable then act depending on the mitigation
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* mode: If 'flush always', keep the flush bit set, otherwise clear
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* it.
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*
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* The flush bit gets set again either from vcpu_run() or from one
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* of the unsafe VMEXIT handlers.
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*/
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always = vmentry_l1d_flush == VMENTER_L1D_FLUSH_ALWAYS;
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if (static_cpu_has(X86_FEATURE_FLUSH_L1D))
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always = false;
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else
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always = vmentry_l1d_flush == VMENTER_L1D_FLUSH_ALWAYS;
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vcpu->arch.l1tf_flush_l1d = always;
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vcpu->stat.l1d_flush++;
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@ -13205,7 +13236,8 @@ static int __init vmx_setup_l1d_flush(void)
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struct page *page;
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if (vmentry_l1d_flush == VMENTER_L1D_FLUSH_NEVER ||
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!boot_cpu_has_bug(X86_BUG_L1TF))
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!boot_cpu_has_bug(X86_BUG_L1TF) ||
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vmx_l1d_use_msr_save_list())
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return 0;
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if (!boot_cpu_has(X86_FEATURE_FLUSH_L1D)) {
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