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gpio-pch: Support interrupt function
Signed-off-by: Tomoya MORINAGA <tomoya-linux@dsn.okisemi.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
This commit is contained in:
Tomoya MORINAGA
Grant Likely
parent
e98bed7f0f
commit
38eb18a6f9
@ -388,6 +388,7 @@ config GPIO_LANGWELL
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config GPIO_PCH
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tristate "Intel EG20T PCH / OKI SEMICONDUCTOR ML7223 IOH GPIO"
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depends on PCI && X86
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select GENERIC_IRQ_CHIP
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help
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This driver is for PCH(Platform controller Hub) GPIO of Intel Topcliff
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which is an IOH(Input/Output Hub) for x86 embedded processor.
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@ -17,6 +17,17 @@
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/gpio.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#define PCH_EDGE_FALLING 0
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#define PCH_EDGE_RISING BIT(0)
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#define PCH_LEVEL_L BIT(1)
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#define PCH_LEVEL_H (BIT(0) | BIT(1))
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#define PCH_EDGE_BOTH BIT(2)
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#define PCH_IM_MASK (BIT(0) | BIT(1) | BIT(2))
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#define PCH_IRQ_BASE 24
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struct pch_regs {
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u32 ien;
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@ -50,6 +61,8 @@ static int gpio_pins[] = {
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/**
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* struct pch_gpio_reg_data - The register store data.
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* @ien_reg: To store contents of IEN register.
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* @imask_reg: To store contents of IMASK register.
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* @po_reg: To store contents of PO register.
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* @pm_reg: To store contents of PM register.
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* @im0_reg: To store contents of IM0 register.
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@ -58,6 +71,8 @@ static int gpio_pins[] = {
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* (Only ML7223 Bus-n)
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*/
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struct pch_gpio_reg_data {
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u32 ien_reg;
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u32 imask_reg;
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u32 po_reg;
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u32 pm_reg;
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u32 im0_reg;
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@ -73,6 +88,8 @@ struct pch_gpio_reg_data {
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* @gpio: Data for GPIO infrastructure.
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* @pch_gpio_reg: Memory mapped Register data is saved here
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* when suspend.
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* @lock: Used for register access protection
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* @irq_base: Save base of IRQ number for interrupt
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* @ioh: IOH ID
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* @spinlock: Used for register access protection in
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* interrupt context pch_irq_mask,
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@ -85,6 +102,7 @@ struct pch_gpio {
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struct gpio_chip gpio;
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struct pch_gpio_reg_data pch_gpio_reg;
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struct mutex lock;
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int irq_base;
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enum pch_type_t ioh;
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spinlock_t spinlock;
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};
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@ -155,6 +173,8 @@ static int pch_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
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*/
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static void pch_gpio_save_reg_conf(struct pch_gpio *chip)
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{
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chip->pch_gpio_reg.ien_reg = ioread32(&chip->reg->ien);
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chip->pch_gpio_reg.imask_reg = ioread32(&chip->reg->imask);
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chip->pch_gpio_reg.po_reg = ioread32(&chip->reg->po);
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chip->pch_gpio_reg.pm_reg = ioread32(&chip->reg->pm);
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chip->pch_gpio_reg.im0_reg = ioread32(&chip->reg->im0);
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@ -170,6 +190,8 @@ static void pch_gpio_save_reg_conf(struct pch_gpio *chip)
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*/
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static void pch_gpio_restore_reg_conf(struct pch_gpio *chip)
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{
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iowrite32(chip->pch_gpio_reg.ien_reg, &chip->reg->ien);
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iowrite32(chip->pch_gpio_reg.imask_reg, &chip->reg->imask);
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/* to store contents of PO register */
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iowrite32(chip->pch_gpio_reg.po_reg, &chip->reg->po);
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/* to store contents of PM register */
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@ -182,6 +204,12 @@ static void pch_gpio_restore_reg_conf(struct pch_gpio *chip)
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&chip->reg->gpio_use_sel);
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}
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static int pch_gpio_to_irq(struct gpio_chip *gpio, unsigned offset)
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{
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struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
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return chip->irq_base + offset;
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}
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static void pch_gpio_setup(struct pch_gpio *chip)
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{
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struct gpio_chip *gpio = &chip->gpio;
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@ -196,6 +224,130 @@ static void pch_gpio_setup(struct pch_gpio *chip)
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gpio->base = -1;
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gpio->ngpio = gpio_pins[chip->ioh];
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gpio->can_sleep = 0;
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gpio->to_irq = pch_gpio_to_irq;
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}
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static int pch_irq_type(struct irq_data *d, unsigned int type)
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{
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u32 im;
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u32 *im_reg;
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u32 ien;
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u32 im_pos;
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int ch;
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unsigned long flags;
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u32 val;
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int irq = d->irq;
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct pch_gpio *chip = gc->private;
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ch = irq - chip->irq_base;
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if (irq <= chip->irq_base + 7) {
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im_reg = &chip->reg->im0;
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im_pos = ch;
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} else {
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im_reg = &chip->reg->im1;
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im_pos = ch - 8;
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}
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dev_dbg(chip->dev, "%s:irq=%d type=%d ch=%d pos=%d\n",
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__func__, irq, type, ch, im_pos);
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spin_lock_irqsave(&chip->spinlock, flags);
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switch (type) {
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case IRQ_TYPE_EDGE_RISING:
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val = PCH_EDGE_RISING;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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val = PCH_EDGE_FALLING;
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break;
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case IRQ_TYPE_EDGE_BOTH:
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val = PCH_EDGE_BOTH;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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val = PCH_LEVEL_H;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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val = PCH_LEVEL_L;
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break;
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case IRQ_TYPE_PROBE:
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goto end;
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default:
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dev_warn(chip->dev, "%s: unknown type(%dd)",
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__func__, type);
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goto end;
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}
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/* Set interrupt mode */
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im = ioread32(im_reg) & ~(PCH_IM_MASK << (im_pos * 4));
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iowrite32(im | (val << (im_pos * 4)), im_reg);
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/* iclr */
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iowrite32(BIT(ch), &chip->reg->iclr);
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/* IMASKCLR */
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iowrite32(BIT(ch), &chip->reg->imaskclr);
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/* Enable interrupt */
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ien = ioread32(&chip->reg->ien);
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iowrite32(ien | BIT(ch), &chip->reg->ien);
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end:
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spin_unlock_irqrestore(&chip->spinlock, flags);
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return 0;
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}
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static void pch_irq_unmask(struct irq_data *d)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct pch_gpio *chip = gc->private;
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iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->imaskclr);
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}
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static void pch_irq_mask(struct irq_data *d)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct pch_gpio *chip = gc->private;
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iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->imask);
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}
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static irqreturn_t pch_gpio_handler(int irq, void *dev_id)
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{
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struct pch_gpio *chip = dev_id;
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u32 reg_val = ioread32(&chip->reg->istatus);
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int i;
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int ret = IRQ_NONE;
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for (i = 0; i < gpio_pins[chip->ioh]; i++) {
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if (reg_val & BIT(i)) {
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dev_dbg(chip->dev, "%s:[%d]:irq=%d status=0x%x\n",
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__func__, i, irq, reg_val);
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iowrite32(BIT(i), &chip->reg->iclr);
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generic_handle_irq(chip->irq_base + i);
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ret = IRQ_HANDLED;
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}
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}
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return ret;
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}
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static __devinit void pch_gpio_alloc_generic_chip(struct pch_gpio *chip,
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unsigned int irq_start, unsigned int num)
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{
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struct irq_chip_generic *gc;
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struct irq_chip_type *ct;
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gc = irq_alloc_generic_chip("pch_gpio", 1, irq_start, chip->base,
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handle_simple_irq);
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gc->private = chip;
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ct = gc->chip_types;
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ct->chip.irq_mask = pch_irq_mask;
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ct->chip.irq_unmask = pch_irq_unmask;
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ct->chip.irq_set_type = pch_irq_type;
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irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
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IRQ_NOREQUEST | IRQ_NOPROBE, 0);
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}
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static int __devinit pch_gpio_probe(struct pci_dev *pdev,
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@ -203,6 +355,7 @@ static int __devinit pch_gpio_probe(struct pci_dev *pdev,
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{
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s32 ret;
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struct pch_gpio *chip;
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int irq_base;
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chip = kzalloc(sizeof(*chip), GFP_KERNEL);
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if (chip == NULL)
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@ -245,8 +398,36 @@ static int __devinit pch_gpio_probe(struct pci_dev *pdev,
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goto err_gpiochip_add;
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}
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irq_base = irq_alloc_descs(-1, 0, gpio_pins[chip->ioh], GFP_KERNEL);
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if (irq_base < 0) {
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dev_warn(&pdev->dev, "PCH gpio: Failed to get IRQ base num\n");
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chip->irq_base = -1;
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goto end;
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}
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chip->irq_base = irq_base;
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ret = request_irq(pdev->irq, pch_gpio_handler,
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IRQF_SHARED, KBUILD_MODNAME, chip);
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if (ret != 0) {
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dev_err(&pdev->dev,
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"%s request_irq failed\n", __func__);
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goto err_request_irq;
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}
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pch_gpio_alloc_generic_chip(chip, irq_base, gpio_pins[chip->ioh]);
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/* Initialize interrupt ien register */
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iowrite32(0, &chip->reg->ien);
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end:
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return 0;
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err_request_irq:
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irq_free_descs(irq_base, gpio_pins[chip->ioh]);
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ret = gpiochip_remove(&chip->gpio);
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if (ret)
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dev_err(&pdev->dev, "%s gpiochip_remove failed\n", __func__);
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err_gpiochip_add:
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pci_iounmap(pdev, chip->base);
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@ -267,6 +448,12 @@ static void __devexit pch_gpio_remove(struct pci_dev *pdev)
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int err;
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struct pch_gpio *chip = pci_get_drvdata(pdev);
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if (chip->irq_base != -1) {
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free_irq(pdev->irq, chip);
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irq_free_descs(chip->irq_base, gpio_pins[chip->ioh]);
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}
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err = gpiochip_remove(&chip->gpio);
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if (err)
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dev_err(&pdev->dev, "Failed gpiochip_remove\n");
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