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perf vendors events arm64: Arm Cortex-A75
Add PMU events for Arm Cortex-A75 Add corresponding common events Update mapfile.csv Event data based on: https://github.com/ARM-software/data/tree/master/pmu/cortex-a75.json which is based on PMU event descriptions from the Arm Cortex-A75 Technical Reference Manual. Common event data based on: https://github.com/ARM-software/data/blob/master/pmu/common_armv9.json which is based on PMU event descriptions found in the Arm Architecture Reference Manual: https://developer.arm.com/documentation/ddi0487/ Mapping data (for mapfile.csv) based on: https://github.com/ARM-software/data/blob/master/cpus.json which is based on Main ID Register (MIDR) information found in the Arm Technical Reference Manuals for individual CPUs. Reviewed-by: John Garry <john.garry@huawei.com> Signed-off-by: Nick Forrington <nick.forrington@arm.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Andi Kleen <ak@linux.intel.com> Cc: Andrew Kilroy <andrew.kilroy@arm.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: James Clark <james.clark@arm.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Kajol Jain <kjain@linux.ibm.com> Cc: Leo Yan <leo.yan@linaro.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Mike Leach <mike.leach@linaro.org> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Will Deacon <will@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20220520181455.340344-8-nick.forrington@arm.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
This commit is contained in:
Nick Forrington
Arnaldo Carvalho de Melo
parent
64a091c67a
commit
387b5a8db3
11
tools/perf/pmu-events/arch/arm64/arm/cortex-a75/branch.json
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11
tools/perf/pmu-events/arch/arm64/arm/cortex-a75/branch.json
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@ -0,0 +1,11 @@
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[
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{
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"ArchStdEvent": "BR_MIS_PRED"
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},
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{
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"ArchStdEvent": "BR_PRED"
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},
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{
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"ArchStdEvent": "BR_INDIRECT_SPEC"
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}
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]
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17
tools/perf/pmu-events/arch/arm64/arm/cortex-a75/bus.json
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17
tools/perf/pmu-events/arch/arm64/arm/cortex-a75/bus.json
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@ -0,0 +1,17 @@
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[
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{
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"ArchStdEvent": "CPU_CYCLES"
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},
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{
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"ArchStdEvent": "BUS_ACCESS"
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},
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{
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"ArchStdEvent": "BUS_CYCLES"
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},
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{
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"ArchStdEvent": "BUS_ACCESS_RD"
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},
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{
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"ArchStdEvent": "BUS_ACCESS_WR"
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}
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]
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164
tools/perf/pmu-events/arch/arm64/arm/cortex-a75/cache.json
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164
tools/perf/pmu-events/arch/arm64/arm/cortex-a75/cache.json
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@ -0,0 +1,164 @@
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[
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{
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"ArchStdEvent": "L1I_CACHE_REFILL"
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},
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{
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"ArchStdEvent": "L1I_TLB_REFILL"
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},
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{
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"ArchStdEvent": "L1D_CACHE_REFILL"
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},
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{
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"ArchStdEvent": "L1D_CACHE"
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},
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{
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"ArchStdEvent": "L1D_TLB_REFILL"
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},
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{
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"ArchStdEvent": "L1I_CACHE"
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},
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{
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"ArchStdEvent": "L1D_CACHE_WB"
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},
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{
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"ArchStdEvent": "L2D_CACHE"
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},
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{
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"ArchStdEvent": "L2D_CACHE_REFILL"
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},
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{
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"ArchStdEvent": "L2D_CACHE_WB"
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},
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{
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"ArchStdEvent": "L1D_CACHE_ALLOCATE"
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},
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{
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"ArchStdEvent": "L2D_CACHE_ALLOCATE"
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},
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{
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"ArchStdEvent": "L1D_TLB"
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},
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{
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"ArchStdEvent": "L1I_TLB"
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},
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{
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"ArchStdEvent": "L3D_CACHE_ALLOCATE"
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},
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{
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"ArchStdEvent": "L3D_CACHE_REFILL"
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},
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{
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"ArchStdEvent": "L3D_CACHE"
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},
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{
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"ArchStdEvent": "L2D_TLB_REFILL"
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},
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{
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"ArchStdEvent": "L2D_TLB"
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},
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{
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"ArchStdEvent": "L2I_TLB"
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},
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{
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"ArchStdEvent": "DTLB_WALK"
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},
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{
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"ArchStdEvent": "ITLB_WALK"
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},
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{
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"ArchStdEvent": "LL_CACHE_RD"
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},
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{
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"ArchStdEvent": "LL_CACHE_MISS_RD"
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},
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{
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"ArchStdEvent": "L1D_CACHE_RD"
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},
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{
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"ArchStdEvent": "L1D_CACHE_WR"
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},
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{
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"ArchStdEvent": "L1D_CACHE_WB_VICTIM"
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},
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{
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"ArchStdEvent": "L1D_CACHE_WB_CLEAN"
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},
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{
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"ArchStdEvent": "L1D_CACHE_INVAL"
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},
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{
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"ArchStdEvent": "L2D_CACHE_RD"
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},
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{
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"ArchStdEvent": "L2D_CACHE_WR"
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},
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{
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"ArchStdEvent": "L2D_CACHE_WB_VICTIM"
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},
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{
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"ArchStdEvent": "L2D_CACHE_WB_CLEAN"
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},
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{
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"ArchStdEvent": "L2D_CACHE_INVAL"
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},
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{
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"ArchStdEvent": "L3D_CACHE_RD"
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},
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{
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"ArchStdEvent": "L3D_CACHE_REFILL_RD"
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},
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{
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"PublicDescription": "Number of ways read in the instruction cache - Tag RAM",
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"EventCode": "0xC2",
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"EventName": "I_TAG_RAM_RD",
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"BriefDescription": "Number of ways read in the instruction cache - Tag RAM"
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},
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{
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"PublicDescription": "Number of ways read in the instruction cache - Data RAM",
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"EventCode": "0xC3",
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"EventName": "I_DATA_RAM_RD",
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"BriefDescription": "Number of ways read in the instruction cache - Data RAM"
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},
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{
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"PublicDescription": "Number of ways read in the instruction BTAC RAM",
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"EventCode": "0xC4",
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"EventName": "I_BTAC_RAM_RD",
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"BriefDescription": "Number of ways read in the instruction BTAC RAM"
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},
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{
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"PublicDescription": "Level 1 PLD TLB refill",
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"EventCode": "0xE7",
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"EventName": "L1PLD_TLB_REFILL",
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"BriefDescription": "Level 1 PLD TLB refill"
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},
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{
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"PublicDescription": "Level 2 preload and MMU prefetcher TLB access. This event only counts software and hardware prefetches at Level 2",
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"EventCode": "0xE8",
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"EventName": "L2PLD_TLB",
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"BriefDescription": "Level 2 preload and MMU prefetcher TLB access. This event only counts software and hardware prefetches at Level 2"
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},
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{
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"PublicDescription": "Level 1 TLB flush",
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"EventCode": "0xE9",
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"EventName": "UTLB_FLUSH",
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"BriefDescription": "Level 1 TLB flush"
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},
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{
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"PublicDescription": "Level 2 TLB access",
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"EventCode": "0xEA",
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"EventName": "TLB_ACCESS",
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"BriefDescription": "Level 2 TLB access"
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},
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{
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"PublicDescription": "Level 1 preload TLB access. This event only counts software and hardware prefetches at Level 1. This event counts all accesses to the preload data micro TLB, that is L1 prefetcher and preload instructions. This event does not take into account whether the MMU is enabled or not",
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"EventCode": "0xEB",
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"EventName": "L1PLD_TLB",
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"BriefDescription": "Level 1 preload TLB access. This event only counts software and hardware prefetches at Level 1. This event counts all accesses to the preload data micro TLB, that is L1 prefetcher and preload instructions. This event does not take into account whether the MMU is enabled or not"
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},
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{
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"PublicDescription": "Prefetch access to unified TLB that caused a page table walk. This event counts software and hardware prefetches",
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"EventCode": "0xEC",
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"EventName": "PLDTLB_WALK",
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"BriefDescription": "Prefetch access to unified TLB that caused a page table walk. This event counts software and hardware prefetches"
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}
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]
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14
tools/perf/pmu-events/arch/arm64/arm/cortex-a75/etm.json
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14
tools/perf/pmu-events/arch/arm64/arm/cortex-a75/etm.json
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@ -0,0 +1,14 @@
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[
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{
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"PublicDescription": "ETM trace unit output 0",
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"EventCode": "0xDE",
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"EventName": "ETM_EXT_OUT0",
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"BriefDescription": "ETM trace unit output 0"
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},
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{
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"PublicDescription": "ETM trace unit output 1",
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"EventCode": "0xDF",
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"EventName": "ETM_EXT_OUT1",
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"BriefDescription": "ETM trace unit output 1"
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}
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]
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@ -0,0 +1,17 @@
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[
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{
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"ArchStdEvent": "EXC_TAKEN"
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},
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{
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"ArchStdEvent": "EXC_UNDEF"
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},
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{
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"ArchStdEvent": "EXC_HVC"
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},
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{
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"PublicDescription": "Number of traps to hypervisor. This event counts the number of exception traps taken to EL2, excluding HVC instructions. This event is set every time that an exception is executed because of a decoded trap to the hypervisor. CCFAIL exceptions and traps caused by HVC instructions are excluded. This event is not counted when it is accessible from Non-secure EL0 or EL1",
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"EventCode": "0xDC",
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"EventName": "EXC_TRAP_HYP",
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"BriefDescription": "Number of traps to hypervisor. This event counts the number of exception traps taken to EL2, excluding HVC instructions. This event is set every time that an exception is executed because of a decoded trap to the hypervisor. CCFAIL exceptions and traps caused by HVC instructions are excluded. This event is not counted when it is accessible from Non-secure EL0 or EL1"
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}
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]
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@ -0,0 +1,74 @@
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[
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{
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"ArchStdEvent": "SW_INCR"
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},
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{
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"ArchStdEvent": "INST_RETIRED"
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},
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{
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"ArchStdEvent": "EXC_RETURN"
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},
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{
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"ArchStdEvent": "CID_WRITE_RETIRED"
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},
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{
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"ArchStdEvent": "PC_WRITE_RETIRED"
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},
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{
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"ArchStdEvent": "BR_IMMED_RETIRED"
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},
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{
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"ArchStdEvent": "BR_RETURN_RETIRED"
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},
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{
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"ArchStdEvent": "INST_SPEC"
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},
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{
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"ArchStdEvent": "TTBR_WRITE_RETIRED"
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},
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{
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"ArchStdEvent": "BR_RETIRED"
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},
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{
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"ArchStdEvent": "LDREX_SPEC"
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},
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{
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"ArchStdEvent": "STREX_PASS_SPEC"
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},
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{
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"ArchStdEvent": "STREX_FAIL_SPEC"
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},
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{
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"ArchStdEvent": "STREX_SPEC"
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},
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{
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"ArchStdEvent": "LD_SPEC"
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},
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{
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"ArchStdEvent": "ST_SPEC"
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},
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{
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"ArchStdEvent": "LDST_SPEC"
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},
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{
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"ArchStdEvent": "DP_SPEC"
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},
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{
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"ArchStdEvent": "ASE_SPEC"
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},
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{
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"ArchStdEvent": "VFP_SPEC"
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},
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{
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"ArchStdEvent": "CRYPTO_SPEC"
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},
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{
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"ArchStdEvent": "ISB_SPEC"
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},
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{
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"ArchStdEvent": "DSB_SPEC"
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},
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{
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"ArchStdEvent": "DMB_SPEC"
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}
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]
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17
tools/perf/pmu-events/arch/arm64/arm/cortex-a75/memory.json
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17
tools/perf/pmu-events/arch/arm64/arm/cortex-a75/memory.json
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[
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{
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"ArchStdEvent": "MEM_ACCESS"
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},
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{
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"ArchStdEvent": "REMOTE_ACCESS_RD"
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},
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{
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"ArchStdEvent": "MEM_ACCESS_RD"
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},
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{
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"ArchStdEvent": "MEM_ACCESS_WR"
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},
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{
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"ArchStdEvent": "UNALIGNED_LDST_SPEC"
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}
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]
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44
tools/perf/pmu-events/arch/arm64/arm/cortex-a75/mmu.json
Normal file
44
tools/perf/pmu-events/arch/arm64/arm/cortex-a75/mmu.json
Normal file
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[
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{
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"PublicDescription": "Duration of a translation table walk handled by the MMU",
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"EventCode": "0xE0",
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"EventName": "MMU_PTW",
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"BriefDescription": "Duration of a translation table walk handled by the MMU"
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},
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{
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"PublicDescription": "Duration of a Stage 1 translation table walk handled by the MMU. This event is not counted when it is accessible from Non-secure EL0 or EL1",
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"EventCode": "0xE1",
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"EventName": "MMU_PTW_ST1",
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"BriefDescription": "Duration of a Stage 1 translation table walk handled by the MMU. This event is not counted when it is accessible from Non-secure EL0 or EL1"
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},
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{
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"PublicDescription": "Duration of a Stage 2 translation table walk handled by the MMU. This event is not counted when it is accessible from Non-secure EL0 or EL1",
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"EventCode": "0xE2",
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"EventName": "MMU_PTW_ST2",
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"BriefDescription": "Duration of a Stage 2 translation table walk handled by the MMU. This event is not counted when it is accessible from Non-secure EL0 or EL1"
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},
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{
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"PublicDescription": "Duration of a translation table walk requested by the LSU",
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"EventCode": "0xE3",
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"EventName": "MMU_PTW_LSU",
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"BriefDescription": "Duration of a translation table walk requested by the LSU"
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},
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{
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"PublicDescription": "Duration of a translation table walk requested by the instruction side",
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"EventCode": "0xE4",
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"EventName": "MMU_PTW_ISIDE",
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"BriefDescription": "Duration of a translation table walk requested by the instruction side"
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},
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{
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"PublicDescription": "Duration of a translation table walk requested by a Preload instruction or Prefetch request",
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"EventCode": "0xE5",
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"EventName": "MMU_PTW_PLD",
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"BriefDescription": "Duration of a translation table walk requested by a Preload instruction or Prefetch request"
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},
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{
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"PublicDescription": "Duration of a translation table walk requested by an address translation operation",
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"EventCode": "0xE6",
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"EventName": "MMU_PTW_CP15",
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"BriefDescription": "Duration of a translation table walk requested by an address translation operation"
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}
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]
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[
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{
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"ArchStdEvent": "STALL_FRONTEND"
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},
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{
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"ArchStdEvent": "STALL_BACKEND"
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},
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{
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"PublicDescription": "A linefill caused an instruction side stall",
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"EventCode": "0xC0",
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"EventName": "LF_STALL",
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"BriefDescription": "A linefill caused an instruction side stall"
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},
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{
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"PublicDescription": "A translation table walk caused an instruction side stall",
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"EventCode": "0xC1",
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"EventName": "PTW_STALL",
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"BriefDescription": "A translation table walk caused an instruction side stall"
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},
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{
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"PublicDescription": "Duration for which all slots in the Load-Store Unit (LSU) are busy",
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"EventCode": "0xD3",
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"EventName": "D_LSU_SLOT_FULL",
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"BriefDescription": "Duration for which all slots in the Load-Store Unit (LSU) are busy"
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},
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{
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"PublicDescription": "Duration for which all slots in the load-store issue queue are busy. This event counts the cycles where all slots in the LS IQs are full with micro-operations waiting for issuing, and the dispatch stage is not empty",
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"EventCode": "0xD8",
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"EventName": "LS_IQ_FULL",
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"BriefDescription": "Duration for which all slots in the load-store issue queue are busy. This event counts the cycles where all slots in the LS IQs are full with micro-operations waiting for issuing, and the dispatch stage is not empty"
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},
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{
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"PublicDescription": "Duration for which all slots in the data processing issue queue are busy. This event counts the cycles where all slots in the DP0 and DP1 IQs are full with micro-operations waiting for issuing, and the despatch stage is not empty",
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"EventCode": "0xD9",
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"EventName": "DP_IQ_FULL",
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"BriefDescription": "Duration for which all slots in the data processing issue queue are busy. This event counts the cycles where all slots in the DP0 and DP1 IQs are full with micro-operations waiting for issuing, and the despatch stage is not empty"
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||||
},
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||||
{
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"PublicDescription": "Duration for which all slots in the data engine issue queue are busy. This event is set every time that the data engine rename has at least one valid instruction, excluding No Operations (NOPs), that cannot move to the issue stage because accpt_instr is LOW",
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"EventCode": "0xDA",
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"EventName": "DE_IQ_FULL",
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"BriefDescription": "Duration for which all slots in the data engine issue queue are busy. This event is set every time that the data engine rename has at least one valid instruction, excluding No Operations (NOPs), that cannot move to the issue stage because accpt_instr is LOW"
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}
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]
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@ -179,6 +179,12 @@
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"EventName": "BUS_CYCLES",
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"BriefDescription": "Bus cycle"
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||||
},
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||||
{
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||||
"PublicDescription": "Level 1 data cache allocation without refill",
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"EventCode": "0x1F",
|
||||
"EventName": "L1D_CACHE_ALLOCATE",
|
||||
"BriefDescription": "Level 1 data cache allocation without refill"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Attributable Level 2 data cache allocation without refill",
|
||||
"EventCode": "0x20",
|
||||
|
||||
@ -21,6 +21,7 @@
|
||||
0x00000000410fd070,v1,arm/cortex-a57-a72,core
|
||||
0x00000000410fd080,v1,arm/cortex-a57-a72,core
|
||||
0x00000000410fd090,v1,arm/cortex-a73,core
|
||||
0x00000000410fd0a0,v1,arm/cortex-a75,core
|
||||
0x00000000410fd0b0,v1,arm/cortex-a76-n1,core
|
||||
0x00000000410fd0c0,v1,arm/cortex-a76-n1,core
|
||||
0x00000000410fd400,v1,arm/neoverse-v1,core
|
||||
|
||||
|
Loading…
Reference in New Issue
Block a user