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ath9k_hw: clean up RF Bank6 handling on AR5416/AR91xx
There are two sets of initvals for this RF bank, one with TPC support and one without. The TPC one always gets used, so remove the other one to avoid confusion. Signed-off-by: Felix Fietkau <nbd@openwrt.org> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -485,9 +485,7 @@ static int ar5008_hw_rf_alloc_ext_banks(struct ath_hw *ah)
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ATH_ALLOC_BANK(ah->analogBank2Data, ah->iniBank2.ia_rows);
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ATH_ALLOC_BANK(ah->analogBank3Data, ah->iniBank3.ia_rows);
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ATH_ALLOC_BANK(ah->analogBank6Data, ah->iniBank6.ia_rows);
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ATH_ALLOC_BANK(ah->analogBank6TPCData, ah->iniBank6TPC.ia_rows);
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ATH_ALLOC_BANK(ah->analogBank7Data, ah->iniBank7.ia_rows);
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ATH_ALLOC_BANK(ah->bank6Temp, ah->iniBank6.ia_rows);
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return 0;
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#undef ATH_ALLOC_BANK
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@ -517,6 +515,7 @@ static bool ar5008_hw_set_rf_regs(struct ath_hw *ah,
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u32 ob5GHz = 0, db5GHz = 0;
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u32 ob2GHz = 0, db2GHz = 0;
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int regWrites = 0;
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int i;
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/*
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* Software does not need to program bank data
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@ -541,13 +540,9 @@ static bool ar5008_hw_set_rf_regs(struct ath_hw *ah,
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/* Setup Bank 6 Write */
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ar5008_rf_bank_setup(ah->analogBank3Data, &ah->iniBank3,
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modesIndex);
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{
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int i;
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for (i = 0; i < ah->iniBank6TPC.ia_rows; i++) {
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ah->analogBank6Data[i] =
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INI_RA(&ah->iniBank6TPC, i, modesIndex);
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}
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}
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for (i = 0; i < ah->iniBank6.ia_rows; i++)
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ah->analogBank6Data[i] = INI_RA(&ah->iniBank6, i, modesIndex);
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/* Only the 5 or 2 GHz OB/DB need to be set for a mode */
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if (eepMinorRev >= 2) {
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@ -572,18 +567,12 @@ static bool ar5008_hw_set_rf_regs(struct ath_hw *ah,
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ar5008_rf_bank_setup(ah->analogBank7Data, &ah->iniBank7, 1);
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/* Write Analog registers */
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REG_WRITE_RF_ARRAY(&ah->iniBank0, ah->analogBank0Data,
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regWrites);
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REG_WRITE_RF_ARRAY(&ah->iniBank1, ah->analogBank1Data,
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regWrites);
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REG_WRITE_RF_ARRAY(&ah->iniBank2, ah->analogBank2Data,
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regWrites);
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REG_WRITE_RF_ARRAY(&ah->iniBank3, ah->analogBank3Data,
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regWrites);
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REG_WRITE_RF_ARRAY(&ah->iniBank6TPC, ah->analogBank6Data,
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regWrites);
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REG_WRITE_RF_ARRAY(&ah->iniBank7, ah->analogBank7Data,
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regWrites);
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REG_WRITE_RF_ARRAY(&ah->iniBank0, ah->analogBank0Data, regWrites);
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REG_WRITE_RF_ARRAY(&ah->iniBank1, ah->analogBank1Data, regWrites);
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REG_WRITE_RF_ARRAY(&ah->iniBank2, ah->analogBank2Data, regWrites);
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REG_WRITE_RF_ARRAY(&ah->iniBank3, ah->analogBank3Data, regWrites);
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REG_WRITE_RF_ARRAY(&ah->iniBank6, ah->analogBank6Data, regWrites);
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REG_WRITE_RF_ARRAY(&ah->iniBank7, ah->analogBank7Data, regWrites);
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return true;
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}
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@ -67,12 +67,10 @@ static int ar9002_hw_init_mode_regs(struct ath_hw *ah)
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} else if (AR_SREV_9100_OR_LATER(ah)) {
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INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100);
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INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100);
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INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100);
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INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100);
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} else {
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INIT_INI_ARRAY(&ah->iniModes, ar5416Modes);
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INIT_INI_ARRAY(&ah->iniCommon, ar5416Common);
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INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC);
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INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac);
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}
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@ -86,14 +84,11 @@ static int ar9002_hw_init_mode_regs(struct ath_hw *ah)
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INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3);
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INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7);
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/* Common for AR5416, AR9160 */
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if (!AR_SREV_9100(ah))
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INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6);
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/* Common for AR913x, AR9160 */
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if (!AR_SREV_5416(ah))
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INIT_INI_ARRAY(&ah->iniBank6TPC,
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ar5416Bank6TPC_9100);
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INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6TPC_9100);
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else
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INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6TPC);
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}
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/* iniAddac needs to be modified for these chips */
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@ -852,9 +852,7 @@ struct ath_hw {
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u32 *analogBank2Data;
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u32 *analogBank3Data;
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u32 *analogBank6Data;
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u32 *analogBank6TPCData;
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u32 *analogBank7Data;
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u32 *bank6Temp;
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int coverage_class;
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u32 slottime;
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@ -891,7 +889,6 @@ struct ath_hw {
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struct ar5416IniArray iniBank2;
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struct ar5416IniArray iniBank3;
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struct ar5416IniArray iniBank6;
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struct ar5416IniArray iniBank6TPC;
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struct ar5416IniArray iniBank7;
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struct ar5416IniArray iniAddac;
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struct ar5416IniArray iniPcieSerdes;
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