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drm/tegra: sor: Support HDMI 2.0 modes
In addition to using the SCDC helpers to enable support for scrambling for HDMI 2.0 modes, take into account the high pixel clocks when programming some of the registers. Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Thierry Reding
parent
c57997bce4
commit
36e90221ac
@ -22,6 +22,7 @@
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_dp_helper.h>
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#include <drm/drm_panel.h>
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#include <drm/drm_scdc_helper.h>
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#include "dc.h"
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#include "drm.h"
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@ -350,11 +351,16 @@ struct tegra_sor {
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struct regulator *avdd_io_supply;
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struct regulator *vdd_pll_supply;
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struct regulator *hdmi_supply;
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struct delayed_work scdc;
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bool scdc_enabled;
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};
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struct tegra_sor_state {
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struct drm_connector_state base;
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unsigned int link_speed;
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unsigned long pclk;
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unsigned int bpc;
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};
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@ -1489,10 +1495,6 @@ static enum drm_mode_status
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tegra_sor_connector_mode_valid(struct drm_connector *connector,
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struct drm_display_mode *mode)
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{
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/* HDMI 2.0 modes are not yet supported */
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if (mode->clock > 340000)
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return MODE_NOCLOCK;
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return MODE_OK;
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}
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@ -1917,6 +1919,18 @@ tegra_sor_encoder_atomic_check(struct drm_encoder *encoder,
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info = &output->connector.display_info;
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/*
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* For HBR2 modes, the SOR brick needs to use the x20 multiplier, so
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* the pixel clock must be corrected accordingly.
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*/
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if (pclk >= 340000000) {
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state->link_speed = 20;
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state->pclk = pclk / 2;
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} else {
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state->link_speed = 10;
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state->pclk = pclk;
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}
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err = tegra_dc_state_setup_clock(dc, crtc_state, sor->clk_parent,
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pclk, 0);
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if (err < 0) {
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@ -2067,6 +2081,81 @@ tegra_sor_hdmi_find_settings(struct tegra_sor *sor, unsigned long frequency)
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return NULL;
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}
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static void tegra_sor_hdmi_disable_scrambling(struct tegra_sor *sor)
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{
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u32 value;
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value = tegra_sor_readl(sor, SOR_HDMI2_CTRL);
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value &= ~SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4;
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value &= ~SOR_HDMI2_CTRL_SCRAMBLE;
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tegra_sor_writel(sor, value, SOR_HDMI2_CTRL);
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}
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static void tegra_sor_hdmi_scdc_disable(struct tegra_sor *sor)
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{
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struct i2c_adapter *ddc = sor->output.ddc;
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drm_scdc_set_high_tmds_clock_ratio(ddc, false);
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drm_scdc_set_scrambling(ddc, false);
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tegra_sor_hdmi_disable_scrambling(sor);
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}
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static void tegra_sor_hdmi_scdc_stop(struct tegra_sor *sor)
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{
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if (sor->scdc_enabled) {
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cancel_delayed_work_sync(&sor->scdc);
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tegra_sor_hdmi_scdc_disable(sor);
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}
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}
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static void tegra_sor_hdmi_enable_scrambling(struct tegra_sor *sor)
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{
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u32 value;
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value = tegra_sor_readl(sor, SOR_HDMI2_CTRL);
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value |= SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4;
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value |= SOR_HDMI2_CTRL_SCRAMBLE;
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tegra_sor_writel(sor, value, SOR_HDMI2_CTRL);
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}
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static void tegra_sor_hdmi_scdc_enable(struct tegra_sor *sor)
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{
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struct i2c_adapter *ddc = sor->output.ddc;
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drm_scdc_set_high_tmds_clock_ratio(ddc, true);
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drm_scdc_set_scrambling(ddc, true);
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tegra_sor_hdmi_enable_scrambling(sor);
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}
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static void tegra_sor_hdmi_scdc_work(struct work_struct *work)
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{
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struct tegra_sor *sor = container_of(work, struct tegra_sor, scdc.work);
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struct i2c_adapter *ddc = sor->output.ddc;
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if (!drm_scdc_get_scrambling_status(ddc)) {
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DRM_DEBUG_KMS("SCDC not scrambled\n");
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tegra_sor_hdmi_scdc_enable(sor);
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}
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schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000));
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}
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static void tegra_sor_hdmi_scdc_start(struct tegra_sor *sor)
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{
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struct drm_scdc *scdc = &sor->output.connector.display_info.hdmi.scdc;
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struct drm_display_mode *mode;
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mode = &sor->output.encoder.crtc->state->adjusted_mode;
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if (mode->clock >= 340000 && scdc->supported) {
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schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000));
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tegra_sor_hdmi_scdc_enable(sor);
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sor->scdc_enabled = true;
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}
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}
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static void tegra_sor_hdmi_disable(struct drm_encoder *encoder)
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{
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struct tegra_output *output = encoder_to_output(encoder);
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@ -2075,6 +2164,8 @@ static void tegra_sor_hdmi_disable(struct drm_encoder *encoder)
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u32 value;
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int err;
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tegra_sor_hdmi_scdc_stop(sor);
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err = tegra_sor_detach(sor);
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if (err < 0)
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dev_err(sor->dev, "failed to detach SOR: %d\n", err);
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@ -2114,12 +2205,14 @@ static void tegra_sor_hdmi_enable(struct drm_encoder *encoder)
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struct tegra_sor *sor = to_sor(output);
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struct tegra_sor_state *state;
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struct drm_display_mode *mode;
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unsigned long rate, pclk;
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unsigned int div, i;
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u32 value;
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int err;
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state = to_sor_state(output->connector.state);
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mode = &encoder->crtc->state->adjusted_mode;
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pclk = mode->clock * 1000;
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pm_runtime_get_sync(sor->dev);
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@ -2195,10 +2288,13 @@ static void tegra_sor_hdmi_enable(struct drm_encoder *encoder)
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value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
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value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
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if (mode->clock < 340000)
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if (mode->clock < 340000) {
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DRM_DEBUG_KMS("setting 2.7 GHz link speed\n");
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value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G2_70;
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else
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} else {
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DRM_DEBUG_KMS("setting 5.4 GHz link speed\n");
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value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G5_40;
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}
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value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK;
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tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
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@ -2254,6 +2350,15 @@ static void tegra_sor_hdmi_enable(struct drm_encoder *encoder)
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return;
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}
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/* adjust clock rate for HDMI 2.0 modes */
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rate = clk_get_rate(sor->clk_parent);
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if (mode->clock >= 340000)
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rate /= 2;
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DRM_DEBUG_KMS("setting clock to %lu Hz, mode: %lu Hz\n", rate, pclk);
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clk_set_rate(sor->clk, rate);
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if (!sor->soc->has_nvdisplay) {
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value = SOR_INPUT_CONTROL_HDMI_SRC_SELECT(dc->pipe);
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@ -2465,6 +2570,8 @@ static void tegra_sor_hdmi_enable(struct drm_encoder *encoder)
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err = tegra_sor_wakeup(sor);
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if (err < 0)
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dev_err(sor->dev, "failed to wakeup SOR: %d\n", err);
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tegra_sor_hdmi_scdc_start(sor);
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}
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static const struct drm_encoder_helper_funcs tegra_sor_hdmi_helpers = {
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@ -2652,6 +2759,8 @@ static int tegra_sor_hdmi_probe(struct tegra_sor *sor)
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return err;
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}
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INIT_DELAYED_WORK(&sor->scdc, tegra_sor_hdmi_scdc_work);
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return 0;
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}
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@ -382,4 +382,8 @@
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#define SOR_HDMI_VSI_INFOFRAME_STATUS 0x124
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#define SOR_HDMI_VSI_INFOFRAME_HEADER 0x125
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#define SOR_HDMI2_CTRL 0x13e
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#define SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4 (1 << 1)
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#define SOR_HDMI2_CTRL_SCRAMBLE (1 << 0)
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#endif
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