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Merge series "spi: Add FSI-attached SPI controller driver" from Eddie James <eajames@linux.ibm.com>:
This series adds a dts binding and a driver for a new SPI controller that is accessed over FSI bus. Eddie James (2): dt-bindings: fsi: Add FSI2SPI bindings spi: Add FSI-attached SPI controller driver .../devicetree/bindings/fsi/ibm,fsi2spi.yaml | 36 ++ MAINTAINERS | 7 + drivers/spi/Kconfig | 7 + drivers/spi/Makefile | 1 + drivers/spi/spi-fsi.c | 558 ++++++++++++++++++ 5 files changed, 609 insertions(+) create mode 100644 Documentation/devicetree/bindings/fsi/ibm,fsi2spi.yaml create mode 100644 drivers/spi/spi-fsi.c -- 2.24.0
This commit is contained in:
Mark Brown
commit
36098a1db7
36
Documentation/devicetree/bindings/fsi/ibm,fsi2spi.yaml
Normal file
36
Documentation/devicetree/bindings/fsi/ibm,fsi2spi.yaml
Normal file
@ -0,0 +1,36 @@
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# SPDX-License-Identifier: (GPL-2.0-or-later)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/fsi/ibm,fsi2spi.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: IBM FSI-attached SPI controllers
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maintainers:
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- Eddie James <eajames@linux.ibm.com>
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description: |
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This binding describes an FSI CFAM engine called the FSI2SPI. Therefore this
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node will always be a child of an FSI CFAM node; see fsi.txt for details on
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FSI slave and CFAM nodes. This FSI2SPI engine provides access to a number of
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SPI controllers.
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properties:
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compatible:
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enum:
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- ibm,fsi2spi
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reg:
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items:
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- description: FSI slave address
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required:
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- compatible
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- reg
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examples:
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- |
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fsi2spi@1c00 {
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compatible = "ibm,fsi2spi";
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reg = <0x1c00 0x400>;
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};
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@ -6861,6 +6861,13 @@ S: Maintained
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F: drivers/i2c/busses/i2c-fsi.c
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F: Documentation/devicetree/bindings/i2c/i2c-fsi.txt
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FSI-ATTACHED SPI DRIVER
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M: Eddie James <eajames@linux.ibm.com>
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L: linux-spi@vger.kernel.org
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S: Maintained
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F: drivers/spi/spi-fsi.c
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F: Documentation/devicetree/bindings/fsi/ibm,fsi2spi.yaml
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FSNOTIFY: FILESYSTEM NOTIFICATION INFRASTRUCTURE
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M: Jan Kara <jack@suse.cz>
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R: Amir Goldstein <amir73il@gmail.com>
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@ -271,6 +271,13 @@ config SPI_FALCON
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has only been tested with m25p80 type chips. The hardware has no
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support for other types of SPI peripherals.
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config SPI_FSI
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tristate "FSI SPI driver"
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depends on FSI
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help
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This enables support for the driver for FSI bus attached SPI
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controllers.
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config SPI_FSL_LPSPI
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tristate "Freescale i.MX LPSPI controller"
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depends on ARCH_MXC || COMPILE_TEST
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@ -42,6 +42,7 @@ spi-dw-midpci-objs := spi-dw-pci.o spi-dw-mid.o
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obj-$(CONFIG_SPI_EFM32) += spi-efm32.o
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obj-$(CONFIG_SPI_EP93XX) += spi-ep93xx.o
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obj-$(CONFIG_SPI_FALCON) += spi-falcon.o
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obj-$(CONFIG_SPI_FSI) += spi-fsi.o
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obj-$(CONFIG_SPI_FSL_CPM) += spi-fsl-cpm.o
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obj-$(CONFIG_SPI_FSL_DSPI) += spi-fsl-dspi.o
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obj-$(CONFIG_SPI_FSL_LIB) += spi-fsl-lib.o
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558
drivers/spi/spi-fsi.c
Normal file
558
drivers/spi/spi-fsi.c
Normal file
@ -0,0 +1,558 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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// Copyright (C) IBM Corporation 2020
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#include <linux/bitfield.h>
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#include <linux/bits.h>
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#include <linux/fsi.h>
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#include <linux/jiffies.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/spi/spi.h>
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#define FSI_ENGID_SPI 0x23
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#define FSI_MBOX_ROOT_CTRL_8 0x2860
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#define FSI2SPI_DATA0 0x00
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#define FSI2SPI_DATA1 0x04
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#define FSI2SPI_CMD 0x08
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#define FSI2SPI_CMD_WRITE BIT(31)
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#define FSI2SPI_RESET 0x18
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#define FSI2SPI_STATUS 0x1c
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#define FSI2SPI_STATUS_ANY_ERROR BIT(31)
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#define FSI2SPI_IRQ 0x20
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#define SPI_FSI_BASE 0x70000
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#define SPI_FSI_INIT_TIMEOUT_MS 1000
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#define SPI_FSI_MAX_TRANSFER_SIZE 2048
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#define SPI_FSI_ERROR 0x0
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#define SPI_FSI_COUNTER_CFG 0x1
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#define SPI_FSI_COUNTER_CFG_LOOPS(x) (((u64)(x) & 0xffULL) << 32)
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#define SPI_FSI_CFG1 0x2
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#define SPI_FSI_CLOCK_CFG 0x3
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#define SPI_FSI_CLOCK_CFG_MM_ENABLE BIT_ULL(32)
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#define SPI_FSI_CLOCK_CFG_ECC_DISABLE (BIT_ULL(35) | BIT_ULL(33))
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#define SPI_FSI_CLOCK_CFG_RESET1 (BIT_ULL(36) | BIT_ULL(38))
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#define SPI_FSI_CLOCK_CFG_RESET2 (BIT_ULL(37) | BIT_ULL(39))
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#define SPI_FSI_CLOCK_CFG_MODE (BIT_ULL(41) | BIT_ULL(42))
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#define SPI_FSI_CLOCK_CFG_SCK_RECV_DEL GENMASK_ULL(51, 44)
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#define SPI_FSI_CLOCK_CFG_SCK_NO_DEL BIT_ULL(51)
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#define SPI_FSI_CLOCK_CFG_SCK_DIV GENMASK_ULL(63, 52)
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#define SPI_FSI_MMAP 0x4
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#define SPI_FSI_DATA_TX 0x5
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#define SPI_FSI_DATA_RX 0x6
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#define SPI_FSI_SEQUENCE 0x7
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#define SPI_FSI_SEQUENCE_STOP 0x00
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#define SPI_FSI_SEQUENCE_SEL_SLAVE(x) (0x10 | ((x) & 0xf))
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#define SPI_FSI_SEQUENCE_SHIFT_OUT(x) (0x30 | ((x) & 0xf))
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#define SPI_FSI_SEQUENCE_SHIFT_IN(x) (0x40 | ((x) & 0xf))
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#define SPI_FSI_SEQUENCE_COPY_DATA_TX 0xc0
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#define SPI_FSI_SEQUENCE_BRANCH(x) (0xe0 | ((x) & 0xf))
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#define SPI_FSI_STATUS 0x8
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#define SPI_FSI_STATUS_ERROR \
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(GENMASK_ULL(31, 21) | GENMASK_ULL(15, 12))
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#define SPI_FSI_STATUS_SEQ_STATE GENMASK_ULL(55, 48)
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#define SPI_FSI_STATUS_SEQ_STATE_IDLE BIT_ULL(48)
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#define SPI_FSI_STATUS_TDR_UNDERRUN BIT_ULL(57)
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#define SPI_FSI_STATUS_TDR_OVERRUN BIT_ULL(58)
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#define SPI_FSI_STATUS_TDR_FULL BIT_ULL(59)
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#define SPI_FSI_STATUS_RDR_UNDERRUN BIT_ULL(61)
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#define SPI_FSI_STATUS_RDR_OVERRUN BIT_ULL(62)
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#define SPI_FSI_STATUS_RDR_FULL BIT_ULL(63)
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#define SPI_FSI_STATUS_ANY_ERROR \
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(SPI_FSI_STATUS_ERROR | SPI_FSI_STATUS_TDR_UNDERRUN | \
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SPI_FSI_STATUS_TDR_OVERRUN | SPI_FSI_STATUS_RDR_UNDERRUN | \
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SPI_FSI_STATUS_RDR_OVERRUN)
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#define SPI_FSI_PORT_CTRL 0x9
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struct fsi_spi {
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struct device *dev; /* SPI controller device */
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struct fsi_device *fsi; /* FSI2SPI CFAM engine device */
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u32 base;
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};
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struct fsi_spi_sequence {
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int bit;
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u64 data;
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};
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static int fsi_spi_check_status(struct fsi_spi *ctx)
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{
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int rc;
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u32 sts;
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__be32 sts_be;
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rc = fsi_device_read(ctx->fsi, FSI2SPI_STATUS, &sts_be,
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sizeof(sts_be));
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if (rc)
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return rc;
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sts = be32_to_cpu(sts_be);
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if (sts & FSI2SPI_STATUS_ANY_ERROR) {
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dev_err(ctx->dev, "Error with FSI2SPI interface: %08x.\n", sts);
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return -EIO;
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}
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return 0;
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}
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static int fsi_spi_read_reg(struct fsi_spi *ctx, u32 offset, u64 *value)
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{
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int rc;
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__be32 cmd_be;
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__be32 data_be;
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u32 cmd = offset + ctx->base;
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*value = 0ULL;
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if (cmd & FSI2SPI_CMD_WRITE)
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return -EINVAL;
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cmd_be = cpu_to_be32(cmd);
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rc = fsi_device_write(ctx->fsi, FSI2SPI_CMD, &cmd_be, sizeof(cmd_be));
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if (rc)
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return rc;
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rc = fsi_spi_check_status(ctx);
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if (rc)
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return rc;
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rc = fsi_device_read(ctx->fsi, FSI2SPI_DATA0, &data_be,
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sizeof(data_be));
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if (rc)
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return rc;
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*value |= (u64)be32_to_cpu(data_be) << 32;
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rc = fsi_device_read(ctx->fsi, FSI2SPI_DATA1, &data_be,
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sizeof(data_be));
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if (rc)
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return rc;
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*value |= (u64)be32_to_cpu(data_be);
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dev_dbg(ctx->dev, "Read %02x[%016llx].\n", offset, *value);
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return 0;
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}
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static int fsi_spi_write_reg(struct fsi_spi *ctx, u32 offset, u64 value)
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{
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int rc;
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__be32 cmd_be;
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__be32 data_be;
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u32 cmd = offset + ctx->base;
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if (cmd & FSI2SPI_CMD_WRITE)
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return -EINVAL;
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dev_dbg(ctx->dev, "Write %02x[%016llx].\n", offset, value);
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data_be = cpu_to_be32(upper_32_bits(value));
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rc = fsi_device_write(ctx->fsi, FSI2SPI_DATA0, &data_be,
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sizeof(data_be));
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if (rc)
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return rc;
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data_be = cpu_to_be32(lower_32_bits(value));
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rc = fsi_device_write(ctx->fsi, FSI2SPI_DATA1, &data_be,
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sizeof(data_be));
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if (rc)
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return rc;
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cmd_be = cpu_to_be32(cmd | FSI2SPI_CMD_WRITE);
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rc = fsi_device_write(ctx->fsi, FSI2SPI_CMD, &cmd_be, sizeof(cmd_be));
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if (rc)
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return rc;
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return fsi_spi_check_status(ctx);
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}
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static int fsi_spi_data_in(u64 in, u8 *rx, int len)
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{
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int i;
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int num_bytes = min(len, 8);
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for (i = 0; i < num_bytes; ++i)
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rx[i] = (u8)(in >> (8 * ((num_bytes - 1) - i)));
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return num_bytes;
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}
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static int fsi_spi_data_out(u64 *out, const u8 *tx, int len)
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{
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int i;
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int num_bytes = min(len, 8);
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u8 *out_bytes = (u8 *)out;
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/* Unused bytes of the tx data should be 0. */
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*out = 0ULL;
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for (i = 0; i < num_bytes; ++i)
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out_bytes[8 - (i + 1)] = tx[i];
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return num_bytes;
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}
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static int fsi_spi_reset(struct fsi_spi *ctx)
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{
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int rc;
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dev_dbg(ctx->dev, "Resetting SPI controller.\n");
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rc = fsi_spi_write_reg(ctx, SPI_FSI_CLOCK_CFG,
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SPI_FSI_CLOCK_CFG_RESET1);
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if (rc)
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return rc;
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return fsi_spi_write_reg(ctx, SPI_FSI_CLOCK_CFG,
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SPI_FSI_CLOCK_CFG_RESET2);
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}
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static int fsi_spi_sequence_add(struct fsi_spi_sequence *seq, u8 val)
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{
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/*
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* Add the next byte of instruction to the 8-byte sequence register.
|
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* Then decrement the counter so that the next instruction will go in
|
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* the right place. Return the number of "slots" left in the sequence
|
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* register.
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*/
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seq->data |= (u64)val << seq->bit;
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seq->bit -= 8;
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return ((64 - seq->bit) / 8) - 2;
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}
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|
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static void fsi_spi_sequence_init(struct fsi_spi_sequence *seq)
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{
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seq->bit = 56;
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seq->data = 0ULL;
|
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}
|
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|
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static int fsi_spi_sequence_transfer(struct fsi_spi *ctx,
|
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struct fsi_spi_sequence *seq,
|
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struct spi_transfer *transfer)
|
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{
|
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int loops;
|
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int idx;
|
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int rc;
|
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u8 len = min(transfer->len, 8U);
|
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u8 rem = transfer->len % len;
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|
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loops = transfer->len / len;
|
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|
||||
if (transfer->tx_buf) {
|
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idx = fsi_spi_sequence_add(seq,
|
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SPI_FSI_SEQUENCE_SHIFT_OUT(len));
|
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if (rem)
|
||||
rem = SPI_FSI_SEQUENCE_SHIFT_OUT(rem);
|
||||
} else if (transfer->rx_buf) {
|
||||
idx = fsi_spi_sequence_add(seq,
|
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SPI_FSI_SEQUENCE_SHIFT_IN(len));
|
||||
if (rem)
|
||||
rem = SPI_FSI_SEQUENCE_SHIFT_IN(rem);
|
||||
} else {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (loops > 1) {
|
||||
fsi_spi_sequence_add(seq, SPI_FSI_SEQUENCE_BRANCH(idx));
|
||||
|
||||
if (rem)
|
||||
fsi_spi_sequence_add(seq, rem);
|
||||
|
||||
rc = fsi_spi_write_reg(ctx, SPI_FSI_COUNTER_CFG,
|
||||
SPI_FSI_COUNTER_CFG_LOOPS(loops - 1));
|
||||
if (rc)
|
||||
return rc;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int fsi_spi_transfer_data(struct fsi_spi *ctx,
|
||||
struct spi_transfer *transfer)
|
||||
{
|
||||
int rc = 0;
|
||||
u64 status = 0ULL;
|
||||
|
||||
if (transfer->tx_buf) {
|
||||
int nb;
|
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int sent = 0;
|
||||
u64 out = 0ULL;
|
||||
const u8 *tx = transfer->tx_buf;
|
||||
|
||||
while (transfer->len > sent) {
|
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nb = fsi_spi_data_out(&out, &tx[sent],
|
||||
(int)transfer->len - sent);
|
||||
|
||||
rc = fsi_spi_write_reg(ctx, SPI_FSI_DATA_TX, out);
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
do {
|
||||
rc = fsi_spi_read_reg(ctx, SPI_FSI_STATUS,
|
||||
&status);
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
if (status & SPI_FSI_STATUS_ANY_ERROR) {
|
||||
rc = fsi_spi_reset(ctx);
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
return -EREMOTEIO;
|
||||
}
|
||||
} while (status & SPI_FSI_STATUS_TDR_FULL);
|
||||
|
||||
sent += nb;
|
||||
}
|
||||
} else if (transfer->rx_buf) {
|
||||
int recv = 0;
|
||||
u64 in = 0ULL;
|
||||
u8 *rx = transfer->rx_buf;
|
||||
|
||||
while (transfer->len > recv) {
|
||||
do {
|
||||
rc = fsi_spi_read_reg(ctx, SPI_FSI_STATUS,
|
||||
&status);
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
if (status & SPI_FSI_STATUS_ANY_ERROR) {
|
||||
rc = fsi_spi_reset(ctx);
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
return -EREMOTEIO;
|
||||
}
|
||||
} while (!(status & SPI_FSI_STATUS_RDR_FULL));
|
||||
|
||||
rc = fsi_spi_read_reg(ctx, SPI_FSI_DATA_RX, &in);
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
recv += fsi_spi_data_in(in, &rx[recv],
|
||||
(int)transfer->len - recv);
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int fsi_spi_transfer_init(struct fsi_spi *ctx)
|
||||
{
|
||||
int rc;
|
||||
bool reset = false;
|
||||
unsigned long end;
|
||||
u64 seq_state;
|
||||
u64 clock_cfg = 0ULL;
|
||||
u64 status = 0ULL;
|
||||
u64 wanted_clock_cfg = SPI_FSI_CLOCK_CFG_ECC_DISABLE |
|
||||
SPI_FSI_CLOCK_CFG_SCK_NO_DEL |
|
||||
FIELD_PREP(SPI_FSI_CLOCK_CFG_SCK_DIV, 4);
|
||||
|
||||
end = jiffies + msecs_to_jiffies(SPI_FSI_INIT_TIMEOUT_MS);
|
||||
do {
|
||||
if (time_after(jiffies, end))
|
||||
return -ETIMEDOUT;
|
||||
|
||||
rc = fsi_spi_read_reg(ctx, SPI_FSI_STATUS, &status);
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
seq_state = status & SPI_FSI_STATUS_SEQ_STATE;
|
||||
|
||||
if (status & (SPI_FSI_STATUS_ANY_ERROR |
|
||||
SPI_FSI_STATUS_TDR_FULL |
|
||||
SPI_FSI_STATUS_RDR_FULL)) {
|
||||
if (reset)
|
||||
return -EIO;
|
||||
|
||||
rc = fsi_spi_reset(ctx);
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
reset = true;
|
||||
continue;
|
||||
}
|
||||
} while (seq_state && (seq_state != SPI_FSI_STATUS_SEQ_STATE_IDLE));
|
||||
|
||||
rc = fsi_spi_read_reg(ctx, SPI_FSI_CLOCK_CFG, &clock_cfg);
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
if ((clock_cfg & (SPI_FSI_CLOCK_CFG_MM_ENABLE |
|
||||
SPI_FSI_CLOCK_CFG_ECC_DISABLE |
|
||||
SPI_FSI_CLOCK_CFG_MODE |
|
||||
SPI_FSI_CLOCK_CFG_SCK_RECV_DEL |
|
||||
SPI_FSI_CLOCK_CFG_SCK_DIV)) != wanted_clock_cfg)
|
||||
rc = fsi_spi_write_reg(ctx, SPI_FSI_CLOCK_CFG,
|
||||
wanted_clock_cfg);
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
static int fsi_spi_transfer_one_message(struct spi_controller *ctlr,
|
||||
struct spi_message *mesg)
|
||||
{
|
||||
int rc = 0;
|
||||
u8 seq_slave = SPI_FSI_SEQUENCE_SEL_SLAVE(mesg->spi->chip_select + 1);
|
||||
struct spi_transfer *transfer;
|
||||
struct fsi_spi *ctx = spi_controller_get_devdata(ctlr);
|
||||
|
||||
list_for_each_entry(transfer, &mesg->transfers, transfer_list) {
|
||||
struct fsi_spi_sequence seq;
|
||||
struct spi_transfer *next = NULL;
|
||||
|
||||
/* Sequencer must do shift out (tx) first. */
|
||||
if (!transfer->tx_buf ||
|
||||
transfer->len > SPI_FSI_MAX_TRANSFER_SIZE) {
|
||||
rc = -EINVAL;
|
||||
goto error;
|
||||
}
|
||||
|
||||
dev_dbg(ctx->dev, "Start tx of %d bytes.\n", transfer->len);
|
||||
|
||||
rc = fsi_spi_transfer_init(ctx);
|
||||
if (rc < 0)
|
||||
goto error;
|
||||
|
||||
fsi_spi_sequence_init(&seq);
|
||||
fsi_spi_sequence_add(&seq, seq_slave);
|
||||
|
||||
rc = fsi_spi_sequence_transfer(ctx, &seq, transfer);
|
||||
if (rc)
|
||||
goto error;
|
||||
|
||||
if (!list_is_last(&transfer->transfer_list,
|
||||
&mesg->transfers)) {
|
||||
next = list_next_entry(transfer, transfer_list);
|
||||
|
||||
/* Sequencer can only do shift in (rx) after tx. */
|
||||
if (next->rx_buf) {
|
||||
if (next->len > SPI_FSI_MAX_TRANSFER_SIZE) {
|
||||
rc = -EINVAL;
|
||||
goto error;
|
||||
}
|
||||
|
||||
dev_dbg(ctx->dev, "Sequence rx of %d bytes.\n",
|
||||
next->len);
|
||||
|
||||
rc = fsi_spi_sequence_transfer(ctx, &seq,
|
||||
next);
|
||||
if (rc)
|
||||
goto error;
|
||||
} else {
|
||||
next = NULL;
|
||||
}
|
||||
}
|
||||
|
||||
fsi_spi_sequence_add(&seq, SPI_FSI_SEQUENCE_SEL_SLAVE(0));
|
||||
|
||||
rc = fsi_spi_write_reg(ctx, SPI_FSI_SEQUENCE, seq.data);
|
||||
if (rc)
|
||||
goto error;
|
||||
|
||||
rc = fsi_spi_transfer_data(ctx, transfer);
|
||||
if (rc)
|
||||
goto error;
|
||||
|
||||
if (next) {
|
||||
rc = fsi_spi_transfer_data(ctx, next);
|
||||
if (rc)
|
||||
goto error;
|
||||
|
||||
transfer = next;
|
||||
}
|
||||
}
|
||||
|
||||
error:
|
||||
mesg->status = rc;
|
||||
spi_finalize_current_message(ctlr);
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
static size_t fsi_spi_max_transfer_size(struct spi_device *spi)
|
||||
{
|
||||
return SPI_FSI_MAX_TRANSFER_SIZE;
|
||||
}
|
||||
|
||||
static int fsi_spi_probe(struct device *dev)
|
||||
{
|
||||
int rc;
|
||||
u32 root_ctrl_8;
|
||||
struct device_node *np;
|
||||
int num_controllers_registered = 0;
|
||||
struct fsi_device *fsi = to_fsi_dev(dev);
|
||||
|
||||
/*
|
||||
* Check the SPI mux before attempting to probe. If the mux isn't set
|
||||
* then the SPI controllers can't access their slave devices.
|
||||
*/
|
||||
rc = fsi_slave_read(fsi->slave, FSI_MBOX_ROOT_CTRL_8, &root_ctrl_8,
|
||||
sizeof(root_ctrl_8));
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
if (!root_ctrl_8) {
|
||||
dev_dbg(dev, "SPI mux not set, aborting probe.\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
for_each_available_child_of_node(dev->of_node, np) {
|
||||
u32 base;
|
||||
struct fsi_spi *ctx;
|
||||
struct spi_controller *ctlr;
|
||||
|
||||
if (of_property_read_u32(np, "reg", &base))
|
||||
continue;
|
||||
|
||||
ctlr = spi_alloc_master(dev, sizeof(*ctx));
|
||||
if (!ctlr)
|
||||
break;
|
||||
|
||||
ctlr->dev.of_node = np;
|
||||
ctlr->num_chipselect = of_get_available_child_count(np) ?: 1;
|
||||
ctlr->flags = SPI_CONTROLLER_HALF_DUPLEX;
|
||||
ctlr->max_transfer_size = fsi_spi_max_transfer_size;
|
||||
ctlr->transfer_one_message = fsi_spi_transfer_one_message;
|
||||
|
||||
ctx = spi_controller_get_devdata(ctlr);
|
||||
ctx->dev = &ctlr->dev;
|
||||
ctx->fsi = fsi;
|
||||
ctx->base = base + SPI_FSI_BASE;
|
||||
|
||||
rc = devm_spi_register_controller(dev, ctlr);
|
||||
if (rc)
|
||||
spi_controller_put(ctlr);
|
||||
else
|
||||
num_controllers_registered++;
|
||||
}
|
||||
|
||||
if (!num_controllers_registered)
|
||||
return -ENODEV;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct fsi_device_id fsi_spi_ids[] = {
|
||||
{ FSI_ENGID_SPI, FSI_VERSION_ANY },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(fsi, fsi_spi_ids);
|
||||
|
||||
static struct fsi_driver fsi_spi_driver = {
|
||||
.id_table = fsi_spi_ids,
|
||||
.drv = {
|
||||
.name = "spi-fsi",
|
||||
.bus = &fsi_bus_type,
|
||||
.probe = fsi_spi_probe,
|
||||
},
|
||||
};
|
||||
module_fsi_driver(fsi_spi_driver);
|
||||
|
||||
MODULE_AUTHOR("Eddie James <eajames@linux.ibm.com>");
|
||||
MODULE_DESCRIPTION("FSI attached SPI controller");
|
||||
MODULE_LICENSE("GPL");
|
||||
Loading…
Reference in New Issue
Block a user