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ARM: SoC fixes for 6.11, part 2

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There is a fairly large number of bug fixes for Qualcomm platforms,
 most of them addressing issues with the devicetree files for the
 newly added Snapdragon X1 based laptops to make them more reliable.
 The Qualcomm driver changes address a few build-time issues as well
 as runtime problems in the tzmem and scm firmware, the USB Type-C
 driver, and the cmd-db and pmic_glink soc drivers.
 
 The NXP i.MX usually gets a bunch of devicetree fixes that is proportional
 to the number of supported machines. This includes both warning fixes
 and correctness for the 64-bit i.MX9, i.MX8 and layerscape platforms,
 as well as a single fix for a 32-bit i.MX6 based board.
 
 The other changes are the usual minor changes, including an update to the
 MAINTAINERS file, an omap3 dts file and a SoC driver for mpfs (risc-v).
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Merge tag 'arm-fixes-6.11-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC fixes from Arnd Bergmann:
 "There is a fairly large number of bug fixes for Qualcomm platforms,
  most of them addressing issues with the devicetree files for the newly
  added Snapdragon X1 based laptops to make them more reliable.

  The Qualcomm driver changes address a few build-time issues as well as
  runtime problems in the tzmem and scm firmware, the USB Type-C driver,
  and the cmd-db and pmic_glink soc drivers.

  The NXP i.MX usually gets a bunch of devicetree fixes that is
  proportional to the number of supported machines. This includes both
  warning fixes and correctness for the 64-bit i.MX9, i.MX8 and
  layerscape platforms, as well as a single fix for a 32-bit i.MX6 based
  board.

  The other changes are the usual minor changes, including an update to
  the MAINTAINERS file, an omap3 dts file and a SoC driver for mpfs
  (risc-v)"

* tag 'arm-fixes-6.11-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (50 commits)
  firmware: microchip: fix incorrect error report of programming:timeout on success
  soc: qcom: pd-mapper: Fix singleton refcount
  firmware: qcom: tzmem: disable sdm670 platform
  soc: qcom: pmic_glink: Actually communicate when remote goes down
  usb: typec: ucsi: Move unregister out of atomic section
  soc: qcom: pmic_glink: Fix race during initialization
  firmware: qcom: qseecom: remove unused functions
  firmware: qcom: tzmem: fix virtual-to-physical address conversion
  firmware: qcom: scm: Mark get_wq_ctx() as atomic call
  arm64: dts: qcom: x1e80100: Fix Adreno SMMU global interrupt
  arm64: dts: qcom: disable GPU on x1e80100 by default
  arm64: dts: imx8mm-phygate: fix typo pinctrcl-0
  arm64: dts: imx95: correct L3Cache cache-sets
  arm64: dts: imx95: correct a55 power-domains
  arm64: dts: freescale: imx93-tqma9352-mba93xxla: fix typo
  arm64: dts: freescale: imx93-tqma9352: fix CMA alloc-ranges
  ARM: dts: imx6dl-yapp43: Increase LED current to match the yapp4 HW design
  arm64: dts: imx93: update default value for snps,clk-csr
  arm64: dts: freescale: tqma9352: Fix watchdog reset
  arm64: dts: imx8mp-beacon-kit: Fix Stereo Audio on WM8962
  ...
This commit is contained in:
Linus Torvalds 2024-09-01 06:42:13 +12:00
commit 35667a2969
36 changed files with 366 additions and 176 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
.mailmap
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@ -354,6 +354,8 @@ Kenneth Westfield <quic_kwestfie@quicinc.com> <kwestfie@codeaurora.org>
Kiran Gunda <quic_kgunda@quicinc.com> <kgunda@codeaurora.org>
Kirill Tkhai <tkhai@ya.ru> <ktkhai@virtuozzo.com>
Kishon Vijay Abraham I <kishon@kernel.org> <kishon@ti.com>
Konrad Dybcio <konradybcio@kernel.org> <konrad.dybcio@linaro.org>
Konrad Dybcio <konradybcio@kernel.org> <konrad.dybcio@somainline.org>
Konstantin Khlebnikov <koct9i@gmail.com> <khlebnikov@yandex-team.ru>
Konstantin Khlebnikov <koct9i@gmail.com> <k.khlebnikov@samsung.com>
Koushik <raghavendra.koushik@neterion.com>

9
MAINTAINERS
View File

@ -2539,8 +2539,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Supported
W: http://www.linux4sam.org
T: git git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux.git
F: arch/arm/boot/dts/microchip/at91*
F: arch/arm/boot/dts/microchip/sama*
F: arch/arm/boot/dts/microchip/
F: arch/arm/include/debug/at91.S
F: arch/arm/mach-at91/
F: drivers/memory/atmel*
@ -2749,7 +2748,7 @@ F: include/linux/soc/qcom/
ARM/QUALCOMM SUPPORT
M: Bjorn Andersson <andersson@kernel.org>
M: Konrad Dybcio <konrad.dybcio@linaro.org>
M: Konrad Dybcio <konradybcio@kernel.org>
L: linux-arm-msm@vger.kernel.org
S: Maintained
T: git git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git
@ -7112,7 +7111,7 @@ F: drivers/gpu/drm/tiny/panel-mipi-dbi.c
DRM DRIVER for Qualcomm Adreno GPUs
M: Rob Clark <robdclark@gmail.com>
R: Sean Paul <sean@poorly.run>
R: Konrad Dybcio <konrad.dybcio@linaro.org>
R: Konrad Dybcio <konradybcio@kernel.org>
L: linux-arm-msm@vger.kernel.org
L: dri-devel@lists.freedesktop.org
L: freedreno@lists.freedesktop.org
@ -18800,7 +18799,7 @@ F: include/uapi/drm/qaic_accel.h
QUALCOMM CORE POWER REDUCTION (CPR) AVS DRIVER
M: Bjorn Andersson <andersson@kernel.org>
M: Konrad Dybcio <konrad.dybcio@linaro.org>
M: Konrad Dybcio <konradybcio@kernel.org>
L: linux-pm@vger.kernel.org
L: linux-arm-msm@vger.kernel.org
S: Maintained

12
arch/arm/boot/dts/nxp/imx/imx6dl-yapp43-common.dtsi
View File

@ -274,24 +274,24 @@
led@0 {
chan-name = "R";
led-cur = /bits/ 8 <0x20>;
max-cur = /bits/ 8 <0x60>;
led-cur = /bits/ 8 <0x6e>;
max-cur = /bits/ 8 <0xc8>;
reg = <0>;
color = <LED_COLOR_ID_RED>;
};
led@1 {
chan-name = "G";
led-cur = /bits/ 8 <0x20>;
max-cur = /bits/ 8 <0x60>;
led-cur = /bits/ 8 <0xbe>;
max-cur = /bits/ 8 <0xc8>;
reg = <1>;
color = <LED_COLOR_ID_GREEN>;
};
led@2 {
chan-name = "B";
led-cur = /bits/ 8 <0x20>;
max-cur = /bits/ 8 <0x60>;
led-cur = /bits/ 8 <0xbe>;
max-cur = /bits/ 8 <0xc8>;
reg = <2>;
color = <LED_COLOR_ID_BLUE>;
};

2
arch/arm/boot/dts/ti/omap/omap3-n900.dts
View File

@ -781,7 +781,7 @@
mount-matrix = "-1", "0", "0",
"0", "1", "0",
"0", "0", "1";
"0", "0", "-1";
};
cam1: camera@3e {

2
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
View File

@ -175,7 +175,7 @@
};
};
core-cluster-thermal {
cluster-thermal {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = <&tmu 1>;

2
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
View File

@ -214,7 +214,7 @@
};
};
core-cluster-thermal {
cluster-thermal {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = <&tmu 3>;

2
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
View File

@ -182,7 +182,7 @@
};
};
core-cluster-thermal {
cluster-thermal {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = <&tmu 3>;

2
arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
View File

@ -131,7 +131,7 @@
};
thermal-zones {
core-cluster-thermal {
cluster-thermal {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = <&tmu 0>;

8
arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
View File

@ -122,7 +122,7 @@
};
};
core-cluster1-thermal {
cluster1-thermal {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = <&tmu 4>;
@ -151,7 +151,7 @@
};
};
core-cluster2-thermal {
cluster2-thermal {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = <&tmu 5>;
@ -180,7 +180,7 @@
};
};
core-cluster3-thermal {
cluster3-thermal {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = <&tmu 6>;
@ -209,7 +209,7 @@
};
};
core-cluster4-thermal {
cluster4-thermal {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = <&tmu 7>;

2
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
View File

@ -492,7 +492,7 @@
};
};
ddr-cluster5-thermal {
ddr-ctrl5-thermal {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = <&tmu 1>;

2
arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l-rs232-rs232.dtso
View File

@ -21,7 +21,7 @@
&gpio3 {
pinctrl-names = "default";
pinctrcl-0 = <&pinctrl_gpio3_hog>;
pinctrl-0 = <&pinctrl_gpio3_hog>;
uart4_rs485_en {
gpio-hog;

2
arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l-rs232-rs485.dtso
View File

@ -22,7 +22,7 @@
&gpio3 {
pinctrl-names = "default";
pinctrcl-0 = <&pinctrl_gpio3_hog>;
pinctrl-0 = <&pinctrl_gpio3_hog>;
uart4_rs485_en {
gpio-hog;

12
arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts
View File

@ -211,13 +211,12 @@
simple-audio-card,cpu {
sound-dai = <&sai3>;
frame-master;
bitclock-master;
};
simple-audio-card,codec {
sound-dai = <&wm8962>;
clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO1>;
frame-master;
bitclock-master;
};
};
};
@ -507,10 +506,9 @@
&sai3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
assigned-clocks = <&clk IMX8MP_CLK_SAI3>,
<&clk IMX8MP_AUDIO_PLL2> ;
assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL2_OUT>;
assigned-clock-rates = <12288000>, <361267200>;
assigned-clocks = <&clk IMX8MP_CLK_SAI3>;
assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
assigned-clock-rates = <12288000>;
fsl,sai-mclk-direction-output;
status = "okay";
};

2
arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts
View File

@ -499,7 +499,7 @@
pinctrl-0 = <&pinctrl_usdhc2_hs>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_uhs>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_uhs>, <&pinctrl_usdhc2_gpio>;
cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;
cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_usdhc2_vmmc>;
bus-width = <4>;
no-sdio;

3
arch/arm64/boot/dts/freescale/imx93-tqma9352.dtsi
View File

@ -19,7 +19,7 @@
linux,cma {
compatible = "shared-dma-pool";
reusable;
alloc-ranges = <0 0x60000000 0 0x40000000>;
alloc-ranges = <0 0x80000000 0 0x40000000>;
size = <0 0x10000000>;
linux,cma-default;
};
@ -156,6 +156,7 @@
&wdog3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};

2
arch/arm64/boot/dts/freescale/imx93.dtsi
View File

@ -1105,7 +1105,7 @@
<&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>;
assigned-clock-rates = <100000000>, <250000000>;
intf_mode = <&wakeupmix_gpr 0x28>;
snps,clk-csr = <0>;
snps,clk-csr = <6>;
nvmem-cells = <&eth_mac2>;
nvmem-cell-names = "mac-address";
status = "disabled";

14
arch/arm64/boot/dts/freescale/imx95.dtsi
View File

@ -27,7 +27,7 @@
reg = <0x0>;
enable-method = "psci";
#cooling-cells = <2>;
power-domains = <&scmi_devpd IMX95_PERF_A55>;
power-domains = <&scmi_perf IMX95_PERF_A55>;
power-domain-names = "perf";
i-cache-size = <32768>;
i-cache-line-size = <64>;
@ -44,7 +44,7 @@
reg = <0x100>;
enable-method = "psci";
#cooling-cells = <2>;
power-domains = <&scmi_devpd IMX95_PERF_A55>;
power-domains = <&scmi_perf IMX95_PERF_A55>;
power-domain-names = "perf";
i-cache-size = <32768>;
i-cache-line-size = <64>;
@ -61,7 +61,7 @@
reg = <0x200>;
enable-method = "psci";
#cooling-cells = <2>;
power-domains = <&scmi_devpd IMX95_PERF_A55>;
power-domains = <&scmi_perf IMX95_PERF_A55>;
power-domain-names = "perf";
i-cache-size = <32768>;
i-cache-line-size = <64>;
@ -78,7 +78,7 @@
reg = <0x300>;
enable-method = "psci";
#cooling-cells = <2>;
power-domains = <&scmi_devpd IMX95_PERF_A55>;
power-domains = <&scmi_perf IMX95_PERF_A55>;
power-domain-names = "perf";
i-cache-size = <32768>;
i-cache-line-size = <64>;
@ -93,7 +93,7 @@
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x400>;
power-domains = <&scmi_devpd IMX95_PERF_A55>;
power-domains = <&scmi_perf IMX95_PERF_A55>;
power-domain-names = "perf";
enable-method = "psci";
#cooling-cells = <2>;
@ -110,7 +110,7 @@
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x500>;
power-domains = <&scmi_devpd IMX95_PERF_A55>;
power-domains = <&scmi_perf IMX95_PERF_A55>;
power-domain-names = "perf";
enable-method = "psci";
#cooling-cells = <2>;
@ -187,7 +187,7 @@
compatible = "cache";
cache-size = <524288>;
cache-line-size = <64>;
cache-sets = <1024>;
cache-sets = <512>;
cache-level = <3>;
cache-unified;
};

4
arch/arm64/boot/dts/qcom/ipq5332.dtsi
View File

@ -320,8 +320,8 @@
reg = <0x08af8800 0x400>;
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 53 IRQ_TYPE_EDGE_BOTH>,
<GIC_SPI 52 IRQ_TYPE_EDGE_BOTH>;
<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pwr_event",
"dp_hs_phy_irq",
"dm_hs_phy_irq";

42
arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts
View File

@ -278,6 +278,13 @@
vdd-l3-supply = <&vreg_s1f_0p7>;
vdd-s1-supply = <&vph_pwr>;
vdd-s2-supply = <&vph_pwr>;
vreg_l3i_0p8: ldo3 {
regulator-name = "vreg_l3i_0p8";
regulator-min-microvolt = <880000>;
regulator-max-microvolt = <920000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
regulators-7 {
@ -423,11 +430,17 @@
};
&pcie4 {
perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie4_default>;
pinctrl-names = "default";
status = "okay";
};
&pcie4_phy {
vdda-phy-supply = <&vreg_l3j_0p8>;
vdda-phy-supply = <&vreg_l3i_0p8>;
vdda-pll-supply = <&vreg_l3e_1p2>;
status = "okay";
@ -517,7 +530,30 @@
bias-disable;
};
pcie6a_default: pcie2a-default-state {
pcie4_default: pcie4-default-state {
clkreq-n-pins {
pins = "gpio147";
function = "pcie4_clk";
drive-strength = <2>;
bias-pull-up;
};
perst-n-pins {
pins = "gpio146";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
wake-n-pins {
pins = "gpio148";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
pcie6a_default: pcie6a-default-state {
clkreq-n-pins {
pins = "gpio153";
function = "pcie6a_clk";
@ -529,7 +565,7 @@
pins = "gpio152";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
bias-disable;
};
wake-n-pins {

60
arch/arm64/boot/dts/qcom/x1e80100-crd.dts
View File

@ -268,7 +268,6 @@
pinctrl-0 = <&edp_reg_en>;
pinctrl-names = "default";
regulator-always-on;
regulator-boot-on;
};
@ -637,6 +636,14 @@
};
};
&gpu {
status = "okay";
zap-shader {
firmware-name = "qcom/x1e80100/gen70500_zap.mbn";
};
};
&i2c0 {
clock-frequency = <400000>;
@ -724,9 +731,13 @@
aux-bus {
panel {
compatible = "edp-panel";
compatible = "samsung,atna45af01", "samsung,atna33xc20";
enable-gpios = <&pmc8380_3_gpios 4 GPIO_ACTIVE_HIGH>;
power-supply = <&vreg_edp_3p3>;
pinctrl-0 = <&edp_bl_en>;
pinctrl-names = "default";
port {
edp_panel_in: endpoint {
remote-endpoint = <&mdss_dp3_out>;
@ -756,11 +767,17 @@
};
&pcie4 {
perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie4_default>;
pinctrl-names = "default";
status = "okay";
};
&pcie4_phy {
vdda-phy-supply = <&vreg_l3j_0p8>;
vdda-phy-supply = <&vreg_l3i_0p8>;
vdda-pll-supply = <&vreg_l3e_1p2>;
status = "okay";
@ -785,6 +802,16 @@
status = "okay";
};
&pmc8380_3_gpios {
edp_bl_en: edp-bl-en-state {
pins = "gpio4";
function = "normal";
power-source = <1>; /* 1.8V */
input-disable;
output-enable;
};
};
&qupv3_0 {
status = "okay";
};
@ -931,7 +958,30 @@
bias-disable;
};
pcie6a_default: pcie2a-default-state {
pcie4_default: pcie4-default-state {
clkreq-n-pins {
pins = "gpio147";
function = "pcie4_clk";
drive-strength = <2>;
bias-pull-up;
};
perst-n-pins {
pins = "gpio146";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
wake-n-pins {
pins = "gpio148";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
pcie6a_default: pcie6a-default-state {
clkreq-n-pins {
pins = "gpio153";
function = "pcie6a_clk";
@ -943,7 +993,7 @@
pins = "gpio152";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
bias-disable;
};
wake-n-pins {

44
arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts
View File

@ -625,16 +625,31 @@
};
&pcie4 {
perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie4_default>;
pinctrl-names = "default";
status = "okay";
};
&pcie4_phy {
vdda-phy-supply = <&vreg_l3j_0p8>;
vdda-phy-supply = <&vreg_l3i_0p8>;
vdda-pll-supply = <&vreg_l3e_1p2>;
status = "okay";
};
&pcie4_port0 {
wifi@0 {
compatible = "pci17cb,1107";
reg = <0x10000 0x0 0x0 0x0 0x0>;
qcom,ath12k-calibration-variant = "LES790";
};
};
&pcie6a {
perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
@ -782,7 +797,30 @@
bias-disable;
};
pcie6a_default: pcie2a-default-state {
pcie4_default: pcie4-default-state {
clkreq-n-pins {
pins = "gpio147";
function = "pcie4_clk";
drive-strength = <2>;
bias-pull-up;
};
perst-n-pins {
pins = "gpio146";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
wake-n-pins {
pins = "gpio148";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
pcie6a_default: pcie6a-default-state {
clkreq-n-pins {
pins = "gpio153";
function = "pcie6a_clk";
@ -794,7 +832,7 @@
pins = "gpio152";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
bias-disable;
};
wake-n-pins {

43
arch/arm64/boot/dts/qcom/x1e80100-qcp.dts
View File

@ -606,6 +606,14 @@
};
};
&gpu {
status = "okay";
zap-shader {
firmware-name = "qcom/x1e80100/gen70500_zap.mbn";
};
};
&lpass_tlmm {
spkr_01_sd_n_active: spkr-01-sd-n-active-state {
pins = "gpio12";
@ -660,11 +668,17 @@
};
&pcie4 {
perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie4_default>;
pinctrl-names = "default";
status = "okay";
};
&pcie4_phy {
vdda-phy-supply = <&vreg_l3j_0p8>;
vdda-phy-supply = <&vreg_l3i_0p8>;
vdda-pll-supply = <&vreg_l3e_1p2>;
status = "okay";
@ -804,7 +818,30 @@
bias-disable;
};
pcie6a_default: pcie2a-default-state {
pcie4_default: pcie4-default-state {
clkreq-n-pins {
pins = "gpio147";
function = "pcie4_clk";
drive-strength = <2>;
bias-pull-up;
};
perst-n-pins {
pins = "gpio146";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
wake-n-pins {
pins = "gpio148";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
pcie6a_default: pcie6a-default-state {
clkreq-n-pins {
pins = "gpio153";
function = "pcie6a_clk";
@ -816,7 +853,7 @@
pins = "gpio152";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
bias-disable;
};
wake-n-pins {

21
arch/arm64/boot/dts/qcom/x1e80100.dtsi
View File

@ -2901,7 +2901,7 @@
dma-coherent;
linux,pci-domain = <7>;
linux,pci-domain = <6>;
num-lanes = <2>;
interrupts = <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,
@ -2959,6 +2959,7 @@
"link_down";
power-domains = <&gcc GCC_PCIE_6A_GDSC>;
required-opps = <&rpmhpd_opp_nom>;
phys = <&pcie6a_phy>;
phy-names = "pciephy";
@ -3022,7 +3023,7 @@
dma-coherent;
linux,pci-domain = <5>;
linux,pci-domain = <4>;
num-lanes = <2>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
@ -3080,11 +3081,22 @@
"link_down";
power-domains = <&gcc GCC_PCIE_4_GDSC>;
required-opps = <&rpmhpd_opp_nom>;
phys = <&pcie4_phy>;
phy-names = "pciephy";
status = "disabled";
pcie4_port0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
};
};
pcie4_phy: phy@1c0e000 {
@ -3155,9 +3167,10 @@
interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "gfx-mem";
status = "disabled";
zap-shader {
memory-region = <&gpu_microcode_mem>;
firmware-name = "qcom/gen70500_zap.mbn";
};
gpu_opp_table: opp-table {
@ -3288,7 +3301,7 @@
reg = <0x0 0x03da0000 0x0 0x40000>;
#iommu-cells = <2>;
#global-interrupts = <1>;
interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,

1
arch/arm64/configs/defconfig
View File

@ -887,6 +887,7 @@ CONFIG_DRM_PANEL_KHADAS_TS050=m
CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m
CONFIG_DRM_PANEL_NOVATEK_NT36672E=m
CONFIG_DRM_PANEL_RAYDIUM_RM67191=m
CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20=m
CONFIG_DRM_PANEL_SITRONIX_ST7703=m
CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m
CONFIG_DRM_PANEL_VISIONOX_VTDR6130=m

2
drivers/firmware/microchip/mpfs-auto-update.c
View File

@ -166,7 +166,7 @@ static enum fw_upload_err mpfs_auto_update_poll_complete(struct fw_upload *fw_up
*/
ret = wait_for_completion_timeout(&priv->programming_complete,
msecs_to_jiffies(AUTO_UPDATE_TIMEOUT_MS));
if (ret)
if (!ret)
return FW_UPLOAD_ERR_TIMEOUT;
return FW_UPLOAD_ERR_NONE;

2
drivers/firmware/qcom/qcom_scm-smc.c
View File

@ -73,7 +73,7 @@ int scm_get_wq_ctx(u32 *wq_ctx, u32 *flags, u32 *more_pending)
struct arm_smccc_res get_wq_res;
struct arm_smccc_args get_wq_ctx = {0};
get_wq_ctx.args[0] = ARM_SMCCC_CALL_VAL(ARM_SMCCC_STD_CALL,
get_wq_ctx.args[0] = ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL,
ARM_SMCCC_SMC_64, ARM_SMCCC_OWNER_SIP,
SCM_SMC_FNID(QCOM_SCM_SVC_WAITQ, QCOM_SCM_WAITQ_GET_WQ_CTX));

33
drivers/firmware/qcom/qcom_tzmem.c
View File

@ -40,7 +40,6 @@ struct qcom_tzmem_pool {
};
struct qcom_tzmem_chunk {
phys_addr_t paddr;
size_t size;
struct qcom_tzmem_pool *owner;
};
@ -78,6 +77,7 @@ static bool qcom_tzmem_using_shm_bridge;
/* List of machines that are known to not support SHM bridge correctly. */
static const char *const qcom_tzmem_blacklist[] = {
"qcom,sc8180x",
"qcom,sdm670", /* failure in GPU firmware loading */
"qcom,sdm845", /* reset in rmtfs memory assignment */
"qcom,sm8150", /* reset in rmtfs memory assignment */
NULL
@ -385,7 +385,6 @@ again:
return NULL;
}
chunk->paddr = gen_pool_virt_to_phys(pool->genpool, vaddr);
chunk->size = size;
chunk->owner = pool;
@ -431,25 +430,37 @@ void qcom_tzmem_free(void *vaddr)
EXPORT_SYMBOL_GPL(qcom_tzmem_free);
/**
* qcom_tzmem_to_phys() - Map the virtual address of a TZ buffer to physical.
* @vaddr: Virtual address of the buffer allocated from a TZ memory pool.
* qcom_tzmem_to_phys() - Map the virtual address of TZ memory to physical.
* @vaddr: Virtual address of memory allocated from a TZ memory pool.
*
* Can be used in any context. The address must have been returned by a call
* to qcom_tzmem_alloc().
* Can be used in any context. The address must point to memory allocated
* using qcom_tzmem_alloc().
*
* Returns: Physical address of the buffer.
* Returns:
* Physical address mapped from the virtual or 0 if the mapping failed.
*/
phys_addr_t qcom_tzmem_to_phys(void *vaddr)
{
struct qcom_tzmem_chunk *chunk;
struct radix_tree_iter iter;
void __rcu **slot;
phys_addr_t ret;
guard(spinlock_irqsave)(&qcom_tzmem_chunks_lock);
chunk = radix_tree_lookup(&qcom_tzmem_chunks, (unsigned long)vaddr);
if (!chunk)
return 0;
radix_tree_for_each_slot(slot, &qcom_tzmem_chunks, &iter, 0) {
chunk = radix_tree_deref_slot_protected(slot,
&qcom_tzmem_chunks_lock);
return chunk->paddr;
ret = gen_pool_virt_to_phys(chunk->owner->genpool,
(unsigned long)vaddr);
if (ret == -1)
continue;
return ret;
}
return 0;
}
EXPORT_SYMBOL_GPL(qcom_tzmem_to_phys);

10
drivers/power/supply/qcom_battmgr.c
View File

@ -1387,12 +1387,16 @@ static int qcom_battmgr_probe(struct auxiliary_device *adev,
"failed to register wireless charing power supply\n");
}
battmgr->client = devm_pmic_glink_register_client(dev,
PMIC_GLINK_OWNER_BATTMGR,
battmgr->client = devm_pmic_glink_client_alloc(dev, PMIC_GLINK_OWNER_BATTMGR,
qcom_battmgr_callback,
qcom_battmgr_pdr_notify,
battmgr);
return PTR_ERR_OR_ZERO(battmgr->client);
if (IS_ERR(battmgr->client))
return PTR_ERR(battmgr->client);
pmic_glink_client_register(battmgr->client);
return 0;
}
static const struct auxiliary_device_id qcom_battmgr_id_table[] = {

2
drivers/soc/qcom/Kconfig
View File

@ -77,7 +77,7 @@ config QCOM_PD_MAPPER
select QCOM_QMI_HELPERS
select QCOM_PDR_MSG
select AUXILIARY_BUS
depends on NET && QRTR
depends on NET && QRTR && (ARCH_QCOM || COMPILE_TEST)
default QCOM_RPROC_COMMON
help
The Protection Domain Mapper maps registered services to the domains

2
drivers/soc/qcom/cmd-db.c
View File

@ -349,7 +349,7 @@ static int cmd_db_dev_probe(struct platform_device *pdev)
return -EINVAL;
}
cmd_db_header = memremap(rmem->base, rmem->size, MEMREMAP_WB);
cmd_db_header = memremap(rmem->base, rmem->size, MEMREMAP_WC);
if (!cmd_db_header) {
ret = -ENOMEM;
cmd_db_header = NULL;

32
drivers/soc/qcom/pmic_glink.c
View File

@ -66,7 +66,7 @@ static void _devm_pmic_glink_release_client(struct device *dev, void *res)
spin_unlock_irqrestore(&pg->client_lock, flags);
}
struct pmic_glink_client *devm_pmic_glink_register_client(struct device *dev,
struct pmic_glink_client *devm_pmic_glink_client_alloc(struct device *dev,
unsigned int id,
void (*cb)(const void *, size_t, void *),
void (*pdr)(void *, int),
@ -74,7 +74,6 @@ struct pmic_glink_client *devm_pmic_glink_register_client(struct device *dev,
{
struct pmic_glink_client *client;
struct pmic_glink *pg = dev_get_drvdata(dev->parent);
unsigned long flags;
client = devres_alloc(_devm_pmic_glink_release_client, sizeof(*client), GFP_KERNEL);
if (!client)
@ -85,6 +84,18 @@ struct pmic_glink_client *devm_pmic_glink_register_client(struct device *dev,
client->cb = cb;
client->pdr_notify = pdr;
client->priv = priv;
INIT_LIST_HEAD(&client->node);
devres_add(dev, client);
return client;
}
EXPORT_SYMBOL_GPL(devm_pmic_glink_client_alloc);
void pmic_glink_client_register(struct pmic_glink_client *client)
{
struct pmic_glink *pg = client->pg;
unsigned long flags;
mutex_lock(&pg->state_lock);
spin_lock_irqsave(&pg->client_lock, flags);
@ -95,17 +106,22 @@ struct pmic_glink_client *devm_pmic_glink_register_client(struct device *dev,
spin_unlock_irqrestore(&pg->client_lock, flags);
mutex_unlock(&pg->state_lock);
devres_add(dev, client);
return client;
}
EXPORT_SYMBOL_GPL(devm_pmic_glink_register_client);
EXPORT_SYMBOL_GPL(pmic_glink_client_register);
int pmic_glink_send(struct pmic_glink_client *client, void *data, size_t len)
{
struct pmic_glink *pg = client->pg;
int ret;
return rpmsg_send(pg->ept, data, len);
mutex_lock(&pg->state_lock);
if (!pg->ept)
ret = -ECONNRESET;
else
ret = rpmsg_send(pg->ept, data, len);
mutex_unlock(&pg->state_lock);
return ret;
}
EXPORT_SYMBOL_GPL(pmic_glink_send);
@ -175,7 +191,7 @@ static void pmic_glink_state_notify_clients(struct pmic_glink *pg)
if (pg->pdr_state == SERVREG_SERVICE_STATE_UP && pg->ept)
new_state = SERVREG_SERVICE_STATE_UP;
} else {
if (pg->pdr_state == SERVREG_SERVICE_STATE_UP && pg->ept)
if (pg->pdr_state == SERVREG_SERVICE_STATE_DOWN || !pg->ept)
new_state = SERVREG_SERVICE_STATE_DOWN;
}

9
drivers/soc/qcom/pmic_glink_altmode.c
View File

@ -520,12 +520,17 @@ static int pmic_glink_altmode_probe(struct auxiliary_device *adev,
return ret;
}
altmode->client = devm_pmic_glink_register_client(dev,
altmode->client = devm_pmic_glink_client_alloc(dev,
altmode->owner_id,
pmic_glink_altmode_callback,
pmic_glink_altmode_pdr_notify,
altmode);
return PTR_ERR_OR_ZERO(altmode->client);
if (IS_ERR(altmode->client))
return PTR_ERR(altmode->client);
pmic_glink_client_register(altmode->client);
return 0;
}
static const struct auxiliary_device_id pmic_glink_altmode_id_table[] = {

4
drivers/soc/qcom/qcom_pd_mapper.c
View File

@ -517,7 +517,7 @@ static const struct qcom_pdm_domain_data *sm8550_domains[] = {
NULL,
};
static const struct of_device_id qcom_pdm_domains[] = {
static const struct of_device_id qcom_pdm_domains[] __maybe_unused = {
{ .compatible = "qcom,apq8064", .data = NULL, },
{ .compatible = "qcom,apq8074", .data = NULL, },
{ .compatible = "qcom,apq8084", .data = NULL, },
@ -635,6 +635,8 @@ static int qcom_pdm_probe(struct auxiliary_device *auxdev,
ret = PTR_ERR(data);
else
__qcom_pdm_data = data;
} else {
refcount_inc(&__qcom_pdm_data->refcnt);
}
auxiliary_set_drvdata(auxdev, __qcom_pdm_data);

33
drivers/usb/typec/ucsi/ucsi_glink.c
View File

@ -68,6 +68,9 @@ struct pmic_glink_ucsi {
struct work_struct notify_work;
struct work_struct register_work;
spinlock_t state_lock;
bool ucsi_registered;
bool pd_running;
u8 read_buf[UCSI_BUF_SIZE];
};
@ -244,8 +247,20 @@ static void pmic_glink_ucsi_notify(struct work_struct *work)
static void pmic_glink_ucsi_register(struct work_struct *work)
{
struct pmic_glink_ucsi *ucsi = container_of(work, struct pmic_glink_ucsi, register_work);
unsigned long flags;
bool pd_running;
spin_lock_irqsave(&ucsi->state_lock, flags);
pd_running = ucsi->pd_running;
spin_unlock_irqrestore(&ucsi->state_lock, flags);
if (!ucsi->ucsi_registered && pd_running) {
ucsi_register(ucsi->ucsi);
ucsi->ucsi_registered = true;
} else if (ucsi->ucsi_registered && !pd_running) {
ucsi_unregister(ucsi->ucsi);
ucsi->ucsi_registered = false;
}
}
static void pmic_glink_ucsi_callback(const void *data, size_t len, void *priv)
@ -269,11 +284,12 @@ static void pmic_glink_ucsi_callback(const void *data, size_t len, void *priv)
static void pmic_glink_ucsi_pdr_notify(void *priv, int state)
{
struct pmic_glink_ucsi *ucsi = priv;
unsigned long flags;
if (state == SERVREG_SERVICE_STATE_UP)
spin_lock_irqsave(&ucsi->state_lock, flags);
ucsi->pd_running = (state == SERVREG_SERVICE_STATE_UP);
spin_unlock_irqrestore(&ucsi->state_lock, flags);
schedule_work(&ucsi->register_work);
else if (state == SERVREG_SERVICE_STATE_DOWN)
ucsi_unregister(ucsi->ucsi);
}
static void pmic_glink_ucsi_destroy(void *data)
@ -320,6 +336,7 @@ static int pmic_glink_ucsi_probe(struct auxiliary_device *adev,
INIT_WORK(&ucsi->register_work, pmic_glink_ucsi_register);
init_completion(&ucsi->read_ack);
init_completion(&ucsi->write_ack);
spin_lock_init(&ucsi->state_lock);
mutex_init(&ucsi->lock);
ucsi->ucsi = ucsi_create(dev, &pmic_glink_ucsi_ops);
@ -367,12 +384,16 @@ static int pmic_glink_ucsi_probe(struct auxiliary_device *adev,
ucsi->port_orientation[port] = desc;
}
ucsi->client = devm_pmic_glink_register_client(dev,
PMIC_GLINK_OWNER_USBC,
ucsi->client = devm_pmic_glink_client_alloc(dev, PMIC_GLINK_OWNER_USBC,
pmic_glink_ucsi_callback,
pmic_glink_ucsi_pdr_notify,
ucsi);
return PTR_ERR_OR_ZERO(ucsi->client);
if (IS_ERR(ucsi->client))
return PTR_ERR(ucsi->client);
pmic_glink_client_register(ucsi->client);
return 0;
}
static void pmic_glink_ucsi_remove(struct auxiliary_device *adev)

45
include/linux/firmware/qcom/qcom_qseecom.h
View File

@ -25,51 +25,6 @@ struct qseecom_client {
u32 app_id;
};
/**
* qseecom_scm_dev() - Get the SCM device associated with the QSEECOM client.
* @client: The QSEECOM client device.
*
* Returns the SCM device under which the provided QSEECOM client device
* operates. This function is intended to be used for DMA allocations.
*/
static inline struct device *qseecom_scm_dev(struct qseecom_client *client)
{
return client->aux_dev.dev.parent->parent;
}
/**
* qseecom_dma_alloc() - Allocate DMA memory for a QSEECOM client.
* @client: The QSEECOM client to allocate the memory for.
* @size: The number of bytes to allocate.
* @dma_handle: Pointer to where the DMA address should be stored.
* @gfp: Allocation flags.
*
* Wrapper function for dma_alloc_coherent(), allocating DMA memory usable for
* TZ/QSEECOM communication. Refer to dma_alloc_coherent() for details.
*/
static inline void *qseecom_dma_alloc(struct qseecom_client *client, size_t size,
dma_addr_t *dma_handle, gfp_t gfp)
{
return dma_alloc_coherent(qseecom_scm_dev(client), size, dma_handle, gfp);
}
/**
* dma_free_coherent() - Free QSEECOM DMA memory.
* @client: The QSEECOM client for which the memory has been allocated.
* @size: The number of bytes allocated.
* @cpu_addr: Virtual memory address to free.
* @dma_handle: DMA memory address to free.
*
* Wrapper function for dma_free_coherent(), freeing memory previously
* allocated with qseecom_dma_alloc(). Refer to dma_free_coherent() for
* details.
*/
static inline void qseecom_dma_free(struct qseecom_client *client, size_t size,
void *cpu_addr, dma_addr_t dma_handle)
{
return dma_free_coherent(qseecom_scm_dev(client), size, cpu_addr, dma_handle);
}
/**
* qcom_qseecom_app_send() - Send to and receive data from a given QSEE app.
* @client: The QSEECOM client associated with the target app.

3
include/linux/soc/qcom/pmic_glink.h
View File

@ -23,10 +23,11 @@ struct pmic_glink_hdr {
int pmic_glink_send(struct pmic_glink_client *client, void *data, size_t len);
struct pmic_glink_client *devm_pmic_glink_register_client(struct device *dev,
struct pmic_glink_client *devm_pmic_glink_client_alloc(struct device *dev,
unsigned int id,
void (*cb)(const void *, size_t, void *),
void (*pdr)(void *, int),
void *priv);
void pmic_glink_client_register(struct pmic_glink_client *client);
#endif