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mt76x0: phy: introduce tssi calibration support
Run mt76x0 tssi calibration process if enabled in eeprom data. Perform calibration procedure every 4s Signed-off-by: Lorenzo Bianconi <lorenzo.bianconi@redhat.com> Signed-off-by: Felix Fietkau <nbd@nbd.name>
This commit is contained in:
Lorenzo Bianconi
Felix Fietkau
parent
693792ec55
commit
3548a9dd2d
@ -503,6 +503,345 @@ mt76x0_phy_bbp_set_bw(struct mt76x02_dev *dev, enum nl80211_chan_width width)
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mt76x02_mcu_function_select(dev, BW_SETTING, bw, false);
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}
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static void mt76x0_phy_tssi_dc_calibrate(struct mt76x02_dev *dev)
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{
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struct ieee80211_channel *chan = dev->mt76.chandef.chan;
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u32 val;
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if (chan->band == NL80211_BAND_5GHZ)
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mt76x0_rf_clear(dev, MT_RF(0, 67), 0xf);
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/* bypass ADDA control */
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mt76_wr(dev, MT_RF_SETTING_0, 0x60002237);
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mt76_wr(dev, MT_RF_BYPASS_0, 0xffffffff);
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/* bbp sw reset */
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mt76_set(dev, MT_BBP(CORE, 4), BIT(0));
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usleep_range(500, 1000);
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mt76_clear(dev, MT_BBP(CORE, 4), BIT(0));
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val = (chan->band == NL80211_BAND_5GHZ) ? 0x80055 : 0x80050;
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mt76_wr(dev, MT_BBP(CORE, 34), val);
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/* enable TX with DAC0 input */
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mt76_wr(dev, MT_BBP(TXBE, 6), BIT(31));
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mt76_poll_msec(dev, MT_BBP(CORE, 34), BIT(4), 0, 200);
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dev->cal.tssi_dc = mt76_rr(dev, MT_BBP(CORE, 35)) & 0xff;
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/* stop bypass ADDA */
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mt76_wr(dev, MT_RF_BYPASS_0, 0);
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/* stop TX */
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mt76_wr(dev, MT_BBP(TXBE, 6), 0);
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/* bbp sw reset */
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mt76_set(dev, MT_BBP(CORE, 4), BIT(0));
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usleep_range(500, 1000);
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mt76_clear(dev, MT_BBP(CORE, 4), BIT(0));
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if (chan->band == NL80211_BAND_5GHZ)
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mt76x0_rf_rmw(dev, MT_RF(0, 67), 0xf, 0x4);
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}
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static int
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mt76x0_phy_tssi_adc_calibrate(struct mt76x02_dev *dev, s16 *ltssi,
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u8 *info)
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{
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struct ieee80211_channel *chan = dev->mt76.chandef.chan;
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u32 val;
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val = (chan->band == NL80211_BAND_5GHZ) ? 0x80055 : 0x80050;
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mt76_wr(dev, MT_BBP(CORE, 34), val);
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if (!mt76_poll_msec(dev, MT_BBP(CORE, 34), BIT(4), 0, 200)) {
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mt76_clear(dev, MT_BBP(CORE, 34), BIT(4));
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return -ETIMEDOUT;
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}
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*ltssi = mt76_rr(dev, MT_BBP(CORE, 35)) & 0xff;
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if (chan->band == NL80211_BAND_5GHZ)
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*ltssi += 128;
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/* set packet info#1 mode */
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mt76_wr(dev, MT_BBP(CORE, 34), 0x80041);
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info[0] = mt76_rr(dev, MT_BBP(CORE, 35)) & 0xff;
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/* set packet info#2 mode */
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mt76_wr(dev, MT_BBP(CORE, 34), 0x80042);
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info[1] = mt76_rr(dev, MT_BBP(CORE, 35)) & 0xff;
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/* set packet info#3 mode */
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mt76_wr(dev, MT_BBP(CORE, 34), 0x80043);
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info[2] = mt76_rr(dev, MT_BBP(CORE, 35)) & 0xff;
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return 0;
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}
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static u8 mt76x0_phy_get_rf_pa_mode(struct mt76x02_dev *dev,
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int index, u8 tx_rate)
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{
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u32 val, reg;
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reg = (index == 1) ? MT_RF_PA_MODE_CFG1 : MT_RF_PA_MODE_CFG0;
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val = mt76_rr(dev, reg);
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return (val & (3 << (tx_rate * 2))) >> (tx_rate * 2);
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}
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static int
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mt76x0_phy_get_target_power(struct mt76x02_dev *dev, u8 tx_mode,
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u8 *info, s8 *target_power,
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s8 *target_pa_power)
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{
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u8 tx_rate, cur_power;
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cur_power = mt76_rr(dev, MT_TX_ALC_CFG_0) & MT_TX_ALC_CFG_0_CH_INIT_0;
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switch (tx_mode) {
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case 0:
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/* cck rates */
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tx_rate = (info[0] & 0x60) >> 5;
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if (tx_rate > 3)
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return -EINVAL;
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*target_power = cur_power + dev->mt76.rate_power.cck[tx_rate];
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*target_pa_power = mt76x0_phy_get_rf_pa_mode(dev, 0, tx_rate);
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break;
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case 1: {
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u8 index;
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/* ofdm rates */
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tx_rate = (info[0] & 0xf0) >> 4;
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switch (tx_rate) {
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case 0xb:
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index = 0;
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break;
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case 0xf:
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index = 1;
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break;
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case 0xa:
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index = 2;
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break;
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case 0xe:
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index = 3;
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break;
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case 0x9:
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index = 4;
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break;
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case 0xd:
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index = 5;
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break;
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case 0x8:
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index = 6;
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break;
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case 0xc:
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index = 7;
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break;
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default:
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return -EINVAL;
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}
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*target_power = cur_power + dev->mt76.rate_power.ofdm[index];
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*target_pa_power = mt76x0_phy_get_rf_pa_mode(dev, 0, index + 4);
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break;
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}
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case 4:
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/* vht rates */
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tx_rate = info[1] & 0xf;
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if (tx_rate > 9)
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return -EINVAL;
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*target_power = cur_power + dev->mt76.rate_power.vht[tx_rate];
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*target_pa_power = mt76x0_phy_get_rf_pa_mode(dev, 1, tx_rate);
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break;
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default:
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/* ht rates */
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tx_rate = info[1] & 0x7f;
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if (tx_rate > 9)
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return -EINVAL;
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*target_power = cur_power + dev->mt76.rate_power.ht[tx_rate];
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*target_pa_power = mt76x0_phy_get_rf_pa_mode(dev, 1, tx_rate);
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break;
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}
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return 0;
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}
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static s16 mt76x0_phy_lin2db(u16 val)
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{
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u32 mantissa = val << 4;
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int ret, data;
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s16 exp = -4;
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while (mantissa < BIT(15)) {
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mantissa <<= 1;
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if (--exp < -20)
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return -10000;
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}
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while (mantissa > 0xffff) {
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mantissa >>= 1;
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if (++exp > 20)
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return -10000;
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}
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/* s(15,0) */
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if (mantissa <= 47104)
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data = mantissa + (mantissa >> 3) + (mantissa >> 4) - 38400;
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else
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data = mantissa - (mantissa >> 3) - (mantissa >> 6) - 23040;
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data = max_t(int, 0, data);
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ret = ((15 + exp) << 15) + data;
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ret = (ret << 2) + (ret << 1) + (ret >> 6) + (ret >> 7);
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return ret >> 10;
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}
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static int
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mt76x0_phy_get_delta_power(struct mt76x02_dev *dev, u8 tx_mode,
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s8 target_power, s8 target_pa_power,
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s16 ltssi)
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{
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struct ieee80211_channel *chan = dev->mt76.chandef.chan;
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int tssi_target = target_power << 12, tssi_slope;
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int tssi_offset, tssi_db, ret;
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u32 data;
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u16 val;
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if (chan->band == NL80211_BAND_5GHZ) {
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u8 bound[7];
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int i, err;
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err = mt76x02_eeprom_copy(dev, MT_EE_TSSI_BOUND1, bound,
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sizeof(bound));
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if (err < 0)
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return err;
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for (i = 0; i < ARRAY_SIZE(bound); i++) {
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if (chan->hw_value <= bound[i] || !bound[i])
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break;
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}
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val = mt76x02_eeprom_get(dev, MT_EE_TSSI_SLOPE_5G + i * 2);
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tssi_offset = val >> 8;
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if ((tssi_offset >= 64 && tssi_offset <= 127) ||
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(tssi_offset & BIT(7)))
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tssi_offset -= BIT(8);
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} else {
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val = mt76x02_eeprom_get(dev, MT_EE_TSSI_SLOPE_2G);
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tssi_offset = val >> 8;
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if (tssi_offset & BIT(7))
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tssi_offset -= BIT(8);
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}
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tssi_slope = val & 0xff;
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switch (target_pa_power) {
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case 1:
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if (chan->band == NL80211_BAND_2GHZ)
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tssi_target += 29491; /* 3.6 * 8192 */
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/* fall through */
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case 0:
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break;
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default:
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tssi_target += 4424; /* 0.54 * 8192 */
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break;
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}
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if (!tx_mode) {
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data = mt76_rr(dev, MT_BBP(CORE, 1));
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if (is_mt7630(dev) && mt76_is_mmio(dev)) {
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int offset;
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/* 2.3 * 8192 or 1.5 * 8192 */
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offset = (data & BIT(5)) ? 18841 : 12288;
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tssi_target += offset;
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} else if (data & BIT(5)) {
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/* 0.8 * 8192 */
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tssi_target += 6554;
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}
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}
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data = mt76_rr(dev, MT_BBP(TXBE, 4));
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switch (data & 0x3) {
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case 1:
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tssi_target -= 49152; /* -6db * 8192 */
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break;
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case 2:
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tssi_target -= 98304; /* -12db * 8192 */
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break;
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case 3:
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tssi_target += 49152; /* 6db * 8192 */
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break;
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default:
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break;
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}
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tssi_db = mt76x0_phy_lin2db(ltssi - dev->cal.tssi_dc) * tssi_slope;
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if (chan->band == NL80211_BAND_5GHZ) {
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tssi_db += ((tssi_offset - 50) << 10); /* offset s4.3 */
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tssi_target -= tssi_db;
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if (ltssi > 254 && tssi_target > 0) {
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/* upper saturate */
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tssi_target = 0;
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}
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} else {
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tssi_db += (tssi_offset << 9); /* offset s3.4 */
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tssi_target -= tssi_db;
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/* upper-lower saturate */
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if ((ltssi > 126 && tssi_target > 0) ||
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((ltssi - dev->cal.tssi_dc) < 1 && tssi_target < 0)) {
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tssi_target = 0;
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}
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}
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if ((dev->cal.tssi_target ^ tssi_target) < 0 &&
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dev->cal.tssi_target > -4096 && dev->cal.tssi_target < 4096 &&
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tssi_target > -4096 && tssi_target < 4096) {
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if ((tssi_target < 0 &&
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tssi_target + dev->cal.tssi_target > 0) ||
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(tssi_target > 0 &&
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tssi_target + dev->cal.tssi_target <= 0))
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tssi_target = 0;
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else
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dev->cal.tssi_target = tssi_target;
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} else {
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dev->cal.tssi_target = tssi_target;
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}
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/* make the compensate value to the nearest compensate code */
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if (tssi_target > 0)
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tssi_target += 2048;
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else
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tssi_target -= 2048;
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tssi_target >>= 12;
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ret = mt76_get_field(dev, MT_TX_ALC_CFG_1, MT_TX_ALC_CFG_1_TEMP_COMP);
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if (ret & BIT(5))
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ret -= BIT(6);
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ret += tssi_target;
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ret = min_t(int, 31, ret);
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return max_t(int, -32, ret);
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}
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static void mt76x0_phy_tssi_calibrate(struct mt76x02_dev *dev)
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{
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s8 target_power, target_pa_power;
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u8 tssi_info[3], tx_mode;
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s16 ltssi;
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s8 val;
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if (mt76x0_phy_tssi_adc_calibrate(dev, <ssi, tssi_info) < 0)
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return;
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tx_mode = tssi_info[0] & 0x7;
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if (mt76x0_phy_get_target_power(dev, tx_mode, tssi_info,
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&target_power, &target_pa_power) < 0)
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return;
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val = mt76x0_phy_get_delta_power(dev, tx_mode, target_power,
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target_pa_power, ltssi);
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mt76_rmw_field(dev, MT_TX_ALC_CFG_1, MT_TX_ALC_CFG_1_TEMP_COMP, val);
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}
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void mt76x0_phy_set_txpower(struct mt76x02_dev *dev)
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{
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struct mt76_rate_power *t = &dev->mt76.rate_power;
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@ -532,7 +871,15 @@ void mt76x0_phy_calibrate(struct mt76x02_dev *dev, bool power_on)
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mt76x02_mcu_calibrate(dev, MCU_CAL_VCO, chan->hw_value,
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false);
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usleep_range(10, 20);
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/* XXX: tssi */
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if (mt76x0_tssi_enabled(dev)) {
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mt76_wr(dev, MT_MAC_SYS_CTRL,
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MT_MAC_SYS_CTRL_ENABLE_RX);
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mt76x0_phy_tssi_dc_calibrate(dev);
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mt76_wr(dev, MT_MAC_SYS_CTRL,
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MT_MAC_SYS_CTRL_ENABLE_TX |
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MT_MAC_SYS_CTRL_ENABLE_RX);
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}
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}
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tx_alc = mt76_rr(dev, MT_TX_ALC_CFG_0);
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@ -759,11 +1106,13 @@ static void mt76x0_phy_calibration_work(struct work_struct *work)
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cal_work.work);
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mt76x0_phy_update_channel_gain(dev);
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if (!mt76x0_tssi_enabled(dev))
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if (mt76x0_tssi_enabled(dev))
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mt76x0_phy_tssi_calibrate(dev);
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else
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mt76x0_phy_temp_sensor(dev);
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ieee80211_queue_delayed_work(dev->mt76.hw, &dev->cal_work,
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MT_CALIBRATE_INTERVAL);
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4 * MT_CALIBRATE_INTERVAL);
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}
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static void mt76x0_rf_patch_reg_array(struct mt76x02_dev *dev,
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@ -57,6 +57,9 @@ struct mt76x02_calibration {
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bool tssi_comp_pending;
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bool dpd_cal_done;
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bool channel_cal_done;
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int tssi_target;
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s8 tssi_dc;
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};
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struct mt76x02_dev {
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@ -56,6 +56,7 @@ enum mt76x02_eeprom_field {
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#define MT_TX_POWER_GROUP_SIZE_5G 5
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#define MT_TX_POWER_GROUPS_5G 6
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MT_EE_TX_POWER_0_START_5G = 0x062,
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MT_EE_TSSI_SLOPE_2G = 0x06e,
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MT_EE_TX_POWER_0_GRP3_TX_POWER_DELTA = 0x074,
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MT_EE_TX_POWER_0_GRP4_TSSI_SLOPE = 0x076,
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@ -86,6 +87,7 @@ enum mt76x02_eeprom_field {
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MT_EE_TSSI_BOUND5 = 0x0dc,
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MT_EE_TX_POWER_BYRATE_BASE = 0x0de,
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MT_EE_TSSI_SLOPE_5G = 0x0f0,
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MT_EE_RF_TEMP_COMP_SLOPE_5G = 0x0f2,
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MT_EE_RF_TEMP_COMP_SLOPE_2G = 0x0f4,
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