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@ -976,9 +976,9 @@ void Uxx_power_on_procedure( phw_data_t pHwData )
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// 20060511.1 Fix the following 4 steps for Rx of RF 2230 initial fail
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// 20060511.1 Fix the following 4 steps for Rx of RF 2230 initial fail
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Wb35Reg_WriteSync( pHwData, 0x03d4, 0x80 );// regulator on only
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Wb35Reg_WriteSync( pHwData, 0x03d4, 0x80 );// regulator on only
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OS_SLEEP(10000); // Modify 20051221.1.b
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msleep(10); // Modify 20051221.1.b
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Wb35Reg_WriteSync( pHwData, 0x03d4, 0xb8 );// REG_ON RF_RSTN on, and
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Wb35Reg_WriteSync( pHwData, 0x03d4, 0xb8 );// REG_ON RF_RSTN on, and
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OS_SLEEP(10000); // Modify 20051221.1.b
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msleep(10); // Modify 20051221.1.b
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ltmp = 0x4968;
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ltmp = 0x4968;
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if( (pHwData->phy_type == RF_WB_242) ||
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if( (pHwData->phy_type == RF_WB_242) ||
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@ -988,12 +988,12 @@ void Uxx_power_on_procedure( phw_data_t pHwData )
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Wb35Reg_WriteSync( pHwData, 0x03d4, 0xa0 );// PLL_PD REF_PD set to 0
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Wb35Reg_WriteSync( pHwData, 0x03d4, 0xa0 );// PLL_PD REF_PD set to 0
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OS_SLEEP(20000); // Modify 20051221.1.b
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msleep(20); // Modify 20051221.1.b
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Wb35Reg_ReadSync( pHwData, 0x03d0, <mp );
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Wb35Reg_ReadSync( pHwData, 0x03d0, <mp );
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loop = 500; // Wait for 5 second 20061101
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loop = 500; // Wait for 5 second 20061101
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while( !(ltmp & 0x20) && loop-- )
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while( !(ltmp & 0x20) && loop-- )
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{
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{
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OS_SLEEP(10000); // Modify 20051221.1.b
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msleep(10); // Modify 20051221.1.b
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if( !Wb35Reg_ReadSync( pHwData, 0x03d0, <mp ) )
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if( !Wb35Reg_ReadSync( pHwData, 0x03d0, <mp ) )
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break;
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break;
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}
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}
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@ -1002,7 +1002,7 @@ void Uxx_power_on_procedure( phw_data_t pHwData )
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}
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}
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Wb35Reg_WriteSync( pHwData, 0x03b0, 1 );// Reset hardware first
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Wb35Reg_WriteSync( pHwData, 0x03b0, 1 );// Reset hardware first
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OS_SLEEP(10000); // Add this 20051221.1.b
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msleep(10); // Add this 20051221.1.b
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// Set burst write delay
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// Set burst write delay
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Wb35Reg_WriteSync( pHwData, 0x03f8, 0x7ff );
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Wb35Reg_WriteSync( pHwData, 0x03f8, 0x7ff );
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@ -1167,23 +1167,23 @@ RFSynthesizer_initial(phw_data_t pHwData)
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// 20060511.1 --- Modifying the follow step for Rx issue-----------------
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// 20060511.1 --- Modifying the follow step for Rx issue-----------------
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ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( (0x07<<20)|0xE168E, 20);
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ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( (0x07<<20)|0xE168E, 20);
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Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
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Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
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OS_SLEEP(10000);
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msleep(10);
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ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( al2230_rf_data[7], 20);
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ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( al2230_rf_data[7], 20);
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Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
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Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
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OS_SLEEP(10000);
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msleep(10);
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case RF_AIROHA_2230S: // 20060420 Add this
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case RF_AIROHA_2230S: // 20060420 Add this
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// 20060511.1 --- Modifying the follow step for Rx issue-----------------
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// 20060511.1 --- Modifying the follow step for Rx issue-----------------
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Wb35Reg_WriteSync( pHwData, 0x03d4, 0x80 );// regulator on only
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Wb35Reg_WriteSync( pHwData, 0x03d4, 0x80 );// regulator on only
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OS_SLEEP(10000); // Modify 20051221.1.b
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msleep(10); // Modify 20051221.1.b
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Wb35Reg_WriteSync( pHwData, 0x03d4, 0xa0 );// PLL_PD REF_PD set to 0
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Wb35Reg_WriteSync( pHwData, 0x03d4, 0xa0 );// PLL_PD REF_PD set to 0
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OS_SLEEP(10000); // Modify 20051221.1.b
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msleep(10); // Modify 20051221.1.b
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Wb35Reg_WriteSync( pHwData, 0x03d4, 0xe0 );// MLK_EN
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Wb35Reg_WriteSync( pHwData, 0x03d4, 0xe0 );// MLK_EN
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Wb35Reg_WriteSync( pHwData, 0x03b0, 1 );// Reset hardware first
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Wb35Reg_WriteSync( pHwData, 0x03b0, 1 );// Reset hardware first
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OS_SLEEP(10000); // Add this 20051221.1.b
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msleep(10); // Add this 20051221.1.b
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//------------------------------------------------------------------------
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//------------------------------------------------------------------------
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// The follow code doesn't use the burst-write mode
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// The follow code doesn't use the burst-write mode
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@ -1195,17 +1195,17 @@ RFSynthesizer_initial(phw_data_t pHwData)
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Wb35Reg_WriteSync( pHwData, 0x105c, ltmp );
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Wb35Reg_WriteSync( pHwData, 0x105c, ltmp );
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pHwData->Wb35Reg.BB50 |= 0x13;//(MASK_IQCAL_MODE|MASK_CALIB_START);//20060315.1 modify
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pHwData->Wb35Reg.BB50 |= 0x13;//(MASK_IQCAL_MODE|MASK_CALIB_START);//20060315.1 modify
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Wb35Reg_WriteSync( pHwData, 0x1050, pHwData->Wb35Reg.BB50);
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Wb35Reg_WriteSync( pHwData, 0x1050, pHwData->Wb35Reg.BB50);
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OS_SLEEP(5000);
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msleep(5);
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//phy_set_rf_data(phw_data, 0x0F, (0x0F<<20) | 0xF01B0); //Activate Filter Cal.
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//phy_set_rf_data(phw_data, 0x0F, (0x0F<<20) | 0xF01B0); //Activate Filter Cal.
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ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( (0x0F<<20) | 0xF01B0, 20);
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ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( (0x0F<<20) | 0xF01B0, 20);
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Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
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Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
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OS_SLEEP(5000);
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msleep(5);
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//phy_set_rf_data(phw_data, 0x0F, (0x0F<<20) | 0xF01e0); //Activate TX DCC
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//phy_set_rf_data(phw_data, 0x0F, (0x0F<<20) | 0xF01e0); //Activate TX DCC
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ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( (0x0F<<20) | 0xF01E0, 20);
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ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( (0x0F<<20) | 0xF01E0, 20);
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Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
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Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
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OS_SLEEP(5000);
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msleep(5);
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//phy_set_rf_data(phw_data, 0x0F, (0x0F<<20) | 0xF01A0); //Resotre Initial Setting
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//phy_set_rf_data(phw_data, 0x0F, (0x0F<<20) | 0xF01A0); //Resotre Initial Setting
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ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( (0x0F<<20) | 0xF01A0, 20);
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ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( (0x0F<<20) | 0xF01A0, 20);
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@ -1229,16 +1229,16 @@ RFSynthesizer_initial(phw_data_t pHwData)
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//2.4GHz
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//2.4GHz
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//ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x1ABA8F;
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//ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x1ABA8F;
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//Wb35Reg_WriteSync pHwData, 0x0864, ltmp );
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//Wb35Reg_WriteSync pHwData, 0x0864, ltmp );
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//OS_SLEEP(1000); // Sleep 1 ms
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//msleep(1); // Sleep 1 ms
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ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x9ABA8F;
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ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x9ABA8F;
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Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
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Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
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OS_SLEEP(5000);
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msleep(5);
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ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x3ABA8F;
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ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x3ABA8F;
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Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
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Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
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OS_SLEEP(5000);
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msleep(5);
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ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x1ABA8F;
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ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x1ABA8F;
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Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
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Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
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OS_SLEEP(5000);
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msleep(5);
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//5GHz
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//5GHz
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Wb35Reg_WriteSync( pHwData, 0x03dc, 0x00000000 );
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Wb35Reg_WriteSync( pHwData, 0x03dc, 0x00000000 );
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@ -1251,7 +1251,7 @@ RFSynthesizer_initial(phw_data_t pHwData)
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// Write to register. number must less and equal than 16
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// Write to register. number must less and equal than 16
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for( i=0; i<number; i++ )
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for( i=0; i<number; i++ )
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Wb35Reg_WriteSync( pHwData, 0x0864, pltmp[i] );
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Wb35Reg_WriteSync( pHwData, 0x0864, pltmp[i] );
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OS_SLEEP(5000);
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msleep(5);
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Wb35Reg_WriteSync( pHwData, 0x03dc, 0x00000080 );
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Wb35Reg_WriteSync( pHwData, 0x03dc, 0x00000080 );
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#ifdef _PE_STATE_DUMP_
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#ifdef _PE_STATE_DUMP_
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@ -1262,13 +1262,13 @@ RFSynthesizer_initial(phw_data_t pHwData)
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//Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
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//Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
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ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x9ABA8F;
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ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x9ABA8F;
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Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
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Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
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OS_SLEEP(5000);
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msleep(5);
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ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x3ABA8F;
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ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x3ABA8F;
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Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
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Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
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OS_SLEEP(5000);
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msleep(5);
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ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x12BACF;
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ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x12BACF;
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Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
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Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
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OS_SLEEP(5000);
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msleep(5);
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//Wb35Reg_WriteSync( pHwData, 0x03dc, 0x00000080 );
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//Wb35Reg_WriteSync( pHwData, 0x03dc, 0x00000080 );
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//WBDEBUG(("* PLL_ON high\n"));
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//WBDEBUG(("* PLL_ON high\n"));
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@ -1290,11 +1290,11 @@ RFSynthesizer_initial(phw_data_t pHwData)
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//Calibration (1a.0). Synthesizer reset (HTHo corrected 2005/05/10)
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//Calibration (1a.0). Synthesizer reset (HTHo corrected 2005/05/10)
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ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x0F<<24) | 0x00101E, 24);
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ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x0F<<24) | 0x00101E, 24);
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Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
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Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
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OS_SLEEP( 5000 ); // Sleep 5ms
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msleep(5); // Sleep 5ms
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//Calibration (1a). VCO frequency calibration mode ; waiting 2msec VCO calibration time
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//Calibration (1a). VCO frequency calibration mode ; waiting 2msec VCO calibration time
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ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFE69c0, 24);
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ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFE69c0, 24);
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Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
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Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
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OS_SLEEP( 2000 ); // Sleep 2ms
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msleep(2); // Sleep 2ms
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//----- Calibration (2). TX baseband Gm-C filter auto-tuning
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//----- Calibration (2). TX baseband Gm-C filter auto-tuning
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//Calibration (2a). turn off ENCAL signal
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//Calibration (2a). turn off ENCAL signal
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@ -1309,7 +1309,7 @@ RFSynthesizer_initial(phw_data_t pHwData)
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//Calibration (2c). turn-on TX Gm-C filter auto-tuning
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//Calibration (2c). turn-on TX Gm-C filter auto-tuning
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ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFCEBC0, 24);
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ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFCEBC0, 24);
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Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
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Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
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OS_SLEEP( 150 ); // Sleep 150 us
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udelay(150); // Sleep 150 us
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//turn off ENCAL signal
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//turn off ENCAL signal
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ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xF8EBC0, 24);
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ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xF8EBC0, 24);
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Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
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Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
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@ -1327,7 +1327,7 @@ RFSynthesizer_initial(phw_data_t pHwData)
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//Calibration (3c). turn-on RX Gm-C filter auto-tuning
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//Calibration (3c). turn-on RX Gm-C filter auto-tuning
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ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFEEDC0, 24);
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ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFEEDC0, 24);
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Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
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Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
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OS_SLEEP( 150 ); // Sleep 150 us
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udelay(150); // Sleep 150 us
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//Calibration (3e). turn off ENCAL signal
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//Calibration (3e). turn off ENCAL signal
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ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFAEDC0, 24);
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ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFAEDC0, 24);
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Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
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Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
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@ -1336,7 +1336,7 @@ RFSynthesizer_initial(phw_data_t pHwData)
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//Calibration (4a). TX LO leakage calibration
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//Calibration (4a). TX LO leakage calibration
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ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFD6BC0, 24);
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ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFD6BC0, 24);
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Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
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Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
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OS_SLEEP( 150 ); // Sleep 150 us
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udelay(150); // Sleep 150 us
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//----- Calibration (5). RX DC offset calibration
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//----- Calibration (5). RX DC offset calibration
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//Calibration (5a). turn off ENCAL signal and set to RX SW DC caliration mode
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//Calibration (5a). turn off ENCAL signal and set to RX SW DC caliration mode
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@ -1353,7 +1353,7 @@ RFSynthesizer_initial(phw_data_t pHwData)
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//Calibration (5d). turn on RX DC offset cal function; and waiting 2 msec cal time
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//Calibration (5d). turn on RX DC offset cal function; and waiting 2 msec cal time
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ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFF6DC0, 24);
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ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFF6DC0, 24);
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Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
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Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
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OS_SLEEP(2000); // Sleep 2ms
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msleep(2); // Sleep 2ms
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//Calibration (5f). turn off ENCAL signal
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//Calibration (5f). turn off ENCAL signal
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ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFAEDC0, 24);
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ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFAEDC0, 24);
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Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
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Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
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@ -1365,7 +1365,7 @@ RFSynthesizer_initial(phw_data_t pHwData)
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//Calibration (5d). turn on RX DC offset cal function; and waiting 2 msec cal time
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//Calibration (5d). turn on RX DC offset cal function; and waiting 2 msec cal time
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ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFF6DC0, 24);
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ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFF6DC0, 24);
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Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
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Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
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OS_SLEEP(2000); // Sleep 2ms
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msleep(2); // Sleep 2ms
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//Calibration (5f). turn off ENCAL signal
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//Calibration (5f). turn off ENCAL signal
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ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFAEDC0, 24);
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ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFAEDC0, 24);
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Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
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Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
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@ -1377,7 +1377,7 @@ RFSynthesizer_initial(phw_data_t pHwData)
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//Calibration (5d). turn on RX DC offset cal function; and waiting 2 msec cal time
|
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//Calibration (5d). turn on RX DC offset cal function; and waiting 2 msec cal time
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ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFF6DC0, 24);
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ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFF6DC0, 24);
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Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
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Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
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|
|
OS_SLEEP(2000); // Sleep 2ms
|
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|
|
msleep(2); // Sleep 2ms
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|
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|
//Calibration (5f). turn off ENCAL signal
|
|
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|
//Calibration (5f). turn off ENCAL signal
|
|
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|
ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFAEDC0, 24);
|
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ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFAEDC0, 24);
|
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Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
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Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
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|
|
@ -1389,7 +1389,7 @@ RFSynthesizer_initial(phw_data_t pHwData)
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|
//Calibration (5d). turn on RX DC offset cal function; and waiting 2 msec cal time
|
|
|
|
//Calibration (5d). turn on RX DC offset cal function; and waiting 2 msec cal time
|
|
|
|
ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFF6DC0, 24);
|
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|
ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFF6DC0, 24);
|
|
|
|
Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
|
|
|
|
Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
|
|
|
|
OS_SLEEP(2000); // Sleep 2ms
|
|
|
|
msleep(2); // Sleep 2ms
|
|
|
|
//Calibration (5f). turn off ENCAL signal
|
|
|
|
//Calibration (5f). turn off ENCAL signal
|
|
|
|
ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFAEDC0, 24);
|
|
|
|
ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFAEDC0, 24);
|
|
|
|
Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
|
|
|
|
Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
|
|
|
@ -1399,16 +1399,16 @@ RFSynthesizer_initial(phw_data_t pHwData)
|
|
|
|
|
|
|
|
|
|
|
|
//; ----- Calibration (7). Switch RF chip to normal mode
|
|
|
|
//; ----- Calibration (7). Switch RF chip to normal mode
|
|
|
|
//0x00 0xF86100 ; 3E184 ; Switch RF chip to normal mode
|
|
|
|
//0x00 0xF86100 ; 3E184 ; Switch RF chip to normal mode
|
|
|
|
// OS_SLEEP(10000); // @@ 20060721
|
|
|
|
// msleep(10); // @@ 20060721
|
|
|
|
ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xF86100, 24);
|
|
|
|
ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xF86100, 24);
|
|
|
|
Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
|
|
|
|
Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
|
|
|
|
OS_SLEEP(5000); // Sleep 5 ms
|
|
|
|
msleep(5); // Sleep 5 ms
|
|
|
|
|
|
|
|
|
|
|
|
// //write back
|
|
|
|
// //write back
|
|
|
|
// Wb35Reg_WriteSync( pHwData, 0x105c, pHwData->Wb35Reg.BB5C );
|
|
|
|
// Wb35Reg_WriteSync( pHwData, 0x105c, pHwData->Wb35Reg.BB5C );
|
|
|
|
// pHwData->Wb35Reg.BB50 &= ~0x13;//(MASK_IQCAL_MODE|MASK_CALIB_START); // 20060315.1 fix
|
|
|
|
// pHwData->Wb35Reg.BB50 &= ~0x13;//(MASK_IQCAL_MODE|MASK_CALIB_START); // 20060315.1 fix
|
|
|
|
// Wb35Reg_WriteSync( pHwData, 0x1050, pHwData->Wb35Reg.BB50);
|
|
|
|
// Wb35Reg_WriteSync( pHwData, 0x1050, pHwData->Wb35Reg.BB50);
|
|
|
|
// OS_SLEEP(1000); // Sleep 1 ms
|
|
|
|
// msleep(1); // Sleep 1 ms
|
|
|
|
break;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|