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x86/ioapic: Cleanup IO/APIC route entry structs
Having two seperate structs for the I/O-APIC RTE entries (non-remapped and
DMAR remapped) requires type casts and makes it hard to map.
Combine them in IO_APIC_routing_entry by defining a union of two 64bit
bitfields. Use naming which reflects which bits are shared and which bits
are actually different for the operating modes.
[dwmw2: Fix it up and finish the job, pulling the 32-bit w1,w2 words for
register access into the same union and eliminating a few more
places where bits were accessed through masks and shifts.]
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/r/20201024213535.443185-21-dwmw2@infradead.org
This commit is contained in:
Thomas Gleixner
parent
a27dca645d
commit
341b4a7211
@ -13,15 +13,6 @@
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* Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar
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*/
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/* I/O Unit Redirection Table */
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#define IO_APIC_REDIR_VECTOR_MASK 0x000FF
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#define IO_APIC_REDIR_DEST_LOGICAL 0x00800
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#define IO_APIC_REDIR_DEST_PHYSICAL 0x00000
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#define IO_APIC_REDIR_SEND_PENDING (1 << 12)
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#define IO_APIC_REDIR_REMOTE_IRR (1 << 14)
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#define IO_APIC_REDIR_LEVEL_TRIGGER (1 << 15)
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#define IO_APIC_REDIR_MASKED (1 << 16)
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/*
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* The structure of the IO-APIC:
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*/
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@ -65,52 +56,39 @@ union IO_APIC_reg_03 {
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};
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struct IO_APIC_route_entry {
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__u32 vector : 8,
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delivery_mode : 3, /* 000: FIXED
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* 001: lowest prio
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* 111: ExtINT
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*/
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dest_mode : 1, /* 0: physical, 1: logical */
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delivery_status : 1,
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polarity : 1,
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irr : 1,
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trigger : 1, /* 0: edge, 1: level */
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mask : 1, /* 0: enabled, 1: disabled */
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__reserved_2 : 15;
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__u32 __reserved_3 : 24,
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dest : 8;
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} __attribute__ ((packed));
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struct IR_IO_APIC_route_entry {
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__u64 vector : 8,
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zero : 3,
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index2 : 1,
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delivery_status : 1,
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polarity : 1,
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irr : 1,
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trigger : 1,
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mask : 1,
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reserved : 31,
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format : 1,
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index : 15;
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union {
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struct {
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u64 vector : 8,
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delivery_mode : 3,
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dest_mode_logical : 1,
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delivery_status : 1,
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active_low : 1,
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irr : 1,
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is_level : 1,
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masked : 1,
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reserved_0 : 15,
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reserved_1 : 24,
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destid_0_7 : 8;
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};
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struct {
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u64 ir_shared_0 : 8,
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ir_zero : 3,
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ir_index_15 : 1,
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ir_shared_1 : 5,
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ir_reserved_0 : 31,
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ir_format : 1,
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ir_index_0_14 : 15;
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};
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struct {
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u64 w1 : 32,
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w2 : 32;
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};
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};
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} __attribute__ ((packed));
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struct irq_alloc_info;
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struct ioapic_domain_cfg;
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#define IOAPIC_EDGE 0
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#define IOAPIC_LEVEL 1
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#define IOAPIC_MASKED 1
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#define IOAPIC_UNMASKED 0
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#define IOAPIC_POL_HIGH 0
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#define IOAPIC_POL_LOW 1
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#define IOAPIC_DEST_MODE_PHYSICAL 0
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#define IOAPIC_DEST_MODE_LOGICAL 1
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#define IOAPIC_MAP_ALLOC 0x1
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#define IOAPIC_MAP_CHECK 0x2
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@ -286,31 +286,26 @@ static void io_apic_write(unsigned int apic, unsigned int reg,
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writel(value, &io_apic->data);
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}
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union entry_union {
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struct { u32 w1, w2; };
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struct IO_APIC_route_entry entry;
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};
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static struct IO_APIC_route_entry __ioapic_read_entry(int apic, int pin)
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{
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union entry_union eu;
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struct IO_APIC_route_entry entry;
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eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
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eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
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entry.w1 = io_apic_read(apic, 0x10 + 2 * pin);
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entry.w2 = io_apic_read(apic, 0x11 + 2 * pin);
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return eu.entry;
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return entry;
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}
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static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
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{
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union entry_union eu;
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struct IO_APIC_route_entry entry;
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unsigned long flags;
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raw_spin_lock_irqsave(&ioapic_lock, flags);
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eu.entry = __ioapic_read_entry(apic, pin);
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entry = __ioapic_read_entry(apic, pin);
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raw_spin_unlock_irqrestore(&ioapic_lock, flags);
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return eu.entry;
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return entry;
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}
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/*
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@ -321,11 +316,8 @@ static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
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*/
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static void __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
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{
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union entry_union eu = {{0, 0}};
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eu.entry = e;
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io_apic_write(apic, 0x11 + 2*pin, eu.w2);
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io_apic_write(apic, 0x10 + 2*pin, eu.w1);
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io_apic_write(apic, 0x11 + 2*pin, e.w2);
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io_apic_write(apic, 0x10 + 2*pin, e.w1);
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}
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static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
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@ -344,12 +336,12 @@ static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
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*/
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static void ioapic_mask_entry(int apic, int pin)
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{
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struct IO_APIC_route_entry e = { .masked = true };
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unsigned long flags;
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union entry_union eu = { .entry.mask = IOAPIC_MASKED };
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raw_spin_lock_irqsave(&ioapic_lock, flags);
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io_apic_write(apic, 0x10 + 2*pin, eu.w1);
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io_apic_write(apic, 0x11 + 2*pin, eu.w2);
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io_apic_write(apic, 0x10 + 2*pin, e.w1);
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io_apic_write(apic, 0x11 + 2*pin, e.w2);
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raw_spin_unlock_irqrestore(&ioapic_lock, flags);
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}
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@ -422,20 +414,15 @@ static void __init replace_pin_at_irq_node(struct mp_chip_data *data, int node,
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add_pin_to_irq_node(data, node, newapic, newpin);
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}
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static void io_apic_modify_irq(struct mp_chip_data *data,
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int mask_and, int mask_or,
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static void io_apic_modify_irq(struct mp_chip_data *data, bool masked,
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void (*final)(struct irq_pin_list *entry))
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{
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union entry_union eu;
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struct irq_pin_list *entry;
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eu.entry = data->entry;
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eu.w1 &= mask_and;
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eu.w1 |= mask_or;
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data->entry = eu.entry;
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data->entry.masked = masked;
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for_each_irq_pin(entry, data->irq_2_pin) {
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io_apic_write(entry->apic, 0x10 + 2 * entry->pin, eu.w1);
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io_apic_write(entry->apic, 0x10 + 2 * entry->pin, data->entry.w1);
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if (final)
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final(entry);
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}
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@ -459,13 +446,13 @@ static void mask_ioapic_irq(struct irq_data *irq_data)
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unsigned long flags;
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raw_spin_lock_irqsave(&ioapic_lock, flags);
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io_apic_modify_irq(data, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
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io_apic_modify_irq(data, true, &io_apic_sync);
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raw_spin_unlock_irqrestore(&ioapic_lock, flags);
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}
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static void __unmask_ioapic(struct mp_chip_data *data)
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{
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io_apic_modify_irq(data, ~IO_APIC_REDIR_MASKED, 0, NULL);
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io_apic_modify_irq(data, false, NULL);
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}
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static void unmask_ioapic_irq(struct irq_data *irq_data)
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@ -506,8 +493,8 @@ static void __eoi_ioapic_pin(int apic, int pin, int vector)
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/*
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* Mask the entry and change the trigger mode to edge.
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*/
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entry1.mask = IOAPIC_MASKED;
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entry1.trigger = IOAPIC_EDGE;
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entry1.masked = true;
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entry1.is_level = false;
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__ioapic_write_entry(apic, pin, entry1);
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@ -542,8 +529,8 @@ static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
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* Make sure the entry is masked and re-read the contents to check
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* if it is a level triggered pin and if the remote-IRR is set.
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*/
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if (entry.mask == IOAPIC_UNMASKED) {
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entry.mask = IOAPIC_MASKED;
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if (!entry.masked) {
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entry.masked = true;
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ioapic_write_entry(apic, pin, entry);
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entry = ioapic_read_entry(apic, pin);
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}
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@ -556,8 +543,8 @@ static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
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* doesn't clear the remote-IRR if the trigger mode is not
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* set to level.
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*/
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if (entry.trigger == IOAPIC_EDGE) {
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entry.trigger = IOAPIC_LEVEL;
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if (!entry.is_level) {
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entry.is_level = true;
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ioapic_write_entry(apic, pin, entry);
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}
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raw_spin_lock_irqsave(&ioapic_lock, flags);
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@ -659,8 +646,8 @@ void mask_ioapic_entries(void)
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struct IO_APIC_route_entry entry;
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entry = ioapics[apic].saved_registers[pin];
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if (entry.mask == IOAPIC_UNMASKED) {
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entry.mask = IOAPIC_MASKED;
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if (!entry.masked) {
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entry.masked = true;
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ioapic_write_entry(apic, pin, entry);
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}
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}
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@ -947,8 +934,8 @@ static bool mp_check_pin_attr(int irq, struct irq_alloc_info *info)
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if (irq < nr_legacy_irqs() && data->count == 1) {
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if (info->ioapic.is_level != data->is_level)
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mp_register_handler(irq, info->ioapic.is_level);
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data->entry.trigger = data->is_level = info->ioapic.is_level;
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data->entry.polarity = data->active_low = info->ioapic.active_low;
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data->entry.is_level = data->is_level = info->ioapic.is_level;
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data->entry.active_low = data->active_low = info->ioapic.active_low;
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}
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return data->is_level == info->ioapic.is_level &&
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@ -1231,10 +1218,9 @@ void ioapic_zap_locks(void)
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static void io_apic_print_entries(unsigned int apic, unsigned int nr_entries)
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{
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int i;
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char buf[256];
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struct IO_APIC_route_entry entry;
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struct IR_IO_APIC_route_entry *ir_entry = (void *)&entry;
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char buf[256];
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int i;
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printk(KERN_DEBUG "IOAPIC %d:\n", apic);
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for (i = 0; i <= nr_entries; i++) {
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@ -1242,20 +1228,20 @@ static void io_apic_print_entries(unsigned int apic, unsigned int nr_entries)
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snprintf(buf, sizeof(buf),
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" pin%02x, %s, %s, %s, V(%02X), IRR(%1d), S(%1d)",
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i,
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entry.mask == IOAPIC_MASKED ? "disabled" : "enabled ",
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entry.trigger == IOAPIC_LEVEL ? "level" : "edge ",
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entry.polarity == IOAPIC_POL_LOW ? "low " : "high",
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entry.masked ? "disabled" : "enabled ",
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entry.is_level ? "level" : "edge ",
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entry.active_low ? "low " : "high",
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entry.vector, entry.irr, entry.delivery_status);
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if (ir_entry->format)
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if (entry.ir_format) {
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printk(KERN_DEBUG "%s, remapped, I(%04X), Z(%X)\n",
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buf, (ir_entry->index2 << 15) | ir_entry->index,
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ir_entry->zero);
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else
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printk(KERN_DEBUG "%s, %s, D(%02X), M(%1d)\n",
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buf,
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entry.dest_mode == IOAPIC_DEST_MODE_LOGICAL ?
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"logical " : "physical",
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entry.dest, entry.delivery_mode);
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(entry.ir_index_15 << 15) | entry.ir_index_0_14,
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entry.ir_zero);
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} else {
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printk(KERN_DEBUG "%s, %s, D(%02X), M(%1d)\n", buf,
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entry.dest_mode_logical ? "logical " : "physical",
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entry.destid_0_7, entry.delivery_mode);
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}
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}
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}
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@ -1380,8 +1366,8 @@ void __init enable_IO_APIC(void)
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/* If the interrupt line is enabled and in ExtInt mode
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* I have found the pin where the i8259 is connected.
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*/
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if ((entry.mask == 0) &&
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(entry.delivery_mode == APIC_DELIVERY_MODE_EXTINT)) {
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if (!entry.masked &&
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entry.delivery_mode == APIC_DELIVERY_MODE_EXTINT) {
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ioapic_i8259.apic = apic;
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ioapic_i8259.pin = pin;
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goto found_i8259;
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@ -1425,12 +1411,12 @@ void native_restore_boot_irq_mode(void)
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struct IO_APIC_route_entry entry;
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memset(&entry, 0, sizeof(entry));
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entry.mask = IOAPIC_UNMASKED;
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entry.trigger = IOAPIC_EDGE;
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entry.polarity = IOAPIC_POL_HIGH;
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entry.dest_mode = IOAPIC_DEST_MODE_PHYSICAL;
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entry.masked = false;
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entry.is_level = false;
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entry.active_low = false;
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entry.dest_mode_logical = false;
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entry.delivery_mode = APIC_DELIVERY_MODE_EXTINT;
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entry.dest = read_apic_id();
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entry.destid_0_7 = read_apic_id();
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/*
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* Add it to the IO-APIC irq-routing table:
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@ -1709,13 +1695,13 @@ static bool io_apic_level_ack_pending(struct mp_chip_data *data)
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raw_spin_lock_irqsave(&ioapic_lock, flags);
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for_each_irq_pin(entry, data->irq_2_pin) {
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unsigned int reg;
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struct IO_APIC_route_entry e;
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int pin;
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pin = entry->pin;
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reg = io_apic_read(entry->apic, 0x10 + pin*2);
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e.w1 = io_apic_read(entry->apic, 0x10 + pin*2);
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/* Is the remote IRR bit set? */
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if (reg & IO_APIC_REDIR_REMOTE_IRR) {
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if (e.irr) {
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raw_spin_unlock_irqrestore(&ioapic_lock, flags);
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return true;
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}
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@ -1874,7 +1860,7 @@ static void ioapic_configure_entry(struct irq_data *irqd)
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* ioapic chip to verify that.
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*/
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if (irqd->chip == &ioapic_chip) {
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mpd->entry.dest = cfg->dest_apicid;
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mpd->entry.destid_0_7 = cfg->dest_apicid;
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mpd->entry.vector = cfg->vector;
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}
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for_each_irq_pin(entry, mpd->irq_2_pin)
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@ -1932,7 +1918,7 @@ static int ioapic_irq_get_chip_state(struct irq_data *irqd,
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* irrelevant because the IO-APIC treats them as fire and
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* forget.
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*/
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if (rentry.irr && rentry.trigger) {
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if (rentry.irr && rentry.is_level) {
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*state = true;
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break;
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}
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@ -2057,12 +2043,12 @@ static inline void __init unlock_ExtINT_logic(void)
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memset(&entry1, 0, sizeof(entry1));
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entry1.dest_mode = IOAPIC_DEST_MODE_PHYSICAL;
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entry1.mask = IOAPIC_UNMASKED;
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entry1.dest = hard_smp_processor_id();
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entry1.delivery_mode = APIC_DELIVERY_MODE_EXTINT;
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entry1.polarity = entry0.polarity;
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entry1.trigger = IOAPIC_EDGE;
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entry1.dest_mode_logical = true;
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entry1.masked = false;
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entry1.destid_0_7 = hard_smp_processor_id();
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entry1.delivery_mode = APIC_DELIVERY_MODE_EXTINT;
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entry1.active_low = entry0.active_low;
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entry1.is_level = false;
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entry1.vector = 0;
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ioapic_write_entry(apic, pin, entry1);
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@ -2937,17 +2923,17 @@ static void mp_setup_entry(struct irq_cfg *cfg, struct mp_chip_data *data,
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struct IO_APIC_route_entry *entry)
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{
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memset(entry, 0, sizeof(*entry));
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entry->delivery_mode = apic->delivery_mode;
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entry->dest_mode = apic->dest_mode_logical;
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entry->dest = cfg->dest_apicid;
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entry->vector = cfg->vector;
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entry->trigger = data->is_level;
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entry->polarity = data->active_low;
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entry->delivery_mode = apic->delivery_mode;
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entry->dest_mode_logical = apic->dest_mode_logical;
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||||
entry->destid_0_7 = cfg->dest_apicid;
|
||||
entry->vector = cfg->vector;
|
||||
entry->is_level = data->is_level;
|
||||
entry->active_low = data->active_low;
|
||||
/*
|
||||
* Mask level triggered irqs. Edge triggered irqs are masked
|
||||
* by the irq core code in case they fire.
|
||||
*/
|
||||
entry->mask = data->is_level;
|
||||
entry->masked = data->is_level;
|
||||
}
|
||||
|
||||
int mp_irqdomain_alloc(struct irq_domain *domain, unsigned int virq,
|
||||
|
||||
@ -3687,11 +3687,11 @@ static void irq_remapping_prepare_irte(struct amd_ir_data *data,
|
||||
entry = info->ioapic.entry;
|
||||
info->ioapic.entry = NULL;
|
||||
memset(entry, 0, sizeof(*entry));
|
||||
entry->vector = index;
|
||||
entry->trigger = info->ioapic.is_level;
|
||||
entry->polarity = info->ioapic.active_low;
|
||||
entry->vector = index;
|
||||
entry->is_level = info->ioapic.is_level;
|
||||
entry->active_low = info->ioapic.active_low;
|
||||
/* Mask level triggered irqs. */
|
||||
entry->mask = info->ioapic.is_level;
|
||||
entry->masked = info->ioapic.is_level;
|
||||
break;
|
||||
|
||||
case X86_IRQ_ALLOC_TYPE_HPET:
|
||||
|
||||
@ -52,7 +52,7 @@ static int hyperv_ir_set_affinity(struct irq_data *data,
|
||||
return ret;
|
||||
|
||||
entry = data->chip_data;
|
||||
entry->dest = cfg->dest_apicid;
|
||||
entry->destid_0_7 = cfg->dest_apicid;
|
||||
entry->vector = cfg->vector;
|
||||
send_cleanup_vector(cfg);
|
||||
|
||||
@ -125,7 +125,7 @@ static int hyperv_irq_remapping_activate(struct irq_domain *domain,
|
||||
struct irq_cfg *cfg = irqd_cfg(irq_data);
|
||||
struct IO_APIC_route_entry *entry = irq_data->chip_data;
|
||||
|
||||
entry->dest = cfg->dest_apicid;
|
||||
entry->destid_0_7 = cfg->dest_apicid;
|
||||
entry->vector = cfg->vector;
|
||||
|
||||
return 0;
|
||||
|
||||
@ -1279,8 +1279,8 @@ static void intel_irq_remapping_prepare_irte(struct intel_ir_data *data,
|
||||
struct irq_alloc_info *info,
|
||||
int index, int sub_handle)
|
||||
{
|
||||
struct IR_IO_APIC_route_entry *entry;
|
||||
struct irte *irte = &data->irte_entry;
|
||||
struct IO_APIC_route_entry *entry;
|
||||
|
||||
prepare_irte(irte, irq_cfg->vector, irq_cfg->dest_apicid);
|
||||
switch (info->type) {
|
||||
@ -1294,22 +1294,21 @@ static void intel_irq_remapping_prepare_irte(struct intel_ir_data *data,
|
||||
irte->avail, irte->vector, irte->dest_id,
|
||||
irte->sid, irte->sq, irte->svt);
|
||||
|
||||
entry = (struct IR_IO_APIC_route_entry *)info->ioapic.entry;
|
||||
entry = info->ioapic.entry;
|
||||
info->ioapic.entry = NULL;
|
||||
memset(entry, 0, sizeof(*entry));
|
||||
entry->index2 = (index >> 15) & 0x1;
|
||||
entry->zero = 0;
|
||||
entry->format = 1;
|
||||
entry->index = (index & 0x7fff);
|
||||
entry->ir_index_15 = !!(index & 0x8000);
|
||||
entry->ir_format = true;
|
||||
entry->ir_index_0_14 = index & 0x7fff;
|
||||
/*
|
||||
* IO-APIC RTE will be configured with virtual vector.
|
||||
* irq handler will do the explicit EOI to the io-apic.
|
||||
*/
|
||||
entry->vector = info->ioapic.pin;
|
||||
entry->trigger = info->ioapic.is_level;
|
||||
entry->polarity = info->ioapic.active_low;
|
||||
entry->vector = info->ioapic.pin;
|
||||
entry->is_level = info->ioapic.is_level;
|
||||
entry->active_low = info->ioapic.active_low;
|
||||
/* Mask level triggered irqs. */
|
||||
entry->mask = info->ioapic.is_level;
|
||||
entry->masked = info->ioapic.is_level;
|
||||
break;
|
||||
|
||||
case X86_IRQ_ALLOC_TYPE_HPET:
|
||||
|
||||
Loading…
Reference in New Issue
Block a user