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dt-bindings: pinctrl: Add dt-bindings for Sunplus SP7021
Add dt-bindings header files and documentation for Sunplus SP7021 SoC. Signed-off-by: Wells Lu <wellslutw@gmail.com> Link: https://lore.kernel.org/r/1642344734-27229-2-git-send-email-wellslutw@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Wells Lu
Linus Walleij
parent
775214d389
commit
340407d214
@ -0,0 +1,374 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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# Copyright (C) Sunplus Co., Ltd.
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/sunplus,sp7021-pinctrl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Sunplus SP7021 Pin Controller Device Tree Bindings
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maintainers:
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- Dvorkin Dmitry <dvorkin@tibbo.com>
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- Wells Lu <wellslutw@gmail.com>
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description: |
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The Sunplus SP7021 pin controller is used to control SoC pins. Please
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refer to pinctrl-bindings.txt in this directory for details of the common
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pinctrl bindings used by client devices.
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SP7021 has 99 digital GPIO pins which are numbered from GPIO 0 to 98. All
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are multiplexed with some special function pins. SP7021 has 3 types of
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special function pins:
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(1) function-group pins:
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Ex 1 (SPI-NOR flash):
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If control-field SPI_FLASH_SEL is set to 1, GPIO 83, 84, 86 and 87
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will be pins of SPI-NOR flash. If it is set to 2, GPIO 76, 78, 79
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and 81 will be pins of SPI-NOR flash.
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Ex 2 (UART_0):
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If control-bit UA0_SEL is set to 1, GPIO 88 and 89 will be TX and
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RX pins of UART_0 (UART channel 0).
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Ex 3 (eMMC):
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If control-bit EMMC_SEL is set to 1, GPIO 72, 73, 74, 75, 76, 77,
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78, 79, 80, 81 will be pins of an eMMC device.
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Properties "function" and "groups" are used to select function-group
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pins.
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(2) fully pin-mux (like phone exchange mux) pins:
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GPIO 8 to 71 are 'fully pin-mux' pins. Any pins of peripherals of
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SP7021 (ex: UART_1, UART_2, UART_3, UART_4, I2C_0, I2C_1, and etc.)
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can be routed to any pins of fully pin-mux pins.
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Ex 1 (UART channel 1):
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If control-field UA1_TX_SEL is set to 3, TX pin of UART_1 will be
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routed to GPIO 10 (3 - 1 + 8 = 10).
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If control-field UA1_RX_SEL is set to 4, RX pin of UART_1 will be
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routed to GPIO 11 (4 - 1 + 8 = 11).
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If control-field UA1_RTS_SEL is set to 5, RTS pin of UART_1 will
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be routed to GPIO 12 (5 - 1 + 8 = 12).
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If control-field UA1_CTS_SEL is set to 6, CTS pin of UART_1 will
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be routed to GPIO 13 (6 - 1 + 8 = 13).
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Ex 2 (I2C channel 0):
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If control-field I2C0_CLK_SEL is set to 20, CLK pin of I2C_0 will
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be routed to GPIO 27 (20 - 1 + 8 = 27).
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If control-field I2C0_DATA_SEL is set to 21, DATA pin of I2C_0
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will be routed to GPIO 28 (21 - 1 + 9 = 28).
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Totally, SP7021 has 120 peripheral pins. The peripheral pins can be
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routed to any of 64 'fully pin-mux' pins.
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(3) I/O processor pins
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SP7021 has a built-in I/O processor.
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Any GPIO pins (GPIO 0 to 98) can be set to pins of I/O processor.
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Vendor property "sunplus,pins" is used to select "fully pin-mux" pins,
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"I/O processor pins" and "digital GPIO" pins.
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The device node of pin controller of Sunplus SP7021 has following
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properties.
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properties:
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compatible:
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const: sunplus,sp7021-pctl
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gpio-controller: true
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'#gpio-cells':
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const: 2
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reg:
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items:
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- description: the MOON2 registers
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- description: the GPIOXT registers
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- description: the FIRST registers
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- description: the MOON1 registers
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reg-names:
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items:
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- const: moon2
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- const: gpioxt
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- const: first
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- const: moon1
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clocks:
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maxItems: 1
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resets:
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maxItems: 1
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patternProperties:
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'-pins$':
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type: object
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description: |
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A pinctrl node should contain at least one subnodes representing the
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pins or function-pins group available on the machine. Each subnode
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will list the pins it needs, and how they should be configured.
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Pinctrl node's client devices use subnodes for desired pin
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configuration. Client device subnodes use below standard properties.
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$ref: pinmux-node.yaml#
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properties:
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sunplus,pins:
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description: |
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Define 'sunplus,pins' which are used by pinctrl node's client
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device.
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It consists of one or more integers which represents the config
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setting for corresponding pin. Each integer defines a individual
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pin in which:
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Bit 32~24: defines GPIO number. Its range is 0 ~ 98.
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Bit 23~16: defines types: (1) fully pin-mux pins
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(2) IO processor pins
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(3) digital GPIO pins
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Bit 15~8: defines pins of peripherals (which are defined in
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'include/dt-binging/pinctrl/sppctl.h').
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Bit 7~0: defines types or initial-state of digital GPIO pins.
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Please use macro SPPCTL_IOPAD to define the integers for pins.
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$ref: /schemas/types.yaml#/definitions/uint32-array
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function:
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description: |
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Define pin-function which is used by pinctrl node's client device.
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The name should be one of string in the following enumeration.
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$ref: "/schemas/types.yaml#/definitions/string"
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enum: [ SPI_FLASH, SPI_FLASH_4BIT, SPI_NAND, CARD0_EMMC, SD_CARD,
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UA0, FPGA_IFX, HDMI_TX, LCDIF, USB0_OTG, USB1_OTG ]
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groups:
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description: |
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Define pin-group in a specified pin-function.
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The name should be one of string in the following enumeration.
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$ref: "/schemas/types.yaml#/definitions/string"
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enum: [ SPI_FLASH1, SPI_FLASH2, SPI_FLASH_4BIT1, SPI_FLASH_4BIT2,
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SPI_NAND, CARD0_EMMC, SD_CARD, UA0, FPGA_IFX, HDMI_TX1,
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HDMI_TX2, HDMI_TX3, LCDIF, USB0_OTG, USB1_OTG ]
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sunplus,zerofunc:
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description: |
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This is a vendor specific property. It is used to disable pins
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which are not used by pinctrl node's client device.
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Some pins may be enabled by boot-loader. We can use this
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property to disable them.
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$ref: /schemas/types.yaml#/definitions/uint32-array
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additionalProperties: false
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allOf:
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- if:
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properties:
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function:
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enum:
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- SPI_FLASH
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then:
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properties:
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groups:
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enum:
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- SPI_FLASH1
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- SPI_FLASH2
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- if:
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properties:
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function:
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enum:
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- SPI_FLASH_4BIT
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then:
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properties:
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groups:
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enum:
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- SPI_FLASH_4BIT1
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- SPI_FLASH_4BIT2
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- if:
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properties:
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function:
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enum:
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- SPI_NAND
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then:
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properties:
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groups:
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enum:
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- SPI_NAND
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- if:
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properties:
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function:
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enum:
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- CARD0_EMMC
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then:
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properties:
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groups:
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enum:
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- CARD0_EMMC
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- if:
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properties:
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function:
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enum:
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- SD_CARD
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then:
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properties:
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groups:
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enum:
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- SD_CARD
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- if:
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properties:
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function:
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enum:
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- UA0
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then:
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properties:
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groups:
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enum:
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- UA0
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- if:
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properties:
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function:
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enum:
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- FPGA_IFX
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then:
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properties:
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groups:
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enum:
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- FPGA_IFX
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- if:
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properties:
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function:
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enum:
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- HDMI_TX
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then:
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properties:
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groups:
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enum:
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- HDMI_TX1
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- HDMI_TX2
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- HDMI_TX3
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- if:
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properties:
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function:
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enum:
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- LCDIF
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then:
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properties:
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groups:
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enum:
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- LCDIF
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- if:
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properties:
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function:
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enum:
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- USB0_OTG
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then:
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properties:
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groups:
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enum:
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- USB0_OTG
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- if:
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properties:
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function:
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enum:
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- USB1_OTG
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then:
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properties:
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groups:
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enum:
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- USB1_OTG
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required:
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- compatible
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- reg
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- reg-names
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- "#gpio-cells"
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- gpio-controller
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- clocks
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- resets
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/pinctrl/sppctl-sp7021.h>
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pinctl@9c000100 {
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compatible = "sunplus,sp7021-pctl";
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reg = <0x9c000100 0x100>, <0x9c000300 0x100>,
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<0x9c0032e4 0x1c>, <0x9c000080 0x20>;
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reg-names = "moon2", "gpioxt", "first", "moon1";
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gpio-controller;
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#gpio-cells = <2>;
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clocks = <&clkc 0x83>;
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resets = <&rstc 0x73>;
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uart0-pins {
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function = "UA0";
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groups = "UA0";
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};
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spinand0-pins {
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function = "SPI_NAND";
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groups = "SPI_NAND";
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};
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uart1-pins {
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sunplus,pins = <
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SPPCTL_IOPAD(11, SPPCTL_PCTL_G_PMUX, MUXF_UA1_TX, 0)
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SPPCTL_IOPAD(10, SPPCTL_PCTL_G_PMUX, MUXF_UA1_RX, 0)
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>;
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};
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uart2-pins {
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sunplus,pins = <
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SPPCTL_IOPAD(20, SPPCTL_PCTL_G_PMUX, MUXF_UA1_TX, 0)
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SPPCTL_IOPAD(21, SPPCTL_PCTL_G_PMUX, MUXF_UA1_RX, 0)
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SPPCTL_IOPAD(22, SPPCTL_PCTL_G_PMUX, MUXF_UA1_RTS, 0)
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SPPCTL_IOPAD(23, SPPCTL_PCTL_G_PMUX, MUXF_UA1_CTS, 0)
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>;
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};
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emmc-pins {
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function = "CARD0_EMMC";
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groups = "CARD0_EMMC";
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};
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sdcard-pins {
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function = "SD_CARD";
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groups = "SD_CARD";
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sunplus,pins = < SPPCTL_IOPAD(91, SPPCTL_PCTL_G_GPIO, 0, 0) >;
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};
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hdmi_A_tx1-pins {
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function = "HDMI_TX";
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groups = "HDMI_TX1";
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};
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hdmi_A_tx2-pins {
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function = "HDMI_TX";
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groups = "HDMI_TX2";
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};
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hdmi_A_tx3-pins {
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function = "HDMI_TX";
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groups = "HDMI_TX3";
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};
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ethernet-pins {
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sunplus,pins = <
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SPPCTL_IOPAD(49,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_CLK_OUT,0)
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SPPCTL_IOPAD(44,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_MAC_SMI_MDC,0)
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SPPCTL_IOPAD(43,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_MAC_SMI_MDIO,0)
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SPPCTL_IOPAD(52,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_TXEN,0)
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SPPCTL_IOPAD(50,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_TXD0,0)
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SPPCTL_IOPAD(51,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_TXD1,0)
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SPPCTL_IOPAD(46,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_CRSDV,0)
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SPPCTL_IOPAD(47,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_RXD0,0)
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SPPCTL_IOPAD(48,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_RXD1,0)
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>;
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sunplus,zerofunc = <
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MUXF_L2SW_LED_FLASH0
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MUXF_L2SW_LED_ON0
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MUXF_L2SW_P0_MAC_RMII_RXER
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>;
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};
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};
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...
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@ -15310,6 +15310,15 @@ M: Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com>
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S: Supported
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F: drivers/pinctrl/pinctrl-thunderbay.c
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PIN CONTROLLER - SUNPLUS / TIBBO
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M: Dvorkin Dmitry <dvorkin@tibbo.com>
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M: Wells Lu <wellslutw@gmail.com>
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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S: Maintained
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W: https://sunplus.atlassian.net/wiki/spaces/doc/overview
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F: Documentation/devicetree/bindings/pinctrl/sunplus,*
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F: include/dt-bindings/pinctrl/sppctl*.h
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PKTCDVD DRIVER
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M: linux-block@vger.kernel.org
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S: Orphan
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179
include/dt-bindings/pinctrl/sppctl-sp7021.h
Normal file
179
include/dt-bindings/pinctrl/sppctl-sp7021.h
Normal file
@ -0,0 +1,179 @@
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
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/*
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* Sunplus SP7021 dt-bindings Pinctrl header file
|
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* Copyright (C) Sunplus Tech/Tibbo Tech.
|
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* Author: Dvorkin Dmitry <dvorkin@tibbo.com>
|
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*/
|
||||
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#ifndef __DT_BINDINGS_PINCTRL_SPPCTL_SP7021_H__
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#define __DT_BINDINGS_PINCTRL_SPPCTL_SP7021_H__
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||||
|
||||
#include <dt-bindings/pinctrl/sppctl.h>
|
||||
|
||||
/*
|
||||
* Please don't change the order of the following defines.
|
||||
* They are based on order of 'hardware' control register
|
||||
* defined in MOON2 ~ MOON3 registers.
|
||||
*/
|
||||
#define MUXF_GPIO 0
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||||
#define MUXF_IOP 1
|
||||
#define MUXF_L2SW_CLK_OUT 2
|
||||
#define MUXF_L2SW_MAC_SMI_MDC 3
|
||||
#define MUXF_L2SW_LED_FLASH0 4
|
||||
#define MUXF_L2SW_LED_FLASH1 5
|
||||
#define MUXF_L2SW_LED_ON0 6
|
||||
#define MUXF_L2SW_LED_ON1 7
|
||||
#define MUXF_L2SW_MAC_SMI_MDIO 8
|
||||
#define MUXF_L2SW_P0_MAC_RMII_TXEN 9
|
||||
#define MUXF_L2SW_P0_MAC_RMII_TXD0 10
|
||||
#define MUXF_L2SW_P0_MAC_RMII_TXD1 11
|
||||
#define MUXF_L2SW_P0_MAC_RMII_CRSDV 12
|
||||
#define MUXF_L2SW_P0_MAC_RMII_RXD0 13
|
||||
#define MUXF_L2SW_P0_MAC_RMII_RXD1 14
|
||||
#define MUXF_L2SW_P0_MAC_RMII_RXER 15
|
||||
#define MUXF_L2SW_P1_MAC_RMII_TXEN 16
|
||||
#define MUXF_L2SW_P1_MAC_RMII_TXD0 17
|
||||
#define MUXF_L2SW_P1_MAC_RMII_TXD1 18
|
||||
#define MUXF_L2SW_P1_MAC_RMII_CRSDV 19
|
||||
#define MUXF_L2SW_P1_MAC_RMII_RXD0 20
|
||||
#define MUXF_L2SW_P1_MAC_RMII_RXD1 21
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||||
#define MUXF_L2SW_P1_MAC_RMII_RXER 22
|
||||
#define MUXF_DAISY_MODE 23
|
||||
#define MUXF_SDIO_CLK 24
|
||||
#define MUXF_SDIO_CMD 25
|
||||
#define MUXF_SDIO_D0 26
|
||||
#define MUXF_SDIO_D1 27
|
||||
#define MUXF_SDIO_D2 28
|
||||
#define MUXF_SDIO_D3 29
|
||||
#define MUXF_PWM0 30
|
||||
#define MUXF_PWM1 31
|
||||
#define MUXF_PWM2 32
|
||||
#define MUXF_PWM3 33
|
||||
#define MUXF_PWM4 34
|
||||
#define MUXF_PWM5 35
|
||||
#define MUXF_PWM6 36
|
||||
#define MUXF_PWM7 37
|
||||
#define MUXF_ICM0_D 38
|
||||
#define MUXF_ICM1_D 39
|
||||
#define MUXF_ICM2_D 40
|
||||
#define MUXF_ICM3_D 41
|
||||
#define MUXF_ICM0_CLK 42
|
||||
#define MUXF_ICM1_CLK 43
|
||||
#define MUXF_ICM2_CLK 44
|
||||
#define MUXF_ICM3_CLK 45
|
||||
#define MUXF_SPIM0_INT 46
|
||||
#define MUXF_SPIM0_CLK 47
|
||||
#define MUXF_SPIM0_EN 48
|
||||
#define MUXF_SPIM0_DO 49
|
||||
#define MUXF_SPIM0_DI 50
|
||||
#define MUXF_SPIM1_INT 51
|
||||
#define MUXF_SPIM1_CLK 52
|
||||
#define MUXF_SPIM1_EN 53
|
||||
#define MUXF_SPIM1_DO 54
|
||||
#define MUXF_SPIM1_DI 55
|
||||
#define MUXF_SPIM2_INT 56
|
||||
#define MUXF_SPIM2_CLK 57
|
||||
#define MUXF_SPIM2_EN 58
|
||||
#define MUXF_SPIM2_DO 59
|
||||
#define MUXF_SPIM2_DI 60
|
||||
#define MUXF_SPIM3_INT 61
|
||||
#define MUXF_SPIM3_CLK 62
|
||||
#define MUXF_SPIM3_EN 63
|
||||
#define MUXF_SPIM3_DO 64
|
||||
#define MUXF_SPIM3_DI 65
|
||||
#define MUXF_SPI0S_INT 66
|
||||
#define MUXF_SPI0S_CLK 67
|
||||
#define MUXF_SPI0S_EN 68
|
||||
#define MUXF_SPI0S_DO 69
|
||||
#define MUXF_SPI0S_DI 70
|
||||
#define MUXF_SPI1S_INT 71
|
||||
#define MUXF_SPI1S_CLK 72
|
||||
#define MUXF_SPI1S_EN 73
|
||||
#define MUXF_SPI1S_DO 74
|
||||
#define MUXF_SPI1S_DI 75
|
||||
#define MUXF_SPI2S_INT 76
|
||||
#define MUXF_SPI2S_CLK 77
|
||||
#define MUXF_SPI2S_EN 78
|
||||
#define MUXF_SPI2S_DO 79
|
||||
#define MUXF_SPI2S_DI 80
|
||||
#define MUXF_SPI3S_INT 81
|
||||
#define MUXF_SPI3S_CLK 82
|
||||
#define MUXF_SPI3S_EN 83
|
||||
#define MUXF_SPI3S_DO 84
|
||||
#define MUXF_SPI3S_DI 85
|
||||
#define MUXF_I2CM0_CLK 86
|
||||
#define MUXF_I2CM0_DAT 87
|
||||
#define MUXF_I2CM1_CLK 88
|
||||
#define MUXF_I2CM1_DAT 89
|
||||
#define MUXF_I2CM2_CLK 90
|
||||
#define MUXF_I2CM2_DAT 91
|
||||
#define MUXF_I2CM3_CLK 92
|
||||
#define MUXF_I2CM3_DAT 93
|
||||
#define MUXF_UA1_TX 94
|
||||
#define MUXF_UA1_RX 95
|
||||
#define MUXF_UA1_CTS 96
|
||||
#define MUXF_UA1_RTS 97
|
||||
#define MUXF_UA2_TX 98
|
||||
#define MUXF_UA2_RX 99
|
||||
#define MUXF_UA2_CTS 100
|
||||
#define MUXF_UA2_RTS 101
|
||||
#define MUXF_UA3_TX 102
|
||||
#define MUXF_UA3_RX 103
|
||||
#define MUXF_UA3_CTS 104
|
||||
#define MUXF_UA3_RTS 105
|
||||
#define MUXF_UA4_TX 106
|
||||
#define MUXF_UA4_RX 107
|
||||
#define MUXF_UA4_CTS 108
|
||||
#define MUXF_UA4_RTS 109
|
||||
#define MUXF_TIMER0_INT 110
|
||||
#define MUXF_TIMER1_INT 111
|
||||
#define MUXF_TIMER2_INT 112
|
||||
#define MUXF_TIMER3_INT 113
|
||||
#define MUXF_GPIO_INT0 114
|
||||
#define MUXF_GPIO_INT1 115
|
||||
#define MUXF_GPIO_INT2 116
|
||||
#define MUXF_GPIO_INT3 117
|
||||
#define MUXF_GPIO_INT4 118
|
||||
#define MUXF_GPIO_INT5 119
|
||||
#define MUXF_GPIO_INT6 120
|
||||
#define MUXF_GPIO_INT7 121
|
||||
|
||||
/*
|
||||
* Please don't change the order of the following defines.
|
||||
* They are based on order of items in array 'sppctl_list_funcs'
|
||||
* in Sunplus pinctrl driver.
|
||||
*/
|
||||
#define GROP_SPI_FLASH 122
|
||||
#define GROP_SPI_FLASH_4BIT 123
|
||||
#define GROP_SPI_NAND 124
|
||||
#define GROP_CARD0_EMMC 125
|
||||
#define GROP_SD_CARD 126
|
||||
#define GROP_UA0 127
|
||||
#define GROP_ACHIP_DEBUG 128
|
||||
#define GROP_ACHIP_UA2AXI 129
|
||||
#define GROP_FPGA_IFX 130
|
||||
#define GROP_HDMI_TX 131
|
||||
#define GROP_AUD_EXT_ADC_IFX0 132
|
||||
#define GROP_AUD_EXT_DAC_IFX0 133
|
||||
#define GROP_SPDIF_RX 134
|
||||
#define GROP_SPDIF_TX 135
|
||||
#define GROP_TDMTX_IFX0 136
|
||||
#define GROP_TDMRX_IFX0 137
|
||||
#define GROP_PDMRX_IFX0 138
|
||||
#define GROP_PCM_IEC_TX 139
|
||||
#define GROP_LCDIF 140
|
||||
#define GROP_DVD_DSP_DEBUG 141
|
||||
#define GROP_I2C_DEBUG 142
|
||||
#define GROP_I2C_SLAVE 143
|
||||
#define GROP_WAKEUP 144
|
||||
#define GROP_UART2AXI 145
|
||||
#define GROP_USB0_I2C 146
|
||||
#define GROP_USB1_I2C 147
|
||||
#define GROP_USB0_OTG 148
|
||||
#define GROP_USB1_OTG 149
|
||||
#define GROP_UPHY0_DEBUG 150
|
||||
#define GROP_UPHY1_DEBUG 151
|
||||
#define GROP_UPHY0_EXT 152
|
||||
#define GROP_PROBE_PORT 153
|
||||
|
||||
#endif
|
||||
31
include/dt-bindings/pinctrl/sppctl.h
Normal file
31
include/dt-bindings/pinctrl/sppctl.h
Normal file
@ -0,0 +1,31 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Sunplus dt-bindings Pinctrl header file
|
||||
* Copyright (C) Sunplus Tech / Tibbo Tech.
|
||||
* Author: Dvorkin Dmitry <dvorkin@tibbo.com>
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_PINCTRL_SPPCTL_H__
|
||||
#define __DT_BINDINGS_PINCTRL_SPPCTL_H__
|
||||
|
||||
#define IOP_G_MASTE (0x01 << 0)
|
||||
#define IOP_G_FIRST (0x01 << 1)
|
||||
|
||||
#define SPPCTL_PCTL_G_PMUX (0x00 | IOP_G_MASTE)
|
||||
#define SPPCTL_PCTL_G_GPIO (IOP_G_FIRST | IOP_G_MASTE)
|
||||
#define SPPCTL_PCTL_G_IOPP (IOP_G_FIRST | 0x00)
|
||||
|
||||
#define SPPCTL_PCTL_L_OUT (0x01 << 0) /* Output LOW */
|
||||
#define SPPCTL_PCTL_L_OU1 (0x01 << 1) /* Output HIGH */
|
||||
#define SPPCTL_PCTL_L_INV (0x01 << 2) /* Input Invert */
|
||||
#define SPPCTL_PCTL_L_ONV (0x01 << 3) /* Output Invert */
|
||||
#define SPPCTL_PCTL_L_ODR (0x01 << 4) /* Output Open Drain */
|
||||
|
||||
/*
|
||||
* pack into 32-bit value:
|
||||
* pin# (8bit), typ (8bit), function (8bit), flag (8bit)
|
||||
*/
|
||||
#define SPPCTL_IOPAD(pin, typ, fun, flg) (((pin) << 24) | ((typ) << 16) | \
|
||||
((fun) << 8) | (flg))
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user