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chelsio: sparse warning fixes (old cxgb2)
Fix problems detected by sparse: 1. whole chunk of MAC code was for defined and never used 2. hook for running ext intr in workqueue wasn't being used Signed-off-by: Stephen Hemminger <shemminger@linux-foundation.org> Signed-off-by: Jeff Garzik <jeff@garzik.org>
This commit is contained in:
Stephen Hemminger
David S. Miller
parent
3bf76b8160
commit
33a85aa1c9
@ -4,6 +4,6 @@
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obj-$(CONFIG_CHELSIO_T1) += cxgb.o
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cxgb-$(CONFIG_CHELSIO_T1_1G) += mac.o mv88e1xxx.o vsc7326.o
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cxgb-$(CONFIG_CHELSIO_T1_1G) += mv88e1xxx.o vsc7326.o
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cxgb-objs := cxgb2.o espi.o tp.o pm3393.o sge.o subr.o \
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mv88x201x.o my3126.o $(cxgb-y)
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@ -372,6 +372,7 @@ extern void t1_interrupts_enable(adapter_t *adapter);
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extern void t1_interrupts_disable(adapter_t *adapter);
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extern void t1_interrupts_clear(adapter_t *adapter);
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extern int t1_elmer0_ext_intr_handler(adapter_t *adapter);
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extern void t1_elmer0_ext_intr(adapter_t *adapter);
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extern int t1_slow_intr_handler(adapter_t *adapter);
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extern int t1_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc);
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@ -1,368 +0,0 @@
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/* $Date: 2005/10/22 00:42:59 $ $RCSfile: mac.c,v $ $Revision: 1.32 $ */
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#include "gmac.h"
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#include "regs.h"
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#include "fpga_defs.h"
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#define MAC_CSR_INTERFACE_GMII 0x0
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#define MAC_CSR_INTERFACE_TBI 0x1
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#define MAC_CSR_INTERFACE_MII 0x2
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#define MAC_CSR_INTERFACE_RMII 0x3
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/* Chelsio's MAC statistics. */
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struct mac_statistics {
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/* Transmit */
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u32 TxFramesTransmittedOK;
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u32 TxReserved1;
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u32 TxReserved2;
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u32 TxOctetsTransmittedOK;
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u32 TxFramesWithDeferredXmissions;
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u32 TxLateCollisions;
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u32 TxFramesAbortedDueToXSCollisions;
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u32 TxFramesLostDueToIntMACXmitError;
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u32 TxReserved3;
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u32 TxMulticastFrameXmittedOK;
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u32 TxBroadcastFramesXmittedOK;
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u32 TxFramesWithExcessiveDeferral;
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u32 TxPAUSEMACCtrlFramesTransmitted;
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/* Receive */
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u32 RxFramesReceivedOK;
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u32 RxFrameCheckSequenceErrors;
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u32 RxAlignmentErrors;
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u32 RxOctetsReceivedOK;
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u32 RxFramesLostDueToIntMACRcvError;
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u32 RxMulticastFramesReceivedOK;
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u32 RxBroadcastFramesReceivedOK;
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u32 RxInRangeLengthErrors;
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u32 RxTxOutOfRangeLengthField;
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u32 RxFrameTooLongErrors;
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u32 RxPAUSEMACCtrlFramesReceived;
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};
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static int static_aPorts[] = {
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FPGA_GMAC_INTERRUPT_PORT0,
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FPGA_GMAC_INTERRUPT_PORT1,
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FPGA_GMAC_INTERRUPT_PORT2,
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FPGA_GMAC_INTERRUPT_PORT3
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};
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struct _cmac_instance {
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u32 index;
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};
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static int mac_intr_enable(struct cmac *mac)
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{
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u32 mac_intr;
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if (t1_is_asic(mac->adapter)) {
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/* ASIC */
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/* We don't use the on chip MAC for ASIC products. */
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} else {
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/* FPGA */
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/* Set parent gmac interrupt. */
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mac_intr = readl(mac->adapter->regs + A_PL_ENABLE);
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mac_intr |= FPGA_PCIX_INTERRUPT_GMAC;
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writel(mac_intr, mac->adapter->regs + A_PL_ENABLE);
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mac_intr = readl(mac->adapter->regs + FPGA_GMAC_ADDR_INTERRUPT_ENABLE);
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mac_intr |= static_aPorts[mac->instance->index];
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writel(mac_intr,
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mac->adapter->regs + FPGA_GMAC_ADDR_INTERRUPT_ENABLE);
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}
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return 0;
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}
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static int mac_intr_disable(struct cmac *mac)
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{
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u32 mac_intr;
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if (t1_is_asic(mac->adapter)) {
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/* ASIC */
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/* We don't use the on chip MAC for ASIC products. */
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} else {
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/* FPGA */
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/* Set parent gmac interrupt. */
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mac_intr = readl(mac->adapter->regs + A_PL_ENABLE);
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mac_intr &= ~FPGA_PCIX_INTERRUPT_GMAC;
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writel(mac_intr, mac->adapter->regs + A_PL_ENABLE);
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mac_intr = readl(mac->adapter->regs + FPGA_GMAC_ADDR_INTERRUPT_ENABLE);
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mac_intr &= ~(static_aPorts[mac->instance->index]);
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writel(mac_intr,
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mac->adapter->regs + FPGA_GMAC_ADDR_INTERRUPT_ENABLE);
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}
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return 0;
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}
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static int mac_intr_clear(struct cmac *mac)
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{
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u32 mac_intr;
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if (t1_is_asic(mac->adapter)) {
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/* ASIC */
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/* We don't use the on chip MAC for ASIC products. */
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} else {
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/* FPGA */
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/* Set parent gmac interrupt. */
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writel(FPGA_PCIX_INTERRUPT_GMAC,
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mac->adapter->regs + A_PL_CAUSE);
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mac_intr = readl(mac->adapter->regs + FPGA_GMAC_ADDR_INTERRUPT_CAUSE);
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mac_intr |= (static_aPorts[mac->instance->index]);
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writel(mac_intr,
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mac->adapter->regs + FPGA_GMAC_ADDR_INTERRUPT_CAUSE);
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}
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return 0;
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}
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static int mac_get_address(struct cmac *mac, u8 addr[6])
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{
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u32 data32_lo, data32_hi;
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data32_lo = readl(mac->adapter->regs
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+ MAC_REG_IDLO(mac->instance->index));
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data32_hi = readl(mac->adapter->regs
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+ MAC_REG_IDHI(mac->instance->index));
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addr[0] = (u8) ((data32_hi >> 8) & 0xFF);
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addr[1] = (u8) ((data32_hi) & 0xFF);
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addr[2] = (u8) ((data32_lo >> 24) & 0xFF);
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addr[3] = (u8) ((data32_lo >> 16) & 0xFF);
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addr[4] = (u8) ((data32_lo >> 8) & 0xFF);
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addr[5] = (u8) ((data32_lo) & 0xFF);
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return 0;
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}
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static int mac_reset(struct cmac *mac)
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{
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u32 data32;
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int mac_in_reset, time_out = 100;
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int idx = mac->instance->index;
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data32 = readl(mac->adapter->regs + MAC_REG_CSR(idx));
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writel(data32 | F_MAC_RESET,
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mac->adapter->regs + MAC_REG_CSR(idx));
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do {
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data32 = readl(mac->adapter->regs + MAC_REG_CSR(idx));
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mac_in_reset = data32 & F_MAC_RESET;
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if (mac_in_reset)
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udelay(1);
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} while (mac_in_reset && --time_out);
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if (mac_in_reset) {
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CH_ERR("%s: MAC %d reset timed out\n",
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mac->adapter->name, idx);
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return 2;
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}
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return 0;
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}
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static int mac_set_rx_mode(struct cmac *mac, struct t1_rx_mode *rm)
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{
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u32 val;
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val = readl(mac->adapter->regs
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+ MAC_REG_CSR(mac->instance->index));
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val &= ~(F_MAC_PROMISC | F_MAC_MC_ENABLE);
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val |= V_MAC_PROMISC(t1_rx_mode_promisc(rm) != 0);
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val |= V_MAC_MC_ENABLE(t1_rx_mode_allmulti(rm) != 0);
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writel(val,
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mac->adapter->regs + MAC_REG_CSR(mac->instance->index));
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return 0;
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}
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static int mac_set_speed_duplex_fc(struct cmac *mac, int speed, int duplex,
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int fc)
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{
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u32 data32;
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data32 = readl(mac->adapter->regs
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+ MAC_REG_CSR(mac->instance->index));
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data32 &= ~(F_MAC_HALF_DUPLEX | V_MAC_SPEED(M_MAC_SPEED) |
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V_INTERFACE(M_INTERFACE) | F_MAC_TX_PAUSE_ENABLE |
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F_MAC_RX_PAUSE_ENABLE);
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switch (speed) {
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case SPEED_10:
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case SPEED_100:
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data32 |= V_INTERFACE(MAC_CSR_INTERFACE_MII);
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data32 |= V_MAC_SPEED(speed == SPEED_10 ? 0 : 1);
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break;
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case SPEED_1000:
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data32 |= V_INTERFACE(MAC_CSR_INTERFACE_GMII);
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data32 |= V_MAC_SPEED(2);
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break;
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}
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if (duplex >= 0)
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data32 |= V_MAC_HALF_DUPLEX(duplex == DUPLEX_HALF);
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if (fc >= 0) {
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data32 |= V_MAC_RX_PAUSE_ENABLE((fc & PAUSE_RX) != 0);
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data32 |= V_MAC_TX_PAUSE_ENABLE((fc & PAUSE_TX) != 0);
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}
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writel(data32,
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mac->adapter->regs + MAC_REG_CSR(mac->instance->index));
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return 0;
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}
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static int mac_enable(struct cmac *mac, int which)
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{
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u32 val;
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val = readl(mac->adapter->regs
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+ MAC_REG_CSR(mac->instance->index));
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if (which & MAC_DIRECTION_RX)
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val |= F_MAC_RX_ENABLE;
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if (which & MAC_DIRECTION_TX)
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val |= F_MAC_TX_ENABLE;
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writel(val,
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mac->adapter->regs + MAC_REG_CSR(mac->instance->index));
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return 0;
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}
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static int mac_disable(struct cmac *mac, int which)
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{
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u32 val;
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val = readl(mac->adapter->regs
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+ MAC_REG_CSR(mac->instance->index));
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if (which & MAC_DIRECTION_RX)
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val &= ~F_MAC_RX_ENABLE;
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if (which & MAC_DIRECTION_TX)
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val &= ~F_MAC_TX_ENABLE;
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writel(val,
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mac->adapter->regs + MAC_REG_CSR(mac->instance->index));
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return 0;
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}
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#if 0
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static int mac_set_ifs(struct cmac *mac, u32 mode)
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{
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t1_write_reg_4(mac->adapter,
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MAC_REG_IFS(mac->instance->index),
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mode);
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return 0;
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}
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static int mac_enable_isl(struct cmac *mac)
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{
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u32 data32 = readl(mac->adapter->regs
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+ MAC_REG_CSR(mac->instance->index));
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data32 |= F_MAC_RX_ENABLE | F_MAC_TX_ENABLE;
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t1_write_reg_4(mac->adapter,
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MAC_REG_CSR(mac->instance->index),
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data32);
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return 0;
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}
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#endif
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static int mac_set_mtu(struct cmac *mac, int mtu)
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{
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if (mtu > 9600)
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return -EINVAL;
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writel(mtu + ETH_HLEN + VLAN_HLEN,
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mac->adapter->regs + MAC_REG_LARGEFRAMELENGTH(mac->instance->index));
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return 0;
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}
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static const struct cmac_statistics *mac_update_statistics(struct cmac *mac,
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int flag)
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{
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struct mac_statistics st;
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u32 *p = (u32 *) & st, i;
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writel(0,
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mac->adapter->regs + MAC_REG_RMCNT(mac->instance->index));
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for (i = 0; i < sizeof(st) / sizeof(u32); i++)
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*p++ = readl(mac->adapter->regs
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+ MAC_REG_RMDATA(mac->instance->index));
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/* XXX convert stats */
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return &mac->stats;
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}
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static void mac_destroy(struct cmac *mac)
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{
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kfree(mac);
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}
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static struct cmac_ops chelsio_mac_ops = {
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.destroy = mac_destroy,
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.reset = mac_reset,
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.interrupt_enable = mac_intr_enable,
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.interrupt_disable = mac_intr_disable,
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.interrupt_clear = mac_intr_clear,
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.enable = mac_enable,
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.disable = mac_disable,
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.set_mtu = mac_set_mtu,
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.set_rx_mode = mac_set_rx_mode,
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.set_speed_duplex_fc = mac_set_speed_duplex_fc,
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.macaddress_get = mac_get_address,
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.statistics_update = mac_update_statistics,
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};
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static struct cmac *mac_create(adapter_t *adapter, int index)
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{
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struct cmac *mac;
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u32 data32;
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if (index >= 4)
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return NULL;
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mac = kzalloc(sizeof(*mac) + sizeof(cmac_instance), GFP_KERNEL);
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if (!mac)
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return NULL;
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mac->ops = &chelsio_mac_ops;
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mac->instance = (cmac_instance *) (mac + 1);
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mac->instance->index = index;
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mac->adapter = adapter;
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data32 = readl(adapter->regs + MAC_REG_CSR(mac->instance->index));
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data32 &= ~(F_MAC_RESET | F_MAC_PROMISC | F_MAC_PROMISC |
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F_MAC_LB_ENABLE | F_MAC_RX_ENABLE | F_MAC_TX_ENABLE);
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data32 |= F_MAC_JUMBO_ENABLE;
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writel(data32, adapter->regs + MAC_REG_CSR(mac->instance->index));
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/* Initialize the random backoff seed. */
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data32 = 0x55aa + (3 * index);
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writel(data32,
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adapter->regs + MAC_REG_GMRANDBACKOFFSEED(mac->instance->index));
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/* Check to see if the mac address needs to be set manually. */
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data32 = readl(adapter->regs + MAC_REG_IDLO(mac->instance->index));
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if (data32 == 0 || data32 == 0xffffffff) {
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/*
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* Add a default MAC address if we can't read one.
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*/
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writel(0x43FFFFFF - index,
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adapter->regs + MAC_REG_IDLO(mac->instance->index));
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writel(0x0007,
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adapter->regs + MAC_REG_IDHI(mac->instance->index));
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}
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(void) mac_set_mtu(mac, 1500);
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return mac;
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}
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const struct gmac t1_chelsio_mac_ops = {
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.create = mac_create
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};
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@ -884,7 +884,7 @@ static int asic_slow_intr(adapter_t *adapter)
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if (cause & F_PL_INTR_PCIX)
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t1_pci_intr_handler(adapter);
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if (cause & F_PL_INTR_EXT)
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t1_elmer0_ext_intr_handler(adapter);
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t1_elmer0_ext_intr(adapter);
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/* Clear the interrupts just processed. */
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writel(cause, adapter->regs + A_PL_CAUSE);
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