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serial: 8250_pci1xxxx: Add driver for quad-uart support
pci1xxxx is a PCIe switch with a multi-function endpoint on one of its downstream ports. Quad-uart is one of the functions in the multi-function endpoint. This driver loads for the quad-uart and enumerates single or multiple instances of uart based on the PCIe subsystem device ID. Co-developed-by: Tharun Kumar P <tharunkumar.pasumarthi@microchip.com> Signed-off-by: Tharun Kumar P <tharunkumar.pasumarthi@microchip.com> Signed-off-by: Kumaravel Thiagarajan <kumaravel.thiagarajan@microchip.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20230207164814.3104605-3-kumaravel.thiagarajan@microchip.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Kumaravel Thiagarajan
Greg Kroah-Hartman
parent
0348386dab
commit
32bb477fa7
@ -13799,6 +13799,13 @@ L: linux-i2c@vger.kernel.org
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S: Maintained
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F: drivers/i2c/busses/i2c-mchp-pci1xxxx.c
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MICROCHIP PCIe UART DRIVER
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M: Kumaravel Thiagarajan <kumaravel.thiagarajan@microchip.com>
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M: Tharun Kumar P <tharunkumar.pasumarthi@microchip.com>
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L: linux-serial@vger.kernel.org
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S: Maintained
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F: drivers/tty/serial/8250/8250_pci1xxxx.c
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MICROCHIP PWM DRIVER
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M: Claudiu Beznea <claudiu.beznea@microchip.com>
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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329
drivers/tty/serial/8250/8250_pci1xxxx.c
Normal file
329
drivers/tty/serial/8250/8250_pci1xxxx.c
Normal file
@ -0,0 +1,329 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Probe module for 8250/16550-type MCHP PCI serial ports.
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*
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* Based on drivers/tty/serial/8250/8250_pci.c,
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*
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* Copyright (C) 2022 Microchip Technology Inc., All Rights Reserved.
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*/
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#include <linux/bitfield.h>
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#include <linux/bitops.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/serial_core.h>
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#include <linux/slab.h>
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#include <linux/string.h>
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#include <linux/units.h>
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#include <linux/tty.h>
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#include <asm/byteorder.h>
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#include "8250.h"
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#include "8250_pcilib.h"
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#define PCI_DEVICE_ID_EFAR_PCI12000 0xa002
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#define PCI_DEVICE_ID_EFAR_PCI11010 0xa012
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#define PCI_DEVICE_ID_EFAR_PCI11101 0xa022
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#define PCI_DEVICE_ID_EFAR_PCI11400 0xa032
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#define PCI_DEVICE_ID_EFAR_PCI11414 0xa042
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#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_4p 0x0001
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#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p012 0x0002
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#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p013 0x0003
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#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p023 0x0004
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#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p123 0x0005
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#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p01 0x0006
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#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p02 0x0007
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#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p03 0x0008
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#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p12 0x0009
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#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p13 0x000a
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#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p23 0x000b
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#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p0 0x000c
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#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p1 0x000d
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#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p2 0x000e
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#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p3 0x000f
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#define PCI_SUBDEVICE_ID_EFAR_PCI12000 PCI_DEVICE_ID_EFAR_PCI12000
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#define PCI_SUBDEVICE_ID_EFAR_PCI11010 PCI_DEVICE_ID_EFAR_PCI11010
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#define PCI_SUBDEVICE_ID_EFAR_PCI11101 PCI_DEVICE_ID_EFAR_PCI11101
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#define PCI_SUBDEVICE_ID_EFAR_PCI11400 PCI_DEVICE_ID_EFAR_PCI11400
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#define PCI_SUBDEVICE_ID_EFAR_PCI11414 PCI_DEVICE_ID_EFAR_PCI11414
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#define UART_ACTV_REG 0x11
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#define UART_BLOCK_SET_ACTIVE BIT(0)
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#define UART_PCI_CTRL_REG 0x80
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#define UART_PCI_CTRL_SET_MULTIPLE_MSI BIT(4)
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#define UART_PCI_CTRL_D3_CLK_ENABLE BIT(0)
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#define ADCL_CFG_REG 0x40
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#define ADCL_CFG_POL_SEL BIT(2)
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#define ADCL_CFG_PIN_SEL BIT(1)
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#define ADCL_CFG_EN BIT(0)
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#define UART_BIT_SAMPLE_CNT 16
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#define BAUD_CLOCK_DIV_INT_MSK GENMASK(31, 8)
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#define ADCL_CFG_RTS_DELAY_MASK GENMASK(11, 8)
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#define UART_CLOCK_DEFAULT (62500 * HZ_PER_KHZ)
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#define UART_WAKE_REG 0x8C
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#define UART_WAKE_MASK_REG 0x90
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#define UART_WAKE_N_PIN BIT(2)
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#define UART_WAKE_NCTS BIT(1)
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#define UART_WAKE_INT BIT(0)
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#define UART_WAKE_SRCS \
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(UART_WAKE_N_PIN | UART_WAKE_NCTS | UART_WAKE_INT)
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#define UART_BAUD_CLK_DIVISOR_REG 0x54
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#define UART_RESET_REG 0x94
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#define UART_RESET_D3_RESET_DISABLE BIT(16)
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#define MAX_PORTS 4
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#define PORT_OFFSET 0x100
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static const int logical_to_physical_port_idx[][MAX_PORTS] = {
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{0, 1, 2, 3}, /* PCI12000, PCI11010, PCI11101, PCI11400, PCI11414 */
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{0, 1, 2, 3}, /* PCI4p */
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{0, 1, 2, -1}, /* PCI3p012 */
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{0, 1, 3, -1}, /* PCI3p013 */
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{0, 2, 3, -1}, /* PCI3p023 */
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{1, 2, 3, -1}, /* PCI3p123 */
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{0, 1, -1, -1}, /* PCI2p01 */
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{0, 2, -1, -1}, /* PCI2p02 */
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{0, 3, -1, -1}, /* PCI2p03 */
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{1, 2, -1, -1}, /* PCI2p12 */
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{1, 3, -1, -1}, /* PCI2p13 */
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{2, 3, -1, -1}, /* PCI2p23 */
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{0, -1, -1, -1}, /* PCI1p0 */
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{1, -1, -1, -1}, /* PCI1p1 */
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{2, -1, -1, -1}, /* PCI1p2 */
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{3, -1, -1, -1}, /* PCI1p3 */
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};
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struct pci1xxxx_8250 {
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unsigned int nr;
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void __iomem *membase;
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int line[];
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};
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static int pci1xxxx_get_num_ports(struct pci_dev *dev)
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{
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switch (dev->subsystem_device) {
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case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p0:
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case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p1:
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case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p2:
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case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p3:
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case PCI_SUBDEVICE_ID_EFAR_PCI12000:
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case PCI_SUBDEVICE_ID_EFAR_PCI11010:
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case PCI_SUBDEVICE_ID_EFAR_PCI11101:
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case PCI_SUBDEVICE_ID_EFAR_PCI11400:
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default:
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return 1;
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case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p01:
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case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p02:
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case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p03:
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case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p12:
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case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p13:
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case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p23:
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return 2;
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case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p012:
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case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p123:
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case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p013:
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case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p023:
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return 3;
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case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_4p:
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case PCI_SUBDEVICE_ID_EFAR_PCI11414:
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return 4;
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}
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}
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static unsigned int pci1xxxx_get_divisor(struct uart_port *port,
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unsigned int baud, unsigned int *frac)
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{
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unsigned int quot;
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/*
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* Calculate baud rate sampling period in nanoseconds.
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* Fractional part x denotes x/255 parts of a nanosecond.
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*/
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quot = NSEC_PER_SEC / (baud * UART_BIT_SAMPLE_CNT);
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*frac = (NSEC_PER_SEC - quot * baud * UART_BIT_SAMPLE_CNT) *
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255 / UART_BIT_SAMPLE_CNT / baud;
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return quot;
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}
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static void pci1xxxx_set_divisor(struct uart_port *port, unsigned int baud,
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unsigned int quot, unsigned int frac)
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{
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writel(FIELD_PREP(BAUD_CLOCK_DIV_INT_MSK, quot) | frac,
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port->membase + UART_BAUD_CLK_DIVISOR_REG);
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}
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static int pci1xxxx_setup(struct pci_dev *pdev,
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struct uart_8250_port *port, int port_idx)
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{
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int ret;
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port->port.flags |= UPF_FIXED_TYPE | UPF_SKIP_TEST;
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port->port.type = PORT_MCHP16550A;
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port->port.set_termios = serial8250_do_set_termios;
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port->port.get_divisor = pci1xxxx_get_divisor;
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port->port.set_divisor = pci1xxxx_set_divisor;
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ret = serial8250_pci_setup_port(pdev, port, 0, PORT_OFFSET * port_idx, 0);
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if (ret < 0)
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return ret;
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writeb(UART_BLOCK_SET_ACTIVE, port->port.membase + UART_ACTV_REG);
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writeb(UART_WAKE_SRCS, port->port.membase + UART_WAKE_REG);
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writeb(UART_WAKE_N_PIN, port->port.membase + UART_WAKE_MASK_REG);
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return 0;
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}
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static unsigned int pci1xxxx_get_max_port(int subsys_dev)
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{
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unsigned int i = MAX_PORTS;
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if (subsys_dev < ARRAY_SIZE(logical_to_physical_port_idx))
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while (i--) {
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if (logical_to_physical_port_idx[subsys_dev][i] != -1)
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return logical_to_physical_port_idx[subsys_dev][i] + 1;
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}
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if (subsys_dev == PCI_SUBDEVICE_ID_EFAR_PCI11414)
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return 4;
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return 1;
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}
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static int pci1xxxx_logical_to_physical_port_translate(int subsys_dev, int port)
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{
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if (subsys_dev < ARRAY_SIZE(logical_to_physical_port_idx))
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return logical_to_physical_port_idx[subsys_dev][port];
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return logical_to_physical_port_idx[0][port];
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}
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static int pci1xxxx_serial_probe(struct pci_dev *pdev,
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const struct pci_device_id *id)
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{
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struct device *dev = &pdev->dev;
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struct pci1xxxx_8250 *priv;
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struct uart_8250_port uart;
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unsigned int max_vec_reqd;
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unsigned int nr_ports, i;
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int num_vectors;
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int subsys_dev;
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int port_idx;
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int rc;
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rc = pcim_enable_device(pdev);
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if (rc)
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return rc;
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nr_ports = pci1xxxx_get_num_ports(pdev);
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priv = devm_kzalloc(dev, struct_size(priv, line, nr_ports), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->membase = pci_ioremap_bar(pdev, 0);
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if (!priv->membase)
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return -ENOMEM;
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pci_set_master(pdev);
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priv->nr = nr_ports;
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subsys_dev = pdev->subsystem_device;
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max_vec_reqd = pci1xxxx_get_max_port(subsys_dev);
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num_vectors = pci_alloc_irq_vectors(pdev, 1, max_vec_reqd, PCI_IRQ_ALL_TYPES);
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if (num_vectors < 0) {
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pci_iounmap(pdev, priv->membase);
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return num_vectors;
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}
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memset(&uart, 0, sizeof(uart));
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uart.port.flags = UPF_SHARE_IRQ | UPF_FIXED_PORT;
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uart.port.uartclk = UART_CLOCK_DEFAULT;
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uart.port.dev = dev;
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if (num_vectors == max_vec_reqd)
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writeb(UART_PCI_CTRL_SET_MULTIPLE_MSI, priv->membase + UART_PCI_CTRL_REG);
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for (i = 0; i < nr_ports; i++) {
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priv->line[i] = -ENODEV;
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port_idx = pci1xxxx_logical_to_physical_port_translate(subsys_dev, i);
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if (num_vectors == max_vec_reqd)
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uart.port.irq = pci_irq_vector(pdev, port_idx);
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else
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uart.port.irq = pci_irq_vector(pdev, 0);
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rc = pci1xxxx_setup(pdev, &uart, port_idx);
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if (rc) {
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dev_warn(dev, "Failed to setup port %u\n", i);
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continue;
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}
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priv->line[i] = serial8250_register_8250_port(&uart);
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if (priv->line[i] < 0) {
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dev_warn(dev,
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"Couldn't register serial port %lx, irq %d, type %d, error %d\n",
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uart.port.iobase, uart.port.irq, uart.port.iotype,
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priv->line[i]);
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}
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}
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pci_set_drvdata(pdev, priv);
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return 0;
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}
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static void pci1xxxx_serial_remove(struct pci_dev *dev)
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{
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struct pci1xxxx_8250 *priv = pci_get_drvdata(dev);
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unsigned int i;
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for (i = 0; i < priv->nr; i++) {
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if (priv->line[i] >= 0)
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serial8250_unregister_port(priv->line[i]);
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}
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pci_free_irq_vectors(dev);
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pci_iounmap(dev, priv->membase);
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}
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static const struct pci_device_id pci1xxxx_pci_tbl[] = {
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{ PCI_VDEVICE(EFAR, PCI_DEVICE_ID_EFAR_PCI11010) },
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{ PCI_VDEVICE(EFAR, PCI_DEVICE_ID_EFAR_PCI11101) },
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{ PCI_VDEVICE(EFAR, PCI_DEVICE_ID_EFAR_PCI11400) },
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{ PCI_VDEVICE(EFAR, PCI_DEVICE_ID_EFAR_PCI11414) },
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{ PCI_VDEVICE(EFAR, PCI_DEVICE_ID_EFAR_PCI12000) },
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{}
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};
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MODULE_DEVICE_TABLE(pci, pci1xxxx_pci_tbl);
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static struct pci_driver pci1xxxx_pci_driver = {
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.name = "pci1xxxx serial",
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.probe = pci1xxxx_serial_probe,
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.remove = pci1xxxx_serial_remove,
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.id_table = pci1xxxx_pci_tbl,
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};
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module_pci_driver(pci1xxxx_pci_driver);
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static_assert((ARRAY_SIZE(logical_to_physical_port_idx) == PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p3 + 1));
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MODULE_IMPORT_NS(SERIAL_8250_PCI);
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MODULE_DESCRIPTION("Microchip Technology Inc. PCIe to UART module");
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MODULE_AUTHOR("Kumaravel Thiagarajan <kumaravel.thiagarajan@microchip.com>");
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MODULE_AUTHOR("Tharun Kumar P <tharunkumar.pasumarthi@microchip.com>");
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MODULE_LICENSE("GPL");
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@ -313,6 +313,14 @@ static const struct serial8250_config uart_config[] = {
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.rxtrig_bytes = {1, 4, 8, 14},
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.flags = UART_CAP_FIFO,
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},
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[PORT_MCHP16550A] = {
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.name = "MCHP16550A",
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.fifo_size = 256,
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.tx_loadsz = 256,
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.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01,
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.rxtrig_bytes = {2, 66, 130, 194},
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.flags = UART_CAP_FIFO,
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},
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};
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/* Uart divisor latch read */
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@ -295,6 +295,17 @@ config SERIAL_8250_HUB6
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To compile this driver as a module, choose M here: the module
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will be called 8250_hub6.
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config SERIAL_8250_PCI1XXXX
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tristate "Microchip 8250 based serial port"
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depends on SERIAL_8250 && PCI
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select SERIAL_8250_PCILIB
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default SERIAL_8250
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help
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Select this option if you have a setup with Microchip PCIe
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Switch with serial port enabled and wish to enable 8250
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serial driver for the serial interface. This driver support
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will ensure to support baud rates upto 1.5Mpbs.
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#
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# Misc. options/drivers.
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#
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@ -27,6 +27,7 @@ obj-$(CONFIG_SERIAL_8250_ACCENT) += 8250_accent.o
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obj-$(CONFIG_SERIAL_8250_BOCA) += 8250_boca.o
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obj-$(CONFIG_SERIAL_8250_EXAR_ST16C554) += 8250_exar_st16c554.o
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obj-$(CONFIG_SERIAL_8250_HUB6) += 8250_hub6.o
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obj-$(CONFIG_SERIAL_8250_PCI1XXXX) += 8250_pci1xxxx.o
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obj-$(CONFIG_SERIAL_8250_FSL) += 8250_fsl.o
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obj-$(CONFIG_SERIAL_8250_MEN_MCB) += 8250_men_mcb.o
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obj-$(CONFIG_SERIAL_8250_DFL) += 8250_dfl.o
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|
||||
@ -207,6 +207,9 @@
|
||||
/* Atheros AR933X SoC */
|
||||
#define PORT_AR933X 99
|
||||
|
||||
/* MCHP 16550A UART with 256 byte FIFOs */
|
||||
#define PORT_MCHP16550A 100
|
||||
|
||||
/* ARC (Synopsys) on-chip UART */
|
||||
#define PORT_ARC 101
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user