- Based against v3.7-rc1
  - Latest changes to arch/arm/mm/cache-tauros2.c
     c2b7e05 ARM: cache: add dt support for tauros2 cache
 
 Misc. fixes for latest changes to mach-dove/
 Fixes build breakage for mach-dove
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Merge tag 'mvebu_dove_late_fixes_for_v3.7' of git://git.infradead.org/users/jcooper/linux into fixes

From Jason Cooper:

Misc. fixes for latest changes to mach-dove/
Fixes build breakage for mach-dove

* tag 'mvebu_dove_late_fixes_for_v3.7' of git://git.infradead.org/users/jcooper/linux:
  ARM: dove: Add crypto engine to DT
  ARM: dove: Remove watchdog from DT
  ARM: dove: Restructure SoC device tree descriptor
  ARM: dove: Fix clock names of sata and gbe
  ARM: dove: Fix tauros2 device tree init
  ARM: dove: Add pcie clock support
This commit is contained in:
Olof Johansson 2012-10-17 17:09:37 -07:00
commit 327f81c455
3 changed files with 41 additions and 21 deletions

View File

@ -4,21 +4,32 @@
compatible = "marvell,dove";
model = "Marvell Armada 88AP510 SoC";
interrupt-parent = <&intc>;
intc: interrupt-controller {
compatible = "marvell,orion-intc";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0xf1020204 0x04>,
<0xf1020214 0x04>;
};
mbus@f1000000 {
soc@f1000000 {
compatible = "simple-bus";
ranges = <0 0xf1000000 0x4000000>;
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&intc>;
ranges = <0xc8000000 0xc8000000 0x0100000 /* CESA SRAM 1M */
0xe0000000 0xe0000000 0x8000000 /* PCIe0 Mem 128M */
0xe8000000 0xe8000000 0x8000000 /* PCIe1 Mem 128M */
0xf0000000 0xf0000000 0x0100000 /* ScratchPad 1M */
0x00000000 0xf1000000 0x1000000 /* SB/NB regs 16M */
0xf2000000 0xf2000000 0x0100000 /* PCIe0 I/O 1M */
0xf2100000 0xf2100000 0x0100000 /* PCIe0 I/O 1M */
0xf8000000 0xf8000000 0x8000000>; /* BootROM 128M */
l2: l2-cache {
compatible = "marvell,tauros2-cache";
marvell,tauros2-cache-features = <0>;
};
intc: interrupt-controller {
compatible = "marvell,orion-intc";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x20204 0x04>, <0x20214 0x04>;
};
uart0: serial@12000 {
compatible = "ns16550a";
@ -56,11 +67,6 @@
status = "disabled";
};
wdt: wdt@20300 {
compatible = "marvell,orion-wdt";
reg = <0x20300 0x28>;
};
gpio0: gpio@d0400 {
compatible = "marvell,orion-gpio";
#gpio-cells = <2>;
@ -139,5 +145,14 @@
nr-ports = <1>;
status = "disabled";
};
crypto: crypto@30000 {
compatible = "marvell,orion-crypto";
reg = <0x30000 0x10000>,
<0xc8000000 0x800>;
reg-names = "regs", "sram";
interrupts = <31>;
status = "okay";
};
};
};

View File

@ -32,6 +32,7 @@
#include <linux/irq.h>
#include <plat/time.h>
#include <linux/platform_data/usb-ehci-orion.h>
#include <plat/irq.h>
#include <plat/common.h>
#include <plat/addr-map.h>
#include "common.h"
@ -109,8 +110,8 @@ static void __init dove_clk_init(void)
orion_clkdev_add(NULL, "orion-ehci.0", usb0);
orion_clkdev_add(NULL, "orion-ehci.1", usb1);
orion_clkdev_add(NULL, "mv643xx_eth.0", ge);
orion_clkdev_add("0", "sata_mv.0", sata);
orion_clkdev_add(NULL, "mv643xx_eth_port.0", ge);
orion_clkdev_add(NULL, "sata_mv.0", sata);
orion_clkdev_add("0", "pcie", pex0);
orion_clkdev_add("1", "pcie", pex1);
orion_clkdev_add(NULL, "sdhci-dove.0", sdio0);
@ -399,7 +400,7 @@ static void __init dove_dt_init(void)
(dove_tclk + 499999) / 1000000);
#ifdef CONFIG_CACHE_TAUROS2
tauros2_init();
tauros2_init(0);
#endif
dove_setup_cpu_mbus();
@ -415,7 +416,6 @@ static void __init dove_dt_init(void)
dove_ehci0_init();
dove_ehci1_init();
dove_pcie_init(1, 1);
dove_crypto_init();
of_platform_populate(NULL, of_default_bus_match_table,
dove_auxdata_lookup, NULL);

View File

@ -10,6 +10,7 @@
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/clk.h>
#include <video/vga.h>
#include <asm/mach/pci.h>
#include <asm/mach/arch.h>
@ -188,6 +189,10 @@ static void __init add_pcie_port(int index, void __iomem *base)
if (orion_pcie_link_up(base)) {
struct pcie_port *pp = &pcie_port[num_pcie_ports++];
struct clk *clk = clk_get_sys("pcie", (index ? "1" : "0"));
if (!IS_ERR(clk))
clk_prepare_enable(clk);
printk(KERN_INFO "link up\n");