ASoC: cs42l43: Use fls to calculate the pre-divider for the PLL

Use fls to calculate the pre-divider and input frequency for the PLL,
this is marginally faster than the previous loop.

Suggested-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Link: https://msgid.link/r/20240125103117.2622095-7-ckeepax@opensource.cirrus.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Charles Keepax 2024-01-25 10:31:17 +00:00 committed by Mark Brown
parent fe04d1632c
commit 31c6e53a4d
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@ -1338,10 +1338,9 @@ static int cs42l43_enable_pll(struct cs42l43_codec *priv)
dev_dbg(priv->dev, "Enabling PLL at %uHz\n", freq);
while (freq > cs42l43_pll_configs[ARRAY_SIZE(cs42l43_pll_configs) - 1].freq) {
div++;
freq /= 2;
}
div = fls(freq) -
fls(cs42l43_pll_configs[ARRAY_SIZE(cs42l43_pll_configs) - 1].freq);
freq >>= div;
if (div <= CS42L43_PLL_REFCLK_DIV_MASK) {
int i;