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ath9k_hw: Implement PLL control on AR9003

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Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Felix Fietkau 2010-04-15 17:38:34 -04:00 committed by John W. Linville
parent f7abf0c195
commit 317d33280c
2 changed files with 27 additions and 2 deletions
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23
drivers/net/wireless/ath/ath9k/ar9003_phy.c
View File

@ -112,8 +112,27 @@ static void ar9003_hw_spur_mitigate(struct ath_hw *ah,
static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah,
struct ath9k_channel *chan)
{
/* TODO */
return 0;
u32 pll;
pll = SM(0x5, AR_RTC_9300_PLL_REFDIV);
if (chan && IS_CHAN_HALF_RATE(chan))
pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL);
else if (chan && IS_CHAN_QUARTER_RATE(chan))
pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL);
if (chan && IS_CHAN_5GHZ(chan)) {
pll |= SM(0x28, AR_RTC_9300_PLL_DIV);
/*
* When doing fast clock, set PLL to 0x142c
*/
if (IS_CHAN_A_5MHZ_SPACED(chan))
pll = 0x142c;
} else
pll |= SM(0x2c, AR_RTC_9300_PLL_DIV);
return pll;
}
static void ar9003_hw_set_channel_regs(struct ath_hw *ah,

6
drivers/net/wireless/ath/ath9k/reg.h
View File

@ -1040,6 +1040,12 @@ enum {
#define AR_PCIE_MSI (AR_SREV_9300_20_OR_LATER(ah) ? 0x40a4 : 0x4094)
#define AR_PCIE_MSI_ENABLE 0x00000001
#define AR_RTC_9300_PLL_DIV 0x000003ff
#define AR_RTC_9300_PLL_DIV_S 0
#define AR_RTC_9300_PLL_REFDIV 0x00003C00
#define AR_RTC_9300_PLL_REFDIV_S 10
#define AR_RTC_9300_PLL_CLKSEL 0x0000C000
#define AR_RTC_9300_PLL_CLKSEL_S 14
#define AR_RTC_9160_PLL_DIV 0x000003ff
#define AR_RTC_9160_PLL_DIV_S 0