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ARM: dts: hisilicon: fix errors detected by snps-dw-apb-uart.yaml
1. Change node name to match '^serial(@[0-9a-f,]+)*$' 2. Change clock-names to "baudclk", "apb_pclk". Both of them use the same clock. Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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@ -41,41 +41,41 @@
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compatible = "simple-bus";
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ranges;
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uart0: uart@10001000 {
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uart0: serial@10001000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x10001000 0x1000>;
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clocks = <&hisi_refclk144mhz>;
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clock-names = "apb_pclk";
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clocks = <&hisi_refclk144mhz>, <&hisi_refclk144mhz>;
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clock-names = "baudclk", "apb_pclk";
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reg-shift = <2>;
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interrupts = <0 32 4>;
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status = "disabled";
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};
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uart1: uart@10002000 {
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uart1: serial@10002000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x10002000 0x1000>;
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clocks = <&hisi_refclk144mhz>;
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clock-names = "apb_pclk";
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clocks = <&hisi_refclk144mhz>, <&hisi_refclk144mhz>;
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clock-names = "baudclk", "apb_pclk";
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reg-shift = <2>;
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interrupts = <0 33 4>;
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status = "disabled";
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};
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uart2: uart@10003000 {
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uart2: serial@10003000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x10003000 0x1000>;
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clocks = <&hisi_refclk144mhz>;
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clock-names = "apb_pclk";
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clocks = <&hisi_refclk144mhz>, <&hisi_refclk144mhz>;
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clock-names = "baudclk", "apb_pclk";
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reg-shift = <2>;
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interrupts = <0 34 4>;
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status = "disabled";
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};
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uart3: uart@10006000 {
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uart3: serial@10006000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x10006000 0x1000>;
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clocks = <&hisi_refclk144mhz>;
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clock-names = "apb_pclk";
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clocks = <&hisi_refclk144mhz>, <&hisi_refclk144mhz>;
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clock-names = "baudclk", "apb_pclk";
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reg-shift = <2>;
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interrupts = <0 4 4>;
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status = "disabled";
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@ -22,7 +22,7 @@
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};
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soc {
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uart0: uart@4007000 {
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uart0: serial@4007000 {
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status = "ok";
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};
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};
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@ -250,12 +250,12 @@
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<0 79 4>;
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};
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uart0: uart@4007000 {
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uart0: serial@4007000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x4007000 0x1000>;
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interrupts = <0 381 4>;
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clocks = <&clk_168m>;
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clock-names = "uartclk";
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clocks = <&clk_168m>, <&clk_168m>;
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clock-names = "baudclk", "apb_pclk";
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reg-shift = <2>;
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status = "disabled";
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};
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