Merge branch 'enable-rx-hw-timestamp-for-ptp-packets-using-cpts-fifo'

Chintan Vankar says:

====================
Enable RX HW timestamp for PTP packets using CPTS FIFO

The CPSW offers two mechanisms for communicating packet ingress timestamp
information to the host.

The first mechanism is via the CPTS Event FIFO which records timestamp
when triggered by certain events. One such event is the reception of an
Ethernet packet with a specified EtherType field. This is used to capture
ingress timestamps for PTP packets. With this mechanism the host must
read the timestamp (from the CPTS FIFO) separately from the packet payload
which is delivered via DMA.

In the second mechanism of timestamping, CPSW driver enables hardware
timestamping for all received packets by setting the TSTAMP_EN bit in
CPTS_CONTROL register, which directs the CPTS module to timestamp all
received packets, followed by passing timestamp via DMA descriptors.
This mechanism is responsible for triggering errata i2401:
"CPSW: Host Timestamps Cause CPSW Port to Lock up."

The errata affects all K3 SoCs. Link to errata for AM64x:
https://www.ti.com/lit/er/sprz457h/sprz457h.pdf

As a workaround we can use first mechanism to timestamp received
packets.
====================

Link: https://lore.kernel.org/r/20240419082626.57225-1-c-vankar@ti.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
This commit is contained in:
Paolo Abeni 2024-04-23 12:07:25 +02:00
commit 30b3fe0672
4 changed files with 118 additions and 64 deletions

View File

@ -695,6 +695,17 @@ static int am65_cpsw_get_ethtool_ts_info(struct net_device *ndev,
struct ethtool_ts_info *info)
{
struct am65_cpsw_common *common = am65_ndev_to_common(ndev);
unsigned int ptp_v2_filter;
ptp_v2_filter = BIT(HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
BIT(HWTSTAMP_FILTER_PTP_V2_L4_SYNC) |
BIT(HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) |
BIT(HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
BIT(HWTSTAMP_FILTER_PTP_V2_L2_SYNC) |
BIT(HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ) |
BIT(HWTSTAMP_FILTER_PTP_V2_EVENT) |
BIT(HWTSTAMP_FILTER_PTP_V2_SYNC) |
BIT(HWTSTAMP_FILTER_PTP_V2_DELAY_REQ);
if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS))
return ethtool_op_get_ts_info(ndev, info);
@ -708,7 +719,7 @@ static int am65_cpsw_get_ethtool_ts_info(struct net_device *ndev,
SOF_TIMESTAMPING_RAW_HARDWARE;
info->phc_index = am65_cpts_phc_index(common->cpts);
info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON);
info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | BIT(HWTSTAMP_FILTER_ALL);
info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | ptp_v2_filter;
return 0;
}

View File

@ -103,6 +103,12 @@
#define AM65_CPSW_PN_TS_CTL_TX_HOST_TS_EN BIT(11)
#define AM65_CPSW_PN_TS_CTL_MSG_TYPE_EN_SHIFT 16
#define AM65_CPSW_PN_TS_CTL_RX_ANX_F_EN BIT(0)
#define AM65_CPSW_PN_TS_CTL_RX_VLAN_LT1_EN BIT(1)
#define AM65_CPSW_PN_TS_CTL_RX_VLAN_LT2_EN BIT(2)
#define AM65_CPSW_PN_TS_CTL_RX_ANX_D_EN BIT(3)
#define AM65_CPSW_PN_TS_CTL_RX_ANX_E_EN BIT(9)
/* AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG register fields */
#define AM65_CPSW_PN_TS_SEQ_ID_OFFSET_SHIFT 16
@ -126,6 +132,11 @@
AM65_CPSW_PN_TS_CTL_TX_ANX_E_EN | \
AM65_CPSW_PN_TS_CTL_TX_ANX_F_EN)
#define AM65_CPSW_TS_RX_ANX_ALL_EN \
(AM65_CPSW_PN_TS_CTL_RX_ANX_D_EN | \
AM65_CPSW_PN_TS_CTL_RX_ANX_E_EN | \
AM65_CPSW_PN_TS_CTL_RX_ANX_F_EN)
#define AM65_CPSW_ALE_AGEOUT_DEFAULT 30
/* Number of TX/RX descriptors */
#define AM65_CPSW_MAX_TX_DESC 500
@ -1050,18 +1061,6 @@ out:
return ret;
}
static void am65_cpsw_nuss_rx_ts(struct sk_buff *skb, u32 *psdata)
{
struct skb_shared_hwtstamps *ssh;
u64 ns;
ns = ((u64)psdata[1] << 32) | psdata[0];
ssh = skb_hwtstamps(skb);
memset(ssh, 0, sizeof(*ssh));
ssh->hwtstamp = ns_to_ktime(ns);
}
/* RX psdata[2] word format - checksum information */
#define AM65_CPSW_RX_PSD_CSUM_ADD GENMASK(15, 0)
#define AM65_CPSW_RX_PSD_CSUM_ERR BIT(16)
@ -1177,13 +1176,11 @@ static int am65_cpsw_nuss_rx_packets(struct am65_cpsw_common *common,
skb_reserve(skb, headroom);
}
/* Pass skb to netstack if no XDP prog or returned XDP_PASS */
if (port->rx_ts_enabled)
am65_cpsw_nuss_rx_ts(skb, psdata);
ndev_priv = netdev_priv(ndev);
am65_cpsw_nuss_set_offload_fwd_mark(skb, ndev_priv->offload_fwd_mark);
skb_put(skb, pkt_len);
if (port->rx_ts_enabled)
am65_cpts_rx_timestamp(common->cpts, skb);
skb_mark_for_recycle(skb);
skb->protocol = eth_type_trans(skb, ndev);
am65_cpsw_nuss_rx_csum(skb, csum_info);
@ -1736,7 +1733,6 @@ static int am65_cpsw_nuss_ndo_slave_set_mac_address(struct net_device *ndev,
static int am65_cpsw_nuss_hwtstamp_set(struct net_device *ndev,
struct ifreq *ifr)
{
struct am65_cpsw_common *common = am65_ndev_to_common(ndev);
struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
u32 ts_ctrl, seq_id, ts_ctrl_ltype2, ts_vlan_ltype;
struct hwtstamp_config cfg;
@ -1760,11 +1756,6 @@ static int am65_cpsw_nuss_hwtstamp_set(struct net_device *ndev,
case HWTSTAMP_FILTER_NONE:
port->rx_ts_enabled = false;
break;
case HWTSTAMP_FILTER_ALL:
case HWTSTAMP_FILTER_SOME:
case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
@ -1774,10 +1765,13 @@ static int am65_cpsw_nuss_hwtstamp_set(struct net_device *ndev,
case HWTSTAMP_FILTER_PTP_V2_EVENT:
case HWTSTAMP_FILTER_PTP_V2_SYNC:
case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
case HWTSTAMP_FILTER_NTP_ALL:
port->rx_ts_enabled = true;
cfg.rx_filter = HWTSTAMP_FILTER_ALL;
cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
break;
case HWTSTAMP_FILTER_ALL:
case HWTSTAMP_FILTER_SOME:
case HWTSTAMP_FILTER_NTP_ALL:
return -EOPNOTSUPP;
default:
return -ERANGE;
}
@ -1807,6 +1801,10 @@ static int am65_cpsw_nuss_hwtstamp_set(struct net_device *ndev,
ts_ctrl |= AM65_CPSW_TS_TX_ANX_ALL_EN |
AM65_CPSW_PN_TS_CTL_TX_VLAN_LT1_EN;
if (port->rx_ts_enabled)
ts_ctrl |= AM65_CPSW_TS_RX_ANX_ALL_EN |
AM65_CPSW_PN_TS_CTL_RX_VLAN_LT1_EN;
writel(seq_id, port->port_base + AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG);
writel(ts_vlan_ltype, port->port_base +
AM65_CPSW_PORTN_REG_TS_VLAN_LTYPE_REG);
@ -1814,9 +1812,6 @@ static int am65_cpsw_nuss_hwtstamp_set(struct net_device *ndev,
AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2);
writel(ts_ctrl, port->port_base + AM65_CPSW_PORTN_REG_TS_CTL);
/* en/dis RX timestamp */
am65_cpts_rx_enable(common->cpts, port->rx_ts_enabled);
return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
}
@ -1833,7 +1828,7 @@ static int am65_cpsw_nuss_hwtstamp_get(struct net_device *ndev,
cfg.tx_type = port->tx_ts_enabled ?
HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
cfg.rx_filter = port->rx_ts_enabled ?
HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE;
HWTSTAMP_FILTER_PTP_V2_EVENT : HWTSTAMP_FILTER_NONE;
return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
}

View File

@ -275,15 +275,13 @@ static bool am65_cpts_fifo_pop_event(struct am65_cpts *cpts,
return true;
}
static int am65_cpts_fifo_read(struct am65_cpts *cpts)
static int __am65_cpts_fifo_read(struct am65_cpts *cpts)
{
struct ptp_clock_event pevent;
struct am65_cpts_event *event;
bool schedule = false;
int i, type, ret = 0;
unsigned long flags;
spin_lock_irqsave(&cpts->lock, flags);
for (i = 0; i < AM65_CPTS_FIFO_DEPTH; i++) {
event = list_first_entry_or_null(&cpts->pool,
struct am65_cpts_event, list);
@ -312,8 +310,7 @@ static int am65_cpts_fifo_read(struct am65_cpts *cpts)
event->tmo = jiffies +
msecs_to_jiffies(AM65_CPTS_EVENT_RX_TX_TIMEOUT);
list_del_init(&event->list);
list_add_tail(&event->list, &cpts->events);
list_move_tail(&event->list, &cpts->events);
dev_dbg(cpts->dev,
"AM65_CPTS_EV_TX e1:%08x e2:%08x t:%lld\n",
@ -356,14 +353,24 @@ static int am65_cpts_fifo_read(struct am65_cpts *cpts)
}
out:
spin_unlock_irqrestore(&cpts->lock, flags);
if (schedule)
ptp_schedule_worker(cpts->ptp_clock, 0);
return ret;
}
static int am65_cpts_fifo_read(struct am65_cpts *cpts)
{
unsigned long flags;
int ret = 0;
spin_lock_irqsave(&cpts->lock, flags);
ret = __am65_cpts_fifo_read(cpts);
spin_unlock_irqrestore(&cpts->lock, flags);
return ret;
}
static u64 am65_cpts_gettime(struct am65_cpts *cpts,
struct ptp_system_timestamp *sts)
{
@ -859,29 +866,6 @@ static long am65_cpts_ts_work(struct ptp_clock_info *ptp)
return delay;
}
/**
* am65_cpts_rx_enable - enable rx timestamping
* @cpts: cpts handle
* @en: enable
*
* This functions enables rx packets timestamping. The CPTS can timestamp all
* rx packets.
*/
void am65_cpts_rx_enable(struct am65_cpts *cpts, bool en)
{
u32 val;
mutex_lock(&cpts->ptp_clk_lock);
val = am65_cpts_read32(cpts, control);
if (en)
val |= AM65_CPTS_CONTROL_TSTAMP_EN;
else
val &= ~AM65_CPTS_CONTROL_TSTAMP_EN;
am65_cpts_write32(cpts, val, control);
mutex_unlock(&cpts->ptp_clk_lock);
}
EXPORT_SYMBOL_GPL(am65_cpts_rx_enable);
static int am65_skb_get_mtype_seqid(struct sk_buff *skb, u32 *mtype_seqid)
{
unsigned int ptp_class = ptp_classify_raw(skb);
@ -906,6 +890,69 @@ static int am65_skb_get_mtype_seqid(struct sk_buff *skb, u32 *mtype_seqid)
return 1;
}
static u64 am65_cpts_find_rx_ts(struct am65_cpts *cpts, u32 skb_mtype_seqid)
{
struct list_head *this, *next;
struct am65_cpts_event *event;
unsigned long flags;
u32 mtype_seqid;
u64 ns = 0;
spin_lock_irqsave(&cpts->lock, flags);
__am65_cpts_fifo_read(cpts);
list_for_each_safe(this, next, &cpts->events) {
event = list_entry(this, struct am65_cpts_event, list);
if (time_after(jiffies, event->tmo)) {
list_move(&event->list, &cpts->pool);
continue;
}
mtype_seqid = event->event1 &
(AM65_CPTS_EVENT_1_MESSAGE_TYPE_MASK |
AM65_CPTS_EVENT_1_SEQUENCE_ID_MASK |
AM65_CPTS_EVENT_1_EVENT_TYPE_MASK);
if (mtype_seqid == skb_mtype_seqid) {
ns = event->timestamp;
list_move(&event->list, &cpts->pool);
break;
}
}
spin_unlock_irqrestore(&cpts->lock, flags);
return ns;
}
void am65_cpts_rx_timestamp(struct am65_cpts *cpts, struct sk_buff *skb)
{
struct am65_cpts_skb_cb_data *skb_cb = (struct am65_cpts_skb_cb_data *)skb->cb;
struct skb_shared_hwtstamps *ssh;
int ret;
u64 ns;
/* am65_cpts_rx_timestamp() is called before eth_type_trans(), so
* skb MAC Hdr properties are not configured yet. Hence need to
* reset skb MAC header here
*/
skb_reset_mac_header(skb);
ret = am65_skb_get_mtype_seqid(skb, &skb_cb->skb_mtype_seqid);
if (!ret)
return; /* if not PTP class packet */
skb_cb->skb_mtype_seqid |= (AM65_CPTS_EV_RX << AM65_CPTS_EVENT_1_EVENT_TYPE_SHIFT);
dev_dbg(cpts->dev, "%s mtype seqid %08x\n", __func__, skb_cb->skb_mtype_seqid);
ns = am65_cpts_find_rx_ts(cpts, skb_cb->skb_mtype_seqid);
if (!ns)
return;
ssh = skb_hwtstamps(skb);
memset(ssh, 0, sizeof(*ssh));
ssh->hwtstamp = ns_to_ktime(ns);
}
EXPORT_SYMBOL_GPL(am65_cpts_rx_timestamp);
/**
* am65_cpts_tx_timestamp - save tx packet for timestamping
* @cpts: cpts handle

View File

@ -22,9 +22,9 @@ void am65_cpts_release(struct am65_cpts *cpts);
struct am65_cpts *am65_cpts_create(struct device *dev, void __iomem *regs,
struct device_node *node);
int am65_cpts_phc_index(struct am65_cpts *cpts);
void am65_cpts_rx_timestamp(struct am65_cpts *cpts, struct sk_buff *skb);
void am65_cpts_tx_timestamp(struct am65_cpts *cpts, struct sk_buff *skb);
void am65_cpts_prep_tx_timestamp(struct am65_cpts *cpts, struct sk_buff *skb);
void am65_cpts_rx_enable(struct am65_cpts *cpts, bool en);
u64 am65_cpts_ns_gettime(struct am65_cpts *cpts);
int am65_cpts_estf_enable(struct am65_cpts *cpts, int idx,
struct am65_cpts_estf_cfg *cfg);
@ -48,6 +48,11 @@ static inline int am65_cpts_phc_index(struct am65_cpts *cpts)
return -1;
}
static inline void am65_cpts_rx_timestamp(struct am65_cpts *cpts,
struct sk_buff *skb)
{
}
static inline void am65_cpts_tx_timestamp(struct am65_cpts *cpts,
struct sk_buff *skb)
{
@ -58,10 +63,6 @@ static inline void am65_cpts_prep_tx_timestamp(struct am65_cpts *cpts,
{
}
static inline void am65_cpts_rx_enable(struct am65_cpts *cpts, bool en)
{
}
static inline s64 am65_cpts_ns_gettime(struct am65_cpts *cpts)
{
return 0;