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x86/entry/64: Use PUSH_AND_CLEAN_REGS in more cases
entry_SYSCALL_64_after_hwframe() and nmi() can be converted to use PUSH_AND_CLEAN_REGS instead of opencoded variants thereof. Due to the interleaving, the additional XOR-based clearing of R8 and R9 in entry_SYSCALL_64_after_hwframe() should not have any noticeable negative implications. Suggested-by: Linus Torvalds <torvalds@linux-foundation.org> Signed-off-by: Dominik Brodowski <linux@dominikbrodowski.net> Cc: Andy Lutomirski <luto@kernel.org> Cc: Borislav Petkov <bp@alien8.de> Cc: Brian Gerst <brgerst@gmail.com> Cc: Denys Vlasenko <dvlasenk@redhat.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Josh Poimboeuf <jpoimboe@redhat.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: dan.j.williams@intel.com Link: http://lkml.kernel.org/r/20180211104949.12992-6-linux@dominikbrodowski.net Signed-off-by: Ingo Molnar <mingo@kernel.org>
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@ -137,7 +137,7 @@ For 32-bit we have the following conventions - kernel is built with
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UNWIND_HINT_REGS offset=\offset
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.endm
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.macro PUSH_AND_CLEAR_REGS
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.macro PUSH_AND_CLEAR_REGS rdx=%rdx rax=%rax
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/*
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* Push registers and sanitize registers of values that a
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* speculation attack might otherwise want to exploit. The
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@ -147,9 +147,9 @@ For 32-bit we have the following conventions - kernel is built with
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*/
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pushq %rdi /* pt_regs->di */
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pushq %rsi /* pt_regs->si */
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pushq %rdx /* pt_regs->dx */
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pushq \rdx /* pt_regs->dx */
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pushq %rcx /* pt_regs->cx */
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pushq %rax /* pt_regs->ax */
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pushq \rax /* pt_regs->ax */
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pushq %r8 /* pt_regs->r8 */
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xorq %r8, %r8 /* nospec r8 */
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pushq %r9 /* pt_regs->r9 */
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@ -227,35 +227,8 @@ ENTRY(entry_SYSCALL_64)
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pushq %rcx /* pt_regs->ip */
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GLOBAL(entry_SYSCALL_64_after_hwframe)
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pushq %rax /* pt_regs->orig_ax */
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pushq %rdi /* pt_regs->di */
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pushq %rsi /* pt_regs->si */
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pushq %rdx /* pt_regs->dx */
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pushq %rcx /* pt_regs->cx */
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pushq $-ENOSYS /* pt_regs->ax */
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pushq %r8 /* pt_regs->r8 */
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pushq %r9 /* pt_regs->r9 */
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pushq %r10 /* pt_regs->r10 */
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/*
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* Clear extra registers that a speculation attack might
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* otherwise want to exploit. Interleave XOR with PUSH
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* for better uop scheduling:
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*/
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xorq %r10, %r10 /* nospec r10 */
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pushq %r11 /* pt_regs->r11 */
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xorq %r11, %r11 /* nospec r11 */
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pushq %rbx /* pt_regs->rbx */
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xorl %ebx, %ebx /* nospec rbx */
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pushq %rbp /* pt_regs->rbp */
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xorl %ebp, %ebp /* nospec rbp */
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pushq %r12 /* pt_regs->r12 */
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xorq %r12, %r12 /* nospec r12 */
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pushq %r13 /* pt_regs->r13 */
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xorq %r13, %r13 /* nospec r13 */
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pushq %r14 /* pt_regs->r14 */
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xorq %r14, %r14 /* nospec r14 */
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pushq %r15 /* pt_regs->r15 */
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xorq %r15, %r15 /* nospec r15 */
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UNWIND_HINT_REGS
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PUSH_AND_CLEAR_REGS rax=$-ENOSYS
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TRACE_IRQS_OFF
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@ -1388,39 +1361,7 @@ ENTRY(nmi)
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pushq 1*8(%rdx) /* pt_regs->rip */
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UNWIND_HINT_IRET_REGS
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pushq $-1 /* pt_regs->orig_ax */
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pushq %rdi /* pt_regs->di */
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pushq %rsi /* pt_regs->si */
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pushq (%rdx) /* pt_regs->dx */
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pushq %rcx /* pt_regs->cx */
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pushq %rax /* pt_regs->ax */
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/*
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* Sanitize registers of values that a speculation attack
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* might otherwise want to exploit. The lower registers are
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* likely clobbered well before they could be put to use in
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* a speculative execution gadget. Interleave XOR with PUSH
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* for better uop scheduling:
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*/
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pushq %r8 /* pt_regs->r8 */
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xorq %r8, %r8 /* nospec r8 */
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pushq %r9 /* pt_regs->r9 */
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xorq %r9, %r9 /* nospec r9 */
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pushq %r10 /* pt_regs->r10 */
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xorq %r10, %r10 /* nospec r10 */
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pushq %r11 /* pt_regs->r11 */
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xorq %r11, %r11 /* nospec r11*/
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pushq %rbx /* pt_regs->rbx */
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xorl %ebx, %ebx /* nospec rbx*/
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pushq %rbp /* pt_regs->rbp */
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xorl %ebp, %ebp /* nospec rbp*/
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pushq %r12 /* pt_regs->r12 */
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xorq %r12, %r12 /* nospec r12*/
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pushq %r13 /* pt_regs->r13 */
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xorq %r13, %r13 /* nospec r13*/
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pushq %r14 /* pt_regs->r14 */
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xorq %r14, %r14 /* nospec r14*/
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pushq %r15 /* pt_regs->r15 */
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xorq %r15, %r15 /* nospec r15*/
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UNWIND_HINT_REGS
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PUSH_AND_CLEAR_REGS rdx=(%rdx)
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ENCODE_FRAME_POINTER
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/*
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