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pinctrl: sh-pfc: Updates for v4.9 (take three)

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- Return pinconf with arguments in packed format,
   - MSIOF and QSPI pin groups on R-Car V2H,
   - Voltage switching for SDHI on R-Car M2-W, E2, and M3-W.
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Merge tag 'sh-pfc-for-v4.9-tag3' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel

pinctrl: sh-pfc: Updates for v4.9 (take three)

  - Return pinconf with arguments in packed format,
  - MSIOF and QSPI pin groups on R-Car V2H,
  - Voltage switching for SDHI on R-Car M2-W, E2, and M3-W.
This commit is contained in:
Linus Walleij 2016-09-14 14:37:36 +02:00
commit 3049d1343f
6 changed files with 207 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

29
drivers/pinctrl/sh-pfc/pfc-r8a7791.c
View File

@ -13,6 +13,10 @@
#include "sh_pfc.h"
/*
* Pins 0-23 assigned to GPIO bank 6 can be used for SD interfaces in
* which case they support both 3.3V and 1.8V signalling.
*/
#define CPU_ALL_PORT(fn, sfx) \
PORT_GP_32(0, fn, sfx), \
PORT_GP_26(1, fn, sfx), \
@ -20,7 +24,15 @@
PORT_GP_32(3, fn, sfx), \
PORT_GP_32(4, fn, sfx), \
PORT_GP_32(5, fn, sfx), \
PORT_GP_32(6, fn, sfx), \
PORT_GP_CFG_24(6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_1(6, 24, fn, sfx), \
PORT_GP_1(6, 25, fn, sfx), \
PORT_GP_1(6, 26, fn, sfx), \
PORT_GP_1(6, 27, fn, sfx), \
PORT_GP_1(6, 28, fn, sfx), \
PORT_GP_1(6, 29, fn, sfx), \
PORT_GP_1(6, 30, fn, sfx), \
PORT_GP_1(6, 31, fn, sfx), \
PORT_GP_26(7, fn, sfx)
enum {
@ -6404,9 +6416,24 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ },
};
static int r8a7791_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
{
if (pin < RCAR_GP_PIN(6, 0) || pin > RCAR_GP_PIN(6, 23))
return -EINVAL;
*pocctrl = 0xe606008c;
return 31 - (pin & 0x1f);
}
static const struct sh_pfc_soc_operations r8a7791_pinmux_ops = {
.pin_to_pocctrl = r8a7791_pin_to_pocctrl,
};
#ifdef CONFIG_PINCTRL_PFC_R8A7791
const struct sh_pfc_soc_info r8a7791_pinmux_info = {
.name = "r8a77910_pfc",
.ops = &r8a7791_pinmux_ops,
.unlock_reg = 0xe6060000, /* PMMR */
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },

115
drivers/pinctrl/sh-pfc/pfc-r8a7792.c
View File

@ -1034,6 +1034,87 @@ static const unsigned int lbsc_ex_cs5_pins[] = {
static const unsigned int lbsc_ex_cs5_mux[] = {
EX_CS5_N_MARK,
};
/* - MSIOF0 ----------------------------------------------------------------- */
static const unsigned int msiof0_clk_pins[] = {
/* SCK */
RCAR_GP_PIN(10, 0),
};
static const unsigned int msiof0_clk_mux[] = {
MSIOF0_SCK_MARK,
};
static const unsigned int msiof0_sync_pins[] = {
/* SYNC */
RCAR_GP_PIN(10, 1),
};
static const unsigned int msiof0_sync_mux[] = {
MSIOF0_SYNC_MARK,
};
static const unsigned int msiof0_rx_pins[] = {
/* RXD */
RCAR_GP_PIN(10, 4),
};
static const unsigned int msiof0_rx_mux[] = {
MSIOF0_RXD_MARK,
};
static const unsigned int msiof0_tx_pins[] = {
/* TXD */
RCAR_GP_PIN(10, 3),
};
static const unsigned int msiof0_tx_mux[] = {
MSIOF0_TXD_MARK,
};
/* - MSIOF1 ----------------------------------------------------------------- */
static const unsigned int msiof1_clk_pins[] = {
/* SCK */
RCAR_GP_PIN(10, 5),
};
static const unsigned int msiof1_clk_mux[] = {
MSIOF1_SCK_MARK,
};
static const unsigned int msiof1_sync_pins[] = {
/* SYNC */
RCAR_GP_PIN(10, 6),
};
static const unsigned int msiof1_sync_mux[] = {
MSIOF1_SYNC_MARK,
};
static const unsigned int msiof1_rx_pins[] = {
/* RXD */
RCAR_GP_PIN(10, 9),
};
static const unsigned int msiof1_rx_mux[] = {
MSIOF1_RXD_MARK,
};
static const unsigned int msiof1_tx_pins[] = {
/* TXD */
RCAR_GP_PIN(10, 8),
};
static const unsigned int msiof1_tx_mux[] = {
MSIOF1_TXD_MARK,
};
/* - QSPI ------------------------------------------------------------------- */
static const unsigned int qspi_ctrl_pins[] = {
/* SPCLK, SSL */
RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
};
static const unsigned int qspi_ctrl_mux[] = {
SPCLK_MARK, SSL_MARK,
};
static const unsigned int qspi_data2_pins[] = {
/* MOSI_IO0, MISO_IO1 */
RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
};
static const unsigned int qspi_data2_mux[] = {
MOSI_IO0_MARK, MISO_IO1_MARK,
};
static const unsigned int qspi_data4_pins[] = {
/* MOSI_IO0, MISO_IO1, IO2, IO3 */
RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 23),
RCAR_GP_PIN(3, 24),
};
static const unsigned int qspi_data4_mux[] = {
MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
};
/* - SCIF0 ------------------------------------------------------------------ */
static const unsigned int scif0_data_pins[] = {
/* RX, TX */
@ -1585,6 +1666,17 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(lbsc_ex_cs3),
SH_PFC_PIN_GROUP(lbsc_ex_cs4),
SH_PFC_PIN_GROUP(lbsc_ex_cs5),
SH_PFC_PIN_GROUP(msiof0_clk),
SH_PFC_PIN_GROUP(msiof0_sync),
SH_PFC_PIN_GROUP(msiof0_rx),
SH_PFC_PIN_GROUP(msiof0_tx),
SH_PFC_PIN_GROUP(msiof1_clk),
SH_PFC_PIN_GROUP(msiof1_sync),
SH_PFC_PIN_GROUP(msiof1_rx),
SH_PFC_PIN_GROUP(msiof1_tx),
SH_PFC_PIN_GROUP(qspi_ctrl),
SH_PFC_PIN_GROUP(qspi_data2),
SH_PFC_PIN_GROUP(qspi_data4),
SH_PFC_PIN_GROUP(scif0_data),
SH_PFC_PIN_GROUP(scif0_clk),
SH_PFC_PIN_GROUP(scif0_ctrl),
@ -1708,6 +1800,26 @@ static const char * const lbsc_groups[] = {
"lbsc_ex_cs5",
};
static const char * const msiof0_groups[] = {
"msiof0_clk",
"msiof0_sync",
"msiof0_rx",
"msiof0_tx",
};
static const char * const msiof1_groups[] = {
"msiof1_clk",
"msiof1_sync",
"msiof1_rx",
"msiof1_tx",
};
static const char * const qspi_groups[] = {
"qspi_ctrl",
"qspi_data2",
"qspi_data4",
};
static const char * const scif0_groups[] = {
"scif0_data",
"scif0_clk",
@ -1808,6 +1920,9 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(du1),
SH_PFC_FUNCTION(intc),
SH_PFC_FUNCTION(lbsc),
SH_PFC_FUNCTION(msiof0),
SH_PFC_FUNCTION(msiof1),
SH_PFC_FUNCTION(qspi),
SH_PFC_FUNCTION(scif0),
SH_PFC_FUNCTION(scif3),
SH_PFC_FUNCTION(sdhi0),

28
drivers/pinctrl/sh-pfc/pfc-r8a7794.c
View File

@ -22,7 +22,9 @@
PORT_GP_32(3, fn, sfx), \
PORT_GP_32(4, fn, sfx), \
PORT_GP_28(5, fn, sfx), \
PORT_GP_26(6, fn, sfx)
PORT_GP_CFG_24(6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_1(6, 24, fn, sfx), \
PORT_GP_1(6, 25, fn, sfx)
enum {
PINMUX_RESERVED = 0,
@ -5160,8 +5162,32 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ },
};
static int r8a7794_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
{
*pocctrl = 0xe606006c;
switch (pin & 0x1f) {
case 6: return 23;
case 7: return 16;
case 14: return 15;
case 15: return 8;
case 0 ... 5:
case 8 ... 13:
return 22 - (pin & 0x1f);
case 16 ... 23:
return 47 - (pin & 0x1f);
}
return -EINVAL;
}
static const struct sh_pfc_soc_operations r8a7794_pinmux_ops = {
.pin_to_pocctrl = r8a7794_pin_to_pocctrl,
};
const struct sh_pfc_soc_info r8a7794_pinmux_info = {
.name = "r8a77940_pfc",
.ops = &r8a7794_pinmux_ops,
.unlock_reg = 0xe6060000, /* PMMR */
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },

28
drivers/pinctrl/sh-pfc/pfc-r8a7796.c
View File

@ -23,8 +23,12 @@
PORT_GP_16(0, fn, sfx), \
PORT_GP_29(1, fn, sfx), \
PORT_GP_15(2, fn, sfx), \
PORT_GP_16(3, fn, sfx), \
PORT_GP_18(4, fn, sfx), \
PORT_GP_CFG_12(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_1(3, 12, fn, sfx), \
PORT_GP_1(3, 13, fn, sfx), \
PORT_GP_1(3, 14, fn, sfx), \
PORT_GP_1(3, 15, fn, sfx), \
PORT_GP_CFG_18(4, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_26(5, fn, sfx), \
PORT_GP_32(6, fn, sfx), \
PORT_GP_4(7, fn, sfx)
@ -2627,8 +2631,28 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ },
};
static int r8a7796_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
{
int bit = -EINVAL;
*pocctrl = 0xe6060380;
if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
bit = pin & 0x1f;
if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
bit = (pin & 0x1f) + 12;
return bit;
}
static const struct sh_pfc_soc_operations r8a7796_pinmux_ops = {
.pin_to_pocctrl = r8a7796_pin_to_pocctrl,
};
const struct sh_pfc_soc_info r8a7796_pinmux_info = {
.name = "r8a77960_pfc",
.ops = &r8a7796_pinmux_ops,
.unlock_reg = 0xe6060000, /* PMMR */
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },

8
drivers/pinctrl/sh-pfc/pinctrl.c
View File

@ -596,6 +596,7 @@ static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin,
struct sh_pfc *pfc = pmx->pfc;
enum pin_config_param param = pinconf_to_config_param(*config);
unsigned long flags;
unsigned int arg;
if (!sh_pfc_pinconf_validate(pfc, _pin, param))
return -ENOTSUPP;
@ -616,7 +617,7 @@ static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin,
if (bias != param)
return -EINVAL;
*config = 0;
arg = 0;
break;
}
@ -627,7 +628,7 @@ static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin,
if (ret < 0)
return ret;
*config = ret;
arg = ret;
break;
}
@ -646,7 +647,7 @@ static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin,
val = sh_pfc_read_reg(pfc, pocctrl, 32);
spin_unlock_irqrestore(&pfc->lock, flags);
*config = (val & BIT(bit)) ? 3300 : 1800;
arg = (val & BIT(bit)) ? 3300 : 1800;
break;
}
@ -654,6 +655,7 @@ static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin,
return -ENOTSUPP;
}
*config = pinconf_to_config_packed(param, arg);
return 0;
}

8
drivers/pinctrl/sh-pfc/sh_pfc.h
View File

@ -422,9 +422,13 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info;
PORT_GP_CFG_1(bank, 22, fn, sfx, cfg)
#define PORT_GP_23(bank, fn, sfx) PORT_GP_CFG_23(bank, fn, sfx, 0)
#define PORT_GP_CFG_26(bank, fn, sfx, cfg) \
#define PORT_GP_CFG_24(bank, fn, sfx, cfg) \
PORT_GP_CFG_23(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 23, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 23, fn, sfx, cfg)
#define PORT_GP_24(bank, fn, sfx) PORT_GP_CFG_24(bank, fn, sfx, 0)
#define PORT_GP_CFG_26(bank, fn, sfx, cfg) \
PORT_GP_CFG_24(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 24, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 25, fn, sfx, cfg)
#define PORT_GP_26(bank, fn, sfx) PORT_GP_CFG_26(bank, fn, sfx, 0)