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staging: mt7621-pci: rewrite hardcoded code for enabling ports
There are some hardcoded values in the process for enabling and disabling some stuff inside 'mt7621_pcie_enable_ports' function. Create some preprocessor definitions to make code more readable. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -80,6 +80,13 @@
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#define RALINK_PCI_STATUS 0x0050
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/* Some definition values */
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#define PCIE_REVISION_ID BIT(0)
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#define PCIE_CLASS_CODE (0x60400 << 8)
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#define PCIE_BAR_MAP_MAX GENMASK(30, 16)
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#define PCIE_BAR_ENABLE BIT(0)
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#define PCIE_PORT_INT_EN(x) BIT(20 + (x))
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#define PCIE_PORT_CLK_EN(x) BIT(24 + (x))
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#define RALINK_PCI_IO_MAP_BASE 0x1e160000
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#define MEMORY_BASE 0x0
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@ -584,13 +591,13 @@ static int mt7621_pcie_init_port(struct mt7621_pcie_port *port)
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if ((pcie_port_read(port, RALINK_PCI_STATUS) & 0x1) == 0) {
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dev_err(dev, "pcie%d no card, disable it (RST & CLK)\n", slot);
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reset_control_assert(port->pcie_rst);
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rt_sysc_m32(BIT(24 + slot), 0, RALINK_CLKCFG1);
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rt_sysc_m32(PCIE_PORT_CLK_EN(slot), 0, RALINK_CLKCFG1);
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port->enabled = false;
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} else {
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port->enabled = true;
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val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
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/* enable pcie interrupt */
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val |= BIT(20 + slot);
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val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
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val |= PCIE_PORT_INT_EN(slot);
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pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
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}
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@ -633,12 +640,14 @@ static void mt7621_pcie_enable_ports(struct mt7621_pcie *pcie)
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offset = MT7621_PCIE_OFFSET + (slot * MT7621_NEXT_PORT);
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if (port->enabled) {
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/* open 7FFF:2G; ENABLE */
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pcie_write(pcie, 0x7FFF0001,
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/* map 2G DDR region */
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pcie_write(pcie, PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE,
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offset + RALINK_PCI_BAR0SETUP_ADDR);
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pcie_write(pcie, MEMORY_BASE,
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offset + RALINK_PCI_IMBASEBAR0_ADDR);
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pcie_write(pcie, 0x06040001, offset + RALINK_PCI_CLASS);
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/* configure class code and revision ID */
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pcie_write(pcie, PCIE_CLASS_CODE | PCIE_REVISION_ID,
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offset + RALINK_PCI_CLASS);
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dev_info(dev, "PCIE%d enabled\n", slot);
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num_slots_enabled++;
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}
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