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ARM OMAP2+ GPMC: calculate GPMCFCLKDIVIDER based on WAITMONITORINGTIME
The WAITMONITORINGTIME is expressed as a number of GPMC_CLK clock cycles, even though the access is defined as asynchronous, and no GPMC_CLK clock is provided to the external device. Still, GPMCFCLKDIVIDER is used as a divider for the GPMC clock, so it must be programmed to define the correct WAITMONITORINGTIME delay. Calculate GPMCFCLKDIVIDER independent of gpmc,sync-clk-ps in DT for pure asynchronous accesses, i.e. both read and write asynchronous. Signed-off-by: Robert ABEL <rabel@cit-ec.uni-bielefeld.de> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Roger Quadros <rogerq@ti.com>
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@ -96,14 +96,6 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
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gpmc_nand_res[1].start = gpmc_get_client_irq(GPMC_IRQ_FIFOEVENTENABLE);
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gpmc_nand_res[2].start = gpmc_get_client_irq(GPMC_IRQ_COUNT_EVENT);
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if (gpmc_t) {
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err = gpmc_cs_set_timings(gpmc_nand_data->cs, gpmc_t);
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if (err < 0) {
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pr_err("omap2-gpmc: Unable to set gpmc timings: %d\n", err);
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return err;
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}
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}
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memset(&s, 0, sizeof(struct gpmc_settings));
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if (gpmc_nand_data->of_node)
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gpmc_read_settings_dt(gpmc_nand_data->of_node, &s);
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@ -111,6 +103,16 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
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gpmc_set_legacy(gpmc_nand_data, &s);
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s.device_nand = true;
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if (gpmc_t) {
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err = gpmc_cs_set_timings(gpmc_nand_data->cs, gpmc_t, &s);
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if (err < 0) {
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pr_err("omap2-gpmc: Unable to set gpmc timings: %d\n",
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err);
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return err;
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}
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}
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err = gpmc_cs_program_settings(gpmc_nand_data->cs, &s);
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if (err < 0)
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goto out_free_cs;
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@ -293,7 +293,7 @@ static int omap2_onenand_setup_async(void __iomem *onenand_base)
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if (ret < 0)
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return ret;
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ret = gpmc_cs_set_timings(gpmc_onenand_data->cs, &t);
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ret = gpmc_cs_set_timings(gpmc_onenand_data->cs, &t, &onenand_async);
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if (ret < 0)
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return ret;
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@ -331,7 +331,7 @@ static int omap2_onenand_setup_sync(void __iomem *onenand_base, int *freq_ptr)
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if (ret < 0)
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return ret;
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ret = gpmc_cs_set_timings(gpmc_onenand_data->cs, &t);
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ret = gpmc_cs_set_timings(gpmc_onenand_data->cs, &t, &onenand_sync);
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if (ret < 0)
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return ret;
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@ -71,7 +71,7 @@ static int tusb_set_async_mode(unsigned sysclk_ps)
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gpmc_calc_timings(&t, &tusb_async, &dev_t);
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return gpmc_cs_set_timings(async_cs, &t);
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return gpmc_cs_set_timings(async_cs, &t, &tusb_async);
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}
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static int tusb_set_sync_mode(unsigned sysclk_ps)
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@ -98,7 +98,7 @@ static int tusb_set_sync_mode(unsigned sysclk_ps)
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gpmc_calc_timings(&t, &tusb_sync, &dev_t);
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return gpmc_cs_set_timings(sync_cs, &t);
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return gpmc_cs_set_timings(sync_cs, &t, &tusb_sync);
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}
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/* tusb driver calls this when it changes the chip's clocking */
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@ -138,7 +138,9 @@
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#define GPMC_CONFIG1_PAGE_LEN(val) ((val & 3) << 23)
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#define GPMC_CONFIG1_WAIT_READ_MON (1 << 22)
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#define GPMC_CONFIG1_WAIT_WRITE_MON (1 << 21)
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#define GPMC_CONFIG1_WAIT_MON_IIME(val) ((val & 3) << 18)
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#define GPMC_CONFIG1_WAIT_MON_TIME(val) ((val & 3) << 18)
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/** WAITMONITORINGTIME Max Ticks */
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#define GPMC_CONFIG1_WAITMONITORINGTIME_MAX 2
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#define GPMC_CONFIG1_WAIT_PIN_SEL(val) ((val & 3) << 16)
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#define GPMC_CONFIG1_DEVICESIZE(val) ((val & 3) << 12)
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#define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1)
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@ -525,13 +527,48 @@ static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
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t->field, #field) < 0) \
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return -1
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/**
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* gpmc_calc_waitmonitoring_divider - calculate proper GPMCFCLKDIVIDER based on WAITMONITORINGTIME
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* WAITMONITORINGTIME will be _at least_ as long as desired, i.e.
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* read --> don't sample bus too early
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* write --> data is longer on bus
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*
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* Formula:
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* gpmc_clk_div + 1 = ceil(ceil(waitmonitoringtime_ns / gpmc_fclk_ns)
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* / waitmonitoring_ticks)
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* WAITMONITORINGTIME resulting in 0 or 1 tick with div = 1 are caught by
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* div <= 0 check.
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*
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* @wait_monitoring: WAITMONITORINGTIME in ns.
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* @return: -1 on failure to scale, else proper divider > 0.
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*/
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static int gpmc_calc_waitmonitoring_divider(unsigned int wait_monitoring)
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{
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int div = gpmc_ns_to_ticks(wait_monitoring);
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div += GPMC_CONFIG1_WAITMONITORINGTIME_MAX - 1;
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div /= GPMC_CONFIG1_WAITMONITORINGTIME_MAX;
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if (div > 4)
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return -1;
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if (div <= 0)
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div = 1;
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return div;
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}
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/**
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* gpmc_calc_divider - calculate GPMC_FCLK divider for sync_clk GPMC_CLK period.
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* @sync_clk: GPMC_CLK period in ps.
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* @return: Returns at least 1 if GPMC_FCLK can be divided to GPMC_CLK.
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* Else, returns -1.
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*/
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int gpmc_calc_divider(unsigned int sync_clk)
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{
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int div;
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u32 l;
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int div = gpmc_ps_to_ticks(sync_clk);
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l = sync_clk + (gpmc_get_fclk_period() - 1);
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div = l / gpmc_get_fclk_period();
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if (div > 4)
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return -1;
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if (div <= 0)
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@ -540,7 +577,15 @@ int gpmc_calc_divider(unsigned int sync_clk)
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return div;
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}
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int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
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/**
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* gpmc_cs_set_timings - program timing parameters for Chip Select Region.
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* @cs: Chip Select Region.
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* @t: GPMC timing parameters.
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* @s: GPMC timing settings.
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* @return: 0 on success, -1 on error.
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*/
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int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t,
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const struct gpmc_settings *s)
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{
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int div;
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u32 l;
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@ -550,6 +595,33 @@ int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
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if (div < 0)
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return div;
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/*
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* See if we need to change the divider for waitmonitoringtime.
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*
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* Calculate GPMCFCLKDIVIDER independent of gpmc,sync-clk-ps in DT for
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* pure asynchronous accesses, i.e. both read and write asynchronous.
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* However, only do so if WAITMONITORINGTIME is actually used, i.e.
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* either WAITREADMONITORING or WAITWRITEMONITORING is set.
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*
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* This statement must not change div to scale async WAITMONITORINGTIME
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* to protect mixed synchronous and asynchronous accesses.
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*
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* We raise an error later if WAITMONITORINGTIME does not fit.
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*/
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if (!s->sync_read && !s->sync_write &&
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(s->wait_on_read || s->wait_on_write)
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) {
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div = gpmc_calc_waitmonitoring_divider(t->wait_monitoring);
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if (div < 0) {
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pr_err("%s: waitmonitoringtime %3d ns too large for greatest gpmcfclkdivider.\n",
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__func__,
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t->wait_monitoring
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);
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return -1;
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}
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}
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GPMC_SET_ONE(GPMC_CS_CONFIG2, 0, 3, cs_on);
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GPMC_SET_ONE(GPMC_CS_CONFIG2, 8, 12, cs_rd_off);
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GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
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@ -1810,7 +1882,7 @@ static int gpmc_probe_generic_child(struct platform_device *pdev,
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if (ret < 0)
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goto err;
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ret = gpmc_cs_set_timings(cs, &gpmc_t);
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ret = gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s);
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if (ret) {
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dev_err(&pdev->dev, "failed to set gpmc timings for: %s\n",
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child->name);
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@ -163,7 +163,8 @@ extern unsigned int gpmc_ticks_to_ns(unsigned int ticks);
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extern void gpmc_cs_write_reg(int cs, int idx, u32 val);
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extern int gpmc_calc_divider(unsigned int sync_clk);
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extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t);
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extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t,
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const struct gpmc_settings *s);
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extern int gpmc_cs_program_settings(int cs, struct gpmc_settings *p);
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extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
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extern void gpmc_cs_free(int cs);
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