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spi: atmel-quadspi: add support for sam9x60 qspi controller
The sam9x60 qspi controller uses 2 clocks, one for the peripheral register access, the other for the qspi core and phy. Both are mandatory. It uses different transfer type bits in IFR register. It has dedicated registers to specify a read or a write instruction: Read Instruction Code Register (RICR) and Write Instruction Code Register (WICR). ICR/RICR/WICR have identical fields. Tested with sst26vf064b jedec,spi-nor flash. Backward compatibility test done on sama5d2 qspi controller and mx25l25635e jedec,spi-nor flash. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Tudor Ambarus
Mark Brown
parent
3a6c501e96
commit
2e5c888873
@ -19,6 +19,7 @@
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/spi/spi-mem.h>
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@ -35,7 +36,9 @@
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#define QSPI_IAR 0x0030 /* Instruction Address Register */
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#define QSPI_ICR 0x0034 /* Instruction Code Register */
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#define QSPI_WICR 0x0034 /* Write Instruction Code Register */
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#define QSPI_IFR 0x0038 /* Instruction Frame Register */
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#define QSPI_RICR 0x003C /* Read Instruction Code Register */
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#define QSPI_SMR 0x0040 /* Scrambling Mode Register */
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#define QSPI_SKR 0x0044 /* Scrambling Key Register */
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@ -88,7 +91,7 @@
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#define QSPI_SCR_DLYBS_MASK GENMASK(23, 16)
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#define QSPI_SCR_DLYBS(n) (((n) << 16) & QSPI_SCR_DLYBS_MASK)
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/* Bitfields in QSPI_ICR (Instruction Code Register) */
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/* Bitfields in QSPI_ICR (Read/Write Instruction Code Register) */
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#define QSPI_ICR_INST_MASK GENMASK(7, 0)
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#define QSPI_ICR_INST(inst) (((inst) << 0) & QSPI_ICR_INST_MASK)
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#define QSPI_ICR_OPT_MASK GENMASK(23, 16)
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@ -118,6 +121,7 @@
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#define QSPI_IFR_CRM BIT(14)
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#define QSPI_IFR_NBDUM_MASK GENMASK(20, 16)
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#define QSPI_IFR_NBDUM(n) (((n) << 16) & QSPI_IFR_NBDUM_MASK)
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#define QSPI_IFR_APBTFRTYP_READ BIT(24) /* Defined in SAM9X60 */
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/* Bitfields in QSPI_SMR (Scrambling Mode Register) */
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#define QSPI_SMR_SCREN BIT(0)
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@ -133,12 +137,18 @@
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#define QSPI_WPSR_WPVSRC_MASK GENMASK(15, 8)
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#define QSPI_WPSR_WPVSRC(src) (((src) << 8) & QSPI_WPSR_WPVSRC)
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struct atmel_qspi_caps {
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bool has_qspick;
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bool has_ricr;
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};
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struct atmel_qspi {
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void __iomem *regs;
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void __iomem *mem;
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struct clk *pclk;
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struct clk *qspick;
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struct platform_device *pdev;
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const struct atmel_qspi_caps *caps;
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u32 pending;
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u32 mr;
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struct completion cmd_completion;
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@ -151,7 +161,7 @@ struct atmel_qspi_mode {
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u32 config;
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};
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static const struct atmel_qspi_mode sama5d2_qspi_modes[] = {
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static const struct atmel_qspi_mode atmel_qspi_modes[] = {
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{ 1, 1, 1, QSPI_IFR_WIDTH_SINGLE_BIT_SPI },
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{ 1, 1, 2, QSPI_IFR_WIDTH_DUAL_OUTPUT },
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{ 1, 1, 4, QSPI_IFR_WIDTH_QUAD_OUTPUT },
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@ -180,8 +190,8 @@ static int atmel_qspi_find_mode(const struct spi_mem_op *op)
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{
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u32 i;
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for (i = 0; i < ARRAY_SIZE(sama5d2_qspi_modes); i++)
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if (atmel_qspi_is_compatible(op, &sama5d2_qspi_modes[i]))
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for (i = 0; i < ARRAY_SIZE(atmel_qspi_modes); i++)
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if (atmel_qspi_is_compatible(op, &atmel_qspi_modes[i]))
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return i;
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return -ENOTSUPP;
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@ -201,36 +211,37 @@ static bool atmel_qspi_supports_op(struct spi_mem *mem,
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return true;
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}
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static int atmel_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
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static int atmel_qspi_set_cfg(struct atmel_qspi *aq,
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const struct spi_mem_op *op, u32 *offset)
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{
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struct atmel_qspi *aq = spi_controller_get_devdata(mem->spi->master);
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int mode;
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u32 iar, icr, ifr;
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u32 dummy_cycles = 0;
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u32 iar, icr, ifr, sr;
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int err = 0;
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int mode;
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iar = 0;
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icr = QSPI_ICR_INST(op->cmd.opcode);
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ifr = QSPI_IFR_INSTEN;
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/*
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* If the QSPI controller is set in regular SPI mode, set it in
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* Serial Memory Mode (SMM).
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*/
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if (aq->mr != QSPI_MR_SMM) {
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writel_relaxed(QSPI_MR_SMM, aq->regs + QSPI_MR);
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aq->mr = QSPI_MR_SMM;
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}
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mode = atmel_qspi_find_mode(op);
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if (mode < 0)
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return mode;
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ifr |= sama5d2_qspi_modes[mode].config;
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ifr |= atmel_qspi_modes[mode].config;
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if (op->dummy.buswidth && op->dummy.nbytes)
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dummy_cycles = op->dummy.nbytes * 8 / op->dummy.buswidth;
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/*
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* The controller allows 24 and 32-bit addressing while NAND-flash
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* requires 16-bit long. Handling 8-bit long addresses is done using
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* the option field. For the 16-bit addresses, the workaround depends
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* of the number of requested dummy bits. If there are 8 or more dummy
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* cycles, the address is shifted and sent with the first dummy byte.
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* Otherwise opcode is disabled and the first byte of the address
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* contains the command opcode (works only if the opcode and address
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* use the same buswidth). The limitation is when the 16-bit address is
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* used without enough dummy cycles and the opcode is using a different
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* buswidth than the address.
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*/
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if (op->addr.buswidth) {
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switch (op->addr.nbytes) {
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case 0:
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@ -264,6 +275,9 @@ static int atmel_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
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}
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}
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/* offset of the data access in the QSPI memory space */
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*offset = iar;
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/* Set number of dummy cycles */
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if (dummy_cycles)
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ifr |= QSPI_IFR_NBDUM(dummy_cycles);
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@ -272,16 +286,51 @@ static int atmel_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
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if (op->data.nbytes)
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ifr |= QSPI_IFR_DATAEN;
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if (op->data.dir == SPI_MEM_DATA_OUT)
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ifr |= QSPI_IFR_SAMA5D2_WRITE_TRSFR;
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/*
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* If the QSPI controller is set in regular SPI mode, set it in
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* Serial Memory Mode (SMM).
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*/
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if (aq->mr != QSPI_MR_SMM) {
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writel_relaxed(QSPI_MR_SMM, aq->regs + QSPI_MR);
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aq->mr = QSPI_MR_SMM;
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}
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/* Clear pending interrupts */
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(void)readl_relaxed(aq->regs + QSPI_SR);
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/* Set QSPI Instruction Frame registers */
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writel_relaxed(iar, aq->regs + QSPI_IAR);
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writel_relaxed(icr, aq->regs + QSPI_ICR);
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writel_relaxed(ifr, aq->regs + QSPI_IFR);
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if (aq->caps->has_ricr) {
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if (!op->addr.nbytes && op->data.dir == SPI_MEM_DATA_IN)
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ifr |= QSPI_IFR_APBTFRTYP_READ;
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/* Set QSPI Instruction Frame registers */
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writel_relaxed(iar, aq->regs + QSPI_IAR);
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if (op->data.dir == SPI_MEM_DATA_IN)
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writel_relaxed(icr, aq->regs + QSPI_RICR);
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else
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writel_relaxed(icr, aq->regs + QSPI_WICR);
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writel_relaxed(ifr, aq->regs + QSPI_IFR);
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} else {
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if (op->data.dir == SPI_MEM_DATA_OUT)
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ifr |= QSPI_IFR_SAMA5D2_WRITE_TRSFR;
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/* Set QSPI Instruction Frame registers */
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writel_relaxed(iar, aq->regs + QSPI_IAR);
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writel_relaxed(icr, aq->regs + QSPI_ICR);
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writel_relaxed(ifr, aq->regs + QSPI_IFR);
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}
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return 0;
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}
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static int atmel_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
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{
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struct atmel_qspi *aq = spi_controller_get_devdata(mem->spi->master);
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u32 sr, offset;
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int err;
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err = atmel_qspi_set_cfg(aq, op, &offset);
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if (err)
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return err;
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/* Skip to the final steps if there is no data */
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if (op->data.nbytes) {
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@ -290,11 +339,11 @@ static int atmel_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
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/* Send/Receive data */
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if (op->data.dir == SPI_MEM_DATA_IN)
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_memcpy_fromio(op->data.buf.in,
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aq->mem + iar, op->data.nbytes);
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_memcpy_fromio(op->data.buf.in, aq->mem + offset,
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op->data.nbytes);
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else
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_memcpy_toio(aq->mem + iar,
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op->data.buf.out, op->data.nbytes);
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_memcpy_toio(aq->mem + offset, op->data.buf.out,
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op->data.nbytes);
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/* Release the chip-select */
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writel_relaxed(QSPI_CR_LASTXFER, aq->regs + QSPI_CR);
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@ -450,28 +499,55 @@ static int atmel_qspi_probe(struct platform_device *pdev)
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goto exit;
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}
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aq->caps = of_device_get_match_data(&pdev->dev);
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if (!aq->caps) {
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dev_err(&pdev->dev, "Could not retrieve QSPI caps\n");
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err = -EINVAL;
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goto exit;
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}
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if (aq->caps->has_qspick) {
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/* Get the QSPI system clock */
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aq->qspick = devm_clk_get(&pdev->dev, "qspick");
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if (IS_ERR(aq->qspick)) {
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dev_err(&pdev->dev, "missing system clock\n");
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err = PTR_ERR(aq->qspick);
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goto disable_pclk;
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}
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/* Enable the QSPI system clock */
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err = clk_prepare_enable(aq->qspick);
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if (err) {
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dev_err(&pdev->dev,
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"failed to enable the QSPI system clock\n");
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goto disable_pclk;
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}
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}
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/* Request the IRQ */
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irq = platform_get_irq(pdev, 0);
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if (irq < 0) {
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dev_err(&pdev->dev, "missing IRQ\n");
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err = irq;
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goto disable_pclk;
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goto disable_qspick;
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}
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err = devm_request_irq(&pdev->dev, irq, atmel_qspi_interrupt,
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0, dev_name(&pdev->dev), aq);
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if (err)
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goto disable_pclk;
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goto disable_qspick;
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err = atmel_qspi_init(aq);
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if (err)
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goto disable_pclk;
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goto disable_qspick;
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err = spi_register_controller(ctrl);
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if (err)
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goto disable_pclk;
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goto disable_qspick;
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return 0;
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disable_qspick:
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clk_disable_unprepare(aq->qspick);
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disable_pclk:
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clk_disable_unprepare(aq->pclk);
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exit:
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@ -487,6 +563,7 @@ static int atmel_qspi_remove(struct platform_device *pdev)
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spi_unregister_controller(ctrl);
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writel_relaxed(QSPI_CR_QSPIDIS, aq->regs + QSPI_CR);
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clk_disable_unprepare(aq->qspick);
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clk_disable_unprepare(aq->pclk);
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return 0;
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}
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@ -495,6 +572,7 @@ static int __maybe_unused atmel_qspi_suspend(struct device *dev)
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{
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struct atmel_qspi *aq = dev_get_drvdata(dev);
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clk_disable_unprepare(aq->qspick);
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clk_disable_unprepare(aq->pclk);
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return 0;
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@ -505,6 +583,7 @@ static int __maybe_unused atmel_qspi_resume(struct device *dev)
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struct atmel_qspi *aq = dev_get_drvdata(dev);
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clk_prepare_enable(aq->pclk);
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clk_prepare_enable(aq->qspick);
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return atmel_qspi_init(aq);
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}
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@ -512,8 +591,22 @@ static int __maybe_unused atmel_qspi_resume(struct device *dev)
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static SIMPLE_DEV_PM_OPS(atmel_qspi_pm_ops, atmel_qspi_suspend,
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atmel_qspi_resume);
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static const struct atmel_qspi_caps atmel_sama5d2_qspi_caps = {};
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static const struct atmel_qspi_caps atmel_sam9x60_qspi_caps = {
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.has_qspick = true,
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.has_ricr = true,
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};
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static const struct of_device_id atmel_qspi_dt_ids[] = {
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{ .compatible = "atmel,sama5d2-qspi" },
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{
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.compatible = "atmel,sama5d2-qspi",
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.data = &atmel_sama5d2_qspi_caps,
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},
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{
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.compatible = "microchip,sam9x60-qspi",
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.data = &atmel_sam9x60_qspi_caps,
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},
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{ /* sentinel */ }
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};
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