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[MIPS] rbtx4938: Fix secondary PCIC and glue internal NICs
* Fix pci ops for secondary PCIC * Do not reserve 1MB for PCI MEM region (leave PCIBIOS_MIN_MEM zero) * Use platform_device to provide ethernet addresses for internal NICs. (background: TX49XX SoCs include PCI NIC (TC35815 compatible) connected via its internal PCI bus, but the NIC's PROM interface is not connected to SEEPROM. So we must provide its ethernet address by another way.) * Check return value of early_read_config_word() Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Atsushi Nemoto
Ralf Baechle
parent
bd43da8ff1
commit
2db30150fe
@ -46,50 +46,63 @@ struct resource tx4938_pcic1_pci_mem_resource = {
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.flags = IORESOURCE_MEM
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};
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static int mkaddr(int bus, int dev_fn, int where, int *flagsp)
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static int mkaddr(int bus, int dev_fn, int where,
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struct tx4938_pcic_reg *pcicptr)
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{
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if (bus > 0) {
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/* Type 1 configuration */
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tx4938_pcicptr->g2pcfgadrs = ((bus & 0xff) << 0x10) |
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pcicptr->g2pcfgadrs = ((bus & 0xff) << 0x10) |
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((dev_fn & 0xff) << 0x08) | (where & 0xfc) | 1;
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} else {
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if (dev_fn >= PCI_DEVFN(TX4938_PCIC_MAX_DEVNU, 0))
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return -1;
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/* Type 0 configuration */
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tx4938_pcicptr->g2pcfgadrs = ((bus & 0xff) << 0x10) |
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pcicptr->g2pcfgadrs = ((bus & 0xff) << 0x10) |
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((dev_fn & 0xff) << 0x08) | (where & 0xfc);
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}
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/* clear M_ABORT and Disable M_ABORT Int. */
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tx4938_pcicptr->pcistatus =
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(tx4938_pcicptr->pcistatus & 0x0000ffff) |
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pcicptr->pcistatus =
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(pcicptr->pcistatus & 0x0000ffff) |
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(PCI_STATUS_REC_MASTER_ABORT << 16);
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tx4938_pcicptr->pcimask &= ~PCI_STATUS_REC_MASTER_ABORT;
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pcicptr->pcimask &= ~PCI_STATUS_REC_MASTER_ABORT;
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return 0;
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}
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static int check_abort(int flags)
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static int check_abort(struct tx4938_pcic_reg *pcicptr)
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{
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int code = PCIBIOS_SUCCESSFUL;
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/* wait write cycle completion before checking error status */
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while (tx4938_pcicptr->pcicstatus & TX4938_PCIC_PCICSTATUS_IWB)
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while (pcicptr->pcicstatus & TX4938_PCIC_PCICSTATUS_IWB)
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;
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if (tx4938_pcicptr->pcistatus & (PCI_STATUS_REC_MASTER_ABORT << 16)) {
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tx4938_pcicptr->pcistatus =
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(tx4938_pcicptr->
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if (pcicptr->pcistatus & (PCI_STATUS_REC_MASTER_ABORT << 16)) {
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pcicptr->pcistatus =
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(pcicptr->
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pcistatus & 0x0000ffff) | (PCI_STATUS_REC_MASTER_ABORT
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<< 16);
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tx4938_pcicptr->pcimask |= PCI_STATUS_REC_MASTER_ABORT;
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pcicptr->pcimask |= PCI_STATUS_REC_MASTER_ABORT;
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code = PCIBIOS_DEVICE_NOT_FOUND;
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}
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return code;
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}
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extern struct pci_controller tx4938_pci_controller[];
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extern struct tx4938_pcic_reg *get_tx4938_pcicptr(int ch);
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static struct tx4938_pcic_reg *pci_bus_to_pcicptr(struct pci_bus *bus)
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{
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struct pci_controller *channel = bus->sysdata;
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return get_tx4938_pcicptr(channel - &tx4938_pci_controller[0]);
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}
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static int tx4938_pcibios_read_config(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 * val)
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{
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int flags, retval, dev, busno, func;
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int retval, dev, busno, func;
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struct tx4938_pcic_reg *pcicptr = pci_bus_to_pcicptr(bus);
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void __iomem *cfgdata =
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(void __iomem *)(unsigned long)&pcicptr->g2pcfgdata;
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dev = PCI_SLOT(devfn);
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func = PCI_FUNC(devfn);
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@ -101,32 +114,32 @@ static int tx4938_pcibios_read_config(struct pci_bus *bus, unsigned int devfn,
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busno = 0;
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}
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if (mkaddr(busno, devfn, where, &flags))
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if (mkaddr(busno, devfn, where, pcicptr))
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return -1;
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switch (size) {
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case 1:
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*val = *(volatile u8 *) ((unsigned long) & tx4938_pcicptr->g2pcfgdata |
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#ifdef __BIG_ENDIAN
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((where & 3) ^ 3));
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cfgdata += (where & 3) ^ 3;
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#else
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(where & 3));
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cfgdata += where & 3;
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#endif
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*val = __raw_readb(cfgdata);
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break;
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case 2:
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*val = *(volatile u16 *) ((unsigned long) & tx4938_pcicptr->g2pcfgdata |
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#ifdef __BIG_ENDIAN
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((where & 3) ^ 2));
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cfgdata += (where & 2) ^ 2;
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#else
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(where & 3));
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cfgdata += where & 2;
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#endif
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*val = __raw_readw(cfgdata);
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break;
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case 4:
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*val = tx4938_pcicptr->g2pcfgdata;
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*val = __raw_readl(cfgdata);
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break;
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}
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retval = check_abort(flags);
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retval = check_abort(pcicptr);
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if (retval == PCIBIOS_DEVICE_NOT_FOUND)
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*val = 0xffffffff;
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@ -136,7 +149,10 @@ static int tx4938_pcibios_read_config(struct pci_bus *bus, unsigned int devfn,
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static int tx4938_pcibios_write_config(struct pci_bus *bus, unsigned int devfn, int where,
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int size, u32 val)
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{
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int flags, dev, busno, func;
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int dev, busno, func;
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struct tx4938_pcic_reg *pcicptr = pci_bus_to_pcicptr(bus);
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void __iomem *cfgdata =
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(void __iomem *)(unsigned long)&pcicptr->g2pcfgdata;
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busno = bus->number;
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dev = PCI_SLOT(devfn);
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@ -149,32 +165,32 @@ static int tx4938_pcibios_write_config(struct pci_bus *bus, unsigned int devfn,
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busno = 0;
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}
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if (mkaddr(busno, devfn, where, &flags))
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if (mkaddr(busno, devfn, where, pcicptr))
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return -1;
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switch (size) {
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case 1:
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*(volatile u8 *) ((unsigned long) & tx4938_pcicptr->g2pcfgdata |
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#ifdef __BIG_ENDIAN
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((where & 3) ^ 3)) = val;
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cfgdata += (where & 3) ^ 3;
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#else
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(where & 3)) = val;
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cfgdata += where & 3;
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#endif
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__raw_writeb(val, cfgdata);
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break;
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case 2:
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*(volatile u16 *) ((unsigned long) & tx4938_pcicptr->g2pcfgdata |
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#ifdef __BIG_ENDIAN
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((where & 0x3) ^ 0x2)) = val;
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cfgdata += (where & 2) ^ 2;
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#else
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(where & 3)) = val;
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cfgdata += where & 2;
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#endif
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__raw_writew(val, cfgdata);
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break;
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case 4:
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tx4938_pcicptr->g2pcfgdata = val;
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__raw_writel(val, cfgdata);
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break;
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}
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return check_abort(flags);
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return check_abort(pcicptr);
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}
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struct pci_ops tx4938_pci_ops = {
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@ -352,7 +352,7 @@ static struct pci_dev *fake_pci_dev(struct pci_controller *hose,
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static struct pci_dev dev;
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static struct pci_bus bus;
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dev.sysdata = (void *)hose;
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dev.sysdata = bus.sysdata = hose;
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dev.devfn = devfn;
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bus.number = busnr;
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bus.ops = hose->pci_ops;
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@ -385,8 +385,10 @@ int txboard_pci66_check(struct pci_controller *hose, int top_bus, int current_bu
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printk("PCI: Checking 66MHz capabilities...\n");
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for (pci_devfn=devfn_start; pci_devfn<devfn_stop; pci_devfn++) {
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early_read_config_word(hose, top_bus, current_bus, pci_devfn,
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PCI_VENDOR_ID, &vid);
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if (early_read_config_word(hose, top_bus, current_bus,
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pci_devfn, PCI_VENDOR_ID,
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&vid) != PCIBIOS_SUCCESSFUL)
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continue;
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if (vid == 0xffff) continue;
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@ -463,7 +465,6 @@ static int __init tx4938_pcibios_init(void)
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int extarb = !(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIXARB);
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PCIBIOS_MIN_IO = 0x00001000UL;
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PCIBIOS_MIN_MEM = 0x01000000UL;
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mem_base[0] = txboard_request_phys_region_shrink(&mem_size[0]);
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io_base[0] = txboard_request_phys_region_shrink(&io_size[0]);
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@ -578,18 +579,17 @@ arch_initcall(tx4938_pcibios_init);
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#define SRTC_CS 2 /* IOC */
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#ifdef CONFIG_PCI
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static unsigned char rbtx4938_ethaddr[17];
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static int __init rbtx4938_ethaddr_init(void)
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{
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unsigned char dat[17];
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unsigned char sum;
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int i;
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/* 0-3: "MAC\0", 4-9:eth0, 10-15:eth1, 16:sum */
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if (spi_eeprom_read(SEEPROM1_CS, 0,
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rbtx4938_ethaddr, sizeof(rbtx4938_ethaddr)))
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if (spi_eeprom_read(SEEPROM1_CS, 0, dat, sizeof(dat))) {
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printk(KERN_ERR "seeprom: read error.\n");
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else {
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unsigned char *dat = rbtx4938_ethaddr;
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return -ENODEV;
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} else {
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if (strcmp(dat, "MAC") != 0)
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printk(KERN_WARNING "seeprom: bad signature.\n");
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for (i = 0, sum = 0; i < sizeof(dat); i++)
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@ -597,31 +597,22 @@ static int __init rbtx4938_ethaddr_init(void)
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if (sum)
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printk(KERN_WARNING "seeprom: bad checksum.\n");
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}
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for (i = 0; i < 2; i++) {
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unsigned int slot = TX4938_PCIC_IDSEL_AD_TO_SLOT(31 - i);
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unsigned int id = (1 << 8) | PCI_DEVFN(slot, 0); /* bus 1 */
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struct platform_device *pdev;
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if (!(tx4938_ccfgptr->pcfg &
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(i ? TX4938_PCFG_ETH1_SEL : TX4938_PCFG_ETH0_SEL)))
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continue;
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pdev = platform_device_alloc("tc35815-mac", id);
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if (!pdev ||
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platform_device_add_data(pdev, &dat[4 + 6 * i], 6) ||
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platform_device_add(pdev))
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platform_device_put(pdev);
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}
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return 0;
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}
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device_initcall(rbtx4938_ethaddr_init);
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int rbtx4938_get_tx4938_ethaddr(struct pci_dev *dev, unsigned char *addr)
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{
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struct pci_controller *channel = (struct pci_controller *)dev->bus->sysdata;
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int ch = 0;
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if (channel != &tx4938_pci_controller[1])
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return -ENODEV;
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/* TX4938 PCIC1 */
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switch (PCI_SLOT(dev->devfn)) {
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case TX4938_PCIC_IDSEL_AD_TO_SLOT(31):
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ch = 0;
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break;
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case TX4938_PCIC_IDSEL_AD_TO_SLOT(30):
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ch = 1;
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break;
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default:
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return -ENODEV;
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}
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memcpy(addr, &rbtx4938_ethaddr[4 + 6 * ch], 6);
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return 0;
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}
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#endif /* CONFIG_PCI */
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static void __init rbtx4938_spi_setup(void)
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